Searched +full:280 +full:mhz (Results 1 – 9 of 9) sorted by relevance
20 clock-frequency = <DT_FREQ_M(280)>; /* SYSCLK runs at 280MHz */
94 /* PLL1P is used for system clock (280 MHz), PLL1Q is used for FDCAN bit quantum clock (80 MHz) */97 mul-n = <280>;105 /* PLL3R is used for outputting 9 MHz pixel clock for LTDC */118 clock-frequency = <DT_FREQ_M(280)>;
56 /* PLL1P is used for system clock (280 MHz) */69 clock-frequency = <DT_FREQ_M(280)>;
35 - 280 MHz max CPU frequency39 - Main clock: External 25MHz crystal oscillator.119 as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 280MHz,120 driven by an 25MHz external crystal oscillator.
69 clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */85 clock-frequency = <DT_FREQ_M(280)>;
17 - 32.768 kHz and 25MHz HSE crystal oscillators40 - 280 MHz max CPU frequency130 by the PLL clock at 280MHz. PLL clock is fed by a 25MHz high speed external clock.
59 - 280 MHz max CPU frequency179 by the PLL clock at 280MHz. PLL clock is fed by a 24MHz high speed external clock.
53 - 280 MHz max CPU frequency133 driven by the PLL clock at 96MHz, driven by an 8MHz high-speed external clock.
113 /* All h7 SoC with maximum 480MHz SYSCLK */121 /* All h7 SoC with maximum 550MHz SYSCLK */132 /* All h7RS SoC with maximum 500MHz SYSCLK (refer to Datasheet DS14359 rev 1) */137 /* Default: All h7 SoC with maximum 280MHz SYSCLK */330 if (MHZ(1) <= vco_freq && vco_freq <= MHZ(2)) {332 } else if (MHZ(2) < vco_freq && vco_freq <= MHZ(4)) {334 } else if (MHZ(4) < vco_freq && vco_freq <= MHZ(8)) {336 } else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) {816 /* Can be HSE , HSI 64Mhz/HSIDIV, CSI 4MHz*/
