| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32l0-pll-clock.yaml | 8 input frequency from 2 to 24 MHz.
16 The PLL output frequency must not exceed 32 MHz.
45 - 96 MHz when the product is in Range 1
46 - 48 MHz when the product is in Range 2
47 - 24 MHz when the product is in Range 3
49 programmed to output a 96 MHz frequency (USBCLK = PLLVCO/2).
57 - 24
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| D | st,stm32u5-msi-clock.yaml | 22 - 0 # range 0 around 48 MHz
23 - 1 # range 1 around 24 MHz
24 - 2 # range 2 around 16 MHz
25 - 3 # range 3 around 12 MHz
26 - 4 # range 4 around 4 MHz (reset value)
27 - 5 # range 5 around 2 MHz
28 - 6 # range 6 around 1.33 MHz
29 - 7 # range 7 around 1 MHz
30 - 8 # range 8 around 3.072 MHz
31 - 9 # range 9 around 1.536 MHz
[all …]
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| D | st,stm32-msi-clock.yaml | 23 - 5 # range 5 around 2 MHz
24 - 6 # range 6 around 4 MHz (reset value)
25 - 7 # range 7 around 8 MHz
26 - 8 # range 8 around 16 MHz
27 - 9 # range 9 around 24 MHz
28 - 10 # range 10 around 32 MHz
29 - 11 # range 11 around 48 MHz
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| D | st,stm32c0-hsi-clock.yaml | 6 On STM32C0, HSI is a 48MHz fixed clock.
12 - 1 ==> HSISYS = 48MHZ
13 - 2 ==> HSISYS = 24MHZ
14 - 4 ==> HSISYS = 12MHZ
15 - 8 ==> HSISYS = 6MHZ
16 - 16 ==> HSISYS = 3MHZ
17 - 32 ==> HSISYS = 1.5MHz
18 - 64 ==> HSISYS = 0.75MHZ
19 - 128 ==> HSISYS = 0.375MHz
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| D | nuvoton,numaker-scc.yaml | 17 Enable/disable 4~24 MHz external crystal oscillator (HXT)
35 Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48)
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| /Zephyr-latest/soc/ene/kb1200/ |
| D | soc.c | 31 /* AHB/APB clock select 96MHz/48MHz */ in clock_init()
34 /* AHB/APB clock select 48MHz/24MHz */ in clock_init()
37 /* AHB/APB clock select 24MHz/12MHz */ in clock_init()
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | soc.c | 55 pllfreq = MHZ(8); in chip_get_pll_freq()
58 pllfreq = MHZ(16); in chip_get_pll_freq()
61 pllfreq = MHZ(24); in chip_get_pll_freq()
64 pllfreq = MHZ(32); in chip_get_pll_freq()
67 pllfreq = MHZ(48); in chip_get_pll_freq()
70 pllfreq = MHZ(64); in chip_get_pll_freq()
73 pllfreq = MHZ(72); in chip_get_pll_freq()
76 pllfreq = MHZ(96); in chip_get_pll_freq()
121 * PLL frequency setting = 4 (48MHz)
122 * MCU div = 0 (PLL / 1 = 48 mhz)
[all …]
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| D | Kconfig | 105 bool "Flash frequency is 48MHz"
109 Change frequency of PLL, CPU, and flash to 48MHz during initialization.
112 (PLL and CPU run at 48MHz, flash frequency is 16MHz)
140 bool "EC bus is 24MHz"
142 Raise EC bus to 24MHz (default is 8MHz).
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/ |
| D | hse_24.overlay | 13 clock-frequency = <DT_FREQ_M(24)>; /* 24MHz clock */
19 clock-frequency = <DT_FREQ_M(24)>;
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| /Zephyr-latest/soc/nxp/imx/imx8m/m4_mini/ |
| D | soc.c | 77 * Switch AHB NOC root to 24M first in order to configure in SOC_ClockInit()
83 * Switch AXI M4 root to 24M first in order to configure in SOC_ClockInit()
98 /* Switch AHB to SYSTEM PLL1 DIV6 = 133MHZ */ in SOC_ClockInit()
101 /* Set root clock to 800MHZ/ 2= 400MHZ */ in SOC_ClockInit()
108 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
110 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
114 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
116 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
120 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
122 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
[all …]
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| /Zephyr-latest/tests/benchmarks/latency_measure/boards/ |
| D | frdm_k64f.conf | 2 # allow for a tickless kernel given its 24-bit timer and its 120 MHz
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| /Zephyr-latest/boards/seagate/legend/ |
| D | legend_stm32f070xb_25ssd.overlay | 13 clock-frequency = <DT_FREQ_M(24)>; /* 24MHz external clock */
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| D | legend_stm32f070xb_35.overlay | 27 clock-frequency = <DT_FREQ_M(24)>; /* 24MHz external clock */
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/boards/ |
| D | pll_hsi_96.overlay | 13 hsi-div = <8>; /* HSI RC: 64MHz, hsi_clk = 8MHz */
19 mul-n = <24>;
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| /Zephyr-latest/soc/nxp/imx/imx8m/m7/ |
| D | soc.c | 64 .postDiv = 2U, /*!< SYSTEM PLL1 frequency = 800MHZ */
72 .postDiv = 1U, /*!< SYSTEM PLL2 frequency = 1000MHZ */
80 .postDiv = 2U, /*!< SYSTEM PLL3 frequency = 600MHZ */
88 * to 800Mhz when power up the SOC, meanwhile A core would enable SYSTEM PLL1, SYSTEM PLL2 in SOC_ClockInit()
93 /* switch AHB NOC root to 24M first in order to configure the SYSTEM PLL1. */ in SOC_ClockInit()
96 /* switch AXI M7 root to 24M first in order to configure the SYSTEM PLL2. */ in SOC_ClockInit()
104 /* Set root clock freq to 133M / 1= 133MHZ */ in SOC_ClockInit()
111 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
113 /* Set root clock to 80MHZ/ 1= 80MHZ */ in SOC_ClockInit()
117 /* Set UART source to SysPLL1 Div10 80MHZ */ in SOC_ClockInit()
[all …]
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| /Zephyr-latest/boards/shields/st_b_lcd40_dsi1_mb1166/boards/ |
| D | stm32h747i_disco_stm32h747xx_m7.overlay | 28 div-r = <24>; /* 27.5 MHz */
37 * = 25 MHz / 5 * 2 * 100 / 2 / (1<<0) / 8 = 62.5 MHz
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| /Zephyr-latest/boards/arm/v2m_beetle/ |
| D | v2m_beetle_defconfig | 12 # 24MHz system clock
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| /Zephyr-latest/soc/atmel/sam/same70/ |
| D | soc.c | 36 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
68 * rather than maximum supported 150 MHz at standard VDDIO=2.7V in clock_init()
79 * By default, MULA == 24, DIVA == 1. in clock_init()
80 * With main crystal running at 12 MHz, in clock_init()
81 * PLL = 12 * (24 + 1) / 1 = 300 MHz in clock_init()
84 * Processor Clock (HCLK)=300 MHz. in clock_init()
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| /Zephyr-latest/soc/atmel/sam/samv71/ |
| D | soc.c | 34 /* Switch the main clock to the internal OSC with 12MHz */ in clock_init()
66 * rather than maximum supported 150 MHz at standard VDDIO=2.7V in clock_init()
77 * By default, MULA == 24, DIVA == 1. in clock_init()
78 * With main crystal running at 12 MHz, in clock_init()
79 * PLL = 12 * (24 + 1) / 1 = 300 MHz in clock_init()
82 * Processor Clock (HCLK)=300 MHz. in clock_init()
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| /Zephyr-latest/boards/up-bridge-the-gap/up_squared/ |
| D | Kconfig.defconfig | 12 # TSC on this board is 1.5936 GHz, HPET and APIC are 19.2 MHz
20 default 24
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| /Zephyr-latest/soc/arm/beetle/ |
| D | soc_pll.h | 23 * - PLL_FEEDDIV [30:24]
27 * The Fin = 24Mhz on Beetle
35 * PLL_FEEDDIV = 2*(R[30:24] + 1)
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| /Zephyr-latest/boards/intel/ehl/ |
| D | Kconfig.defconfig | 21 # TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
29 default 24
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| /Zephyr-latest/tests/kernel/timer/starve/ |
| D | README.txt | 21 24-bit resolution and determines elapsed time by a 24-bit unsigned
26 Systems that use a 32-bit counter of 80 MHz ticks would fail after
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| /Zephyr-latest/soc/microchip/mec/ |
| D | Kconfig | 37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
54 default 24 if MCHP_MEC_HEADER_SPI_FREQ_MHZ_24
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
268 and main 96 MHz clock (MCK):
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| /Zephyr-latest/boards/up-bridge-the-gap/up_squared_pro_7000/ |
| D | Kconfig.defconfig | 12 # TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
21 default 24
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