Home
last modified time | relevance | path

Searched +full:24 +full:- +full:bit (Results 1 – 25 of 553) sorted by relevance

12345678910>>...23

/Zephyr-latest/include/zephyr/bluetooth/
Dbyteorder.h8 * SPDX-License-Identifier: Apache-2.0
26 /** @brief Encode 16-bit value into array values in little-endian format.
28 * Helper macro to encode 16-bit values into comma separated values.
32 * @param _v 16-bit integer in host endianness.
34 * @return The comma separated values for the 16-bit value.
40 /** @brief Encode 24-bit value into array values in little-endian format.
42 * Helper macro to encode 24-bit values into comma separated values.
46 * @param _v 24-bit integer in host endianness.
48 * @return The comma separated values for the 24-bit value.
54 /** @brief Encode 32-bit value into array values in little-endian format.
[all …]
/Zephyr-latest/dts/bindings/display/
Dnxp,dcnano-lcdif.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dcnano-lcdif"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
17 backlight-gpios:
18 type: phandle-array
23 data-bus-width:
25 default: "24-bit"
27 - "16-bit-config1" # 16 bit configuration 1. RGB565: XXXXXXXX_RRRRRGGG_GGGBBBBB
28 - "16-bit-config2" # 16 bit configuration 2. RGB565: XXXRRRRR_XXGGGGGG_XXXBBBBB
29 - "16-bit-config3" # 16-bit configuration 3. RGB565: XXRRRRRX_XXGGGGGG_XXBBBBBX
[all …]
/Zephyr-latest/include/zephyr/sys/
Dbyteorder.h6 * Copyright (c) 2015-2016, Intel Corporation.
8 * SPDX-License-Identifier: Apache-2.0
23 #define BSWAP_32(x) ((uint32_t) ((((x) >> 24) & 0xff) | \
26 (((x) & 0xff) << 24)))
33 (((x) >> 24) & 0xff00) | \
36 (((x) & 0xff00) << 24) | \
40 (((x) >> 24) & 0xff0000) | \
43 (((x) & 0xff0000) << 24) | \
48 * @brief Convert 16-bit integer from little-endian to host endianness.
50 * @param val 16-bit integer in little-endian format.
[all …]
/Zephyr-latest/drivers/serial/
Duart_rzt2m.h4 * SPDX-License-Identifier: Apache-2.0
36 #define CCR0_MASK_RE BIT(0)
37 #define CCR0_MASK_TE BIT(4)
38 #define CCR0_MASK_DCME BIT(9)
39 #define CCR0_MASK_IDSEL BIT(10)
40 #define CCR0_MASK_RIE BIT(16)
41 #define CCR0_MASK_TIE BIT(20)
42 #define CCR0_MASK_TEIE BIT(21)
43 #define CCR0_MASK_SSE BIT(24)
45 #define CCR1_MASK_CTSE BIT(0)
[all …]
/Zephyr-latest/dts/bindings/mipi-dsi/
Dnxp,imx-mipi-dsi.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,imx-mipi-dsi"
10 include: mipi-dsi-host.yaml
22 dpi-color-coding:
25 - "16-bit-config-1"
26 - "16-bit-config-2"
27 - "16-bit-config-3"
28 - "18-bit-config-1"
29 - "18-bit-config-2"
30 - "24-bit"
[all …]
Dnxp,mipi-dsi-2l.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,mipi-dsi-2l"
10 include: mipi-dsi-host.yaml
21 dpi-color-coding:
24 - "16-bit-config-1"
25 - "16-bit-config-2"
26 - "16-bit-config-3"
27 - "18-bit-config-1"
28 - "18-bit-config-2"
29 - "24-bit"
[all …]
/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
89 #define MCP251XFD_REG_CON_ABAT BIT(27)
90 #define MCP251XFD_REG_CON_REQOP_MASK GENMASK(26, 24)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
102 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
104 #define MCP251XFD_REG_CON_RTXAT BIT(16)
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
[all …]
Dmec172x_espi_vw.h4 * SPDX-License-Identifier: Apache-2.0
13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
14 /* 32-bit word 0 (bits[31:0]) */
28 /* 32-bit word 1 (bits[63:32]) */
37 #define ESPI_M2SW1_SRC3_SEL_POS 24
43 /* 32-bit word 2 (bits[95:64]) */
52 #define ESPI_M2SW2_SRC3_POS 24u
77 /* Slave to Master VW register: 64-bit (2 32 bit registers) */
78 /* 32-bit word 0 (bits[31:0]) */
96 #define ESPI_S2MW0_CHG0 BIT(ESPI_S2MW0_CHG0_POS)
[all …]
Dmec172x_espi_saf.h4 * SPDX-License-Identifier: Apache-2.0
33 /* SAF Protection region described by 4 32-bit registers. 17 regions */
36 /* Register bit definitions */
54 #define MCHP_SAF_ECP_CMD_LEN_POS 24
62 #define MCHP_SAF_ECP_CMD_ERASE_32K BIT(24)
63 #define MCHP_SAF_ECP_CMD_ERASE_64K BIT(25)
82 #define MCHP_SAF_ECP_START BIT(0)
101 #define MCHP_SAF_ECP_STS_DONE BIT(0)
102 #define MCHP_SAF_ECP_STS_DONE_TST BIT(1)
103 #define MCHP_SAF_ECP_STS_TMOUT BIT(2)
[all …]
/Zephyr-latest/soc/renesas/rzt2m/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
16 #define CNTCR_EN BIT(0)
17 #define CNTCR_HDBG BIT(1)
20 #define PRCRS_CLK BIT(0)
21 #define PRCRS_LPC_RESET BIT(1)
22 #define PRCRS_GPIO BIT(2)
23 #define PRCRS_SYS_CTRL BIT(3)
25 /* Non-safety area protect register */
26 #define PRCRN_PRC0 BIT(0)
27 #define PRCRN_PRC1 BIT(1)
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
47 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
[all …]
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
46 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
[all …]
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
54 #define SSCR0_FRDC_GET(x) ((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
100 #define MAC_CONF_IPG GENMASK(26, 24)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
[all …]
/Zephyr-latest/drivers/memc/
Dsifive_ddr.c2 * (C) Copyright 2020-2021 SiFive, Inc.
5 * SPDX-License-Identifier: Apache-2.0
8 * https://github.com/sifive/freedom-u540-c000-bootloader
25 #define OPTIMAL_RMODW_EN BIT(0)
26 #define DISABLE_RD_INTERLEAVE BIT(16)
27 #define OUT_OF_RANGE BIT(1)
28 #define MULTIPLE_OUT_OF_RANGE BIT(2)
29 #define PORT_COMMAND_CHANNEL_ERROR BIT(7)
30 #define MC_INIT_COMPLETE BIT(8)
31 #define LEVELING_OPERATION_COMPLETED BIT(22)
[all …]
/Zephyr-latest/include/zephyr/
Dnet_buf.h8 * SPDX-License-Identifier: Apache-2.0
84 * The main use of this is for scenarios where the meta-data of the normal
123 * @return Pointer to stack-allocated net_buf_simple object.
145 if (!buf->__buf) { in net_buf_simple_init()
146 buf->__buf = (uint8_t *)buf + sizeof(*buf); in net_buf_simple_init()
149 buf->data = buf->__buf + reserve_head; in net_buf_simple_init()
150 buf->len = 0U; in net_buf_simple_init()
174 buf->len = 0U; in net_buf_simple_reset()
175 buf->data = buf->__buf; in net_buf_simple_reset()
220 * @brief Add (8-bit) byte at the end of the buffer
[all …]
/Zephyr-latest/drivers/i2c/
Di2c_andes_atciic100.h4 * SPDX-License-Identifier: Apache-2.0
31 ((const struct i2c_atciic100_config * const)(dev)->config)->base
47 #define IEN_CMPL BIT(9)
48 #define IEN_BYTE_RECV BIT(8)
49 #define IEN_BYTE_TRANS BIT(7)
50 #define IEN_START BIT(6)
51 #define IEN_STOP BIT(5)
52 #define IEN_ARB_LOSE BIT(4)
53 #define IEN_ADDR_HIT BIT(3)
54 #define IEN_FIFO_HALF BIT(2)
[all …]
/Zephyr-latest/include/zephyr/math/
Dilog2.h4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
[all …]
/Zephyr-latest/tests/kernel/timer/starve/
DREADME.txt20 For example a system that uses a 32768-Hz internal timer counter with
21 24-bit resolution and determines elapsed time by a 24-bit unsigned
22 difference between the current and last-recorded counter value will fail
26 Systems that use a 32-bit counter of 80 MHz ticks would fail after
/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.h3 * SPDX-License-Identifier: Apache-2.0
10 #define CDNS_HRS09_PHY_SW_RESET BIT(0)
11 #define CDNS_HRS09_PHY_INIT_COMP BIT(1)
12 #define CDNS_HRS09_EXT_WR_MODE BIT(3)
13 #define CDNS_HRS09_RDCMD_EN_BIT BIT(15)
14 #define CDNS_HRS09_RDDATA_EN_BIT BIT(16)
21 #define CDNS_HRS00_SWR BIT(0)
26 /* SRS09 - Present State Register */
27 #define CDNS_SRS09_STAT_DAT_BUSY BIT(2)
28 #define CDNS_SRS09_CI BIT(16)
[all …]
/Zephyr-latest/boards/shields/rk055hdmipi4ma0/
Drk055hdmipi4ma0.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/display/panel.h>
15 en_mipi_display_rk055hdmipi4ma0: enable-mipi-display-rk055hdmipi4ma0 {
16 compatible = "regulator-fixed";
17 regulator-name = "en_mipi_display";
18 enable-gpios = <&nxp_mipi_connector 32 GPIO_ACTIVE_HIGH>;
19 regulator-boot-on;
23 compatible = "zephyr,lvgl-pointer-input";
30 gt911_rk055hdmipi4ma0: gt911-rk055hdmipi4ma0@5d {
33 irq-gpios = <&nxp_mipi_connector 29 GPIO_ACTIVE_HIGH>;
[all …]
/Zephyr-latest/drivers/stepper/adi_tmc/
Dadi_tmc_reg.h9 * SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
10 * SPDX-License-Identifier: Apache-2.0
26 #define TMC5XXX_CLOCK_FREQ_SHIFT 24
36 #define TMC5XXX_SG_MIN_VALUE -64
38 #define TMC5XXX_SW_MODE_SG_STOP_ENABLE BIT(10)
55 #define TMC5XXX_CHOPCONF_MRES_MASK GENMASK(27, 24)
56 #define TMC5XXX_CHOPCONF_MRES_SHIFT 24
61 #define TMC5XXX_RAMPSTAT_POS_REACHED_EVENT_MASK BIT(7)
65 #define TMC5XXX_RAMPSTAT_STOP_SG_EVENT_MASK BIT(6)
69 #define TMC5XXX_RAMPSTAT_STOP_RIGHT_EVENT_MASK BIT(5)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dmchp-xec-ecia.h4 * SPDX-License-Identifier: Apache-2.0
10 * Encode peripheral interrupt information into a 32-bit unsigned.
12 * gb = bits[12:8], peripheral source bit position [0, 31] in the GIRQ
14 * nd = bits[31:24], direct NVIC number. For sources without a direct
21 (((nd) & 0xff) << 24))
27 #define MCHP_XEC_ECIA_NVIC_DIRECT(e) (((e) >> 24) & 0xff)
/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
52 * So based on a 24 mA maximum value each step is either
53 * 24/4 mA or 24/8 mA.
55 #define PFC_RCAR_DRIVE_MAX 24U
79 uint8_t bit = pin % 32; in pfc_rcar_set_gpsr() local
84 val |= BIT(bit); in pfc_rcar_set_gpsr()
86 val &= ~BIT(bit); in pfc_rcar_set_gpsr()
95 uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t); in pfc_rcar_set_ipsr()
98 val &= ~(0xFU << rcar_func->shift); in pfc_rcar_set_ipsr()
[all …]

12345678910>>...23