Lines Matching +full:24 +full:- +full:bit
4 * SPDX-License-Identifier: Apache-2.0
31 ((const struct i2c_atciic100_config * const)(dev)->config)->base
47 #define IEN_CMPL BIT(9)
48 #define IEN_BYTE_RECV BIT(8)
49 #define IEN_BYTE_TRANS BIT(7)
50 #define IEN_START BIT(6)
51 #define IEN_STOP BIT(5)
52 #define IEN_ARB_LOSE BIT(4)
53 #define IEN_ADDR_HIT BIT(3)
54 #define IEN_FIFO_HALF BIT(2)
55 #define IEN_FIFO_FULL BIT(1)
56 #define IEN_FIFO_EMPTY BIT(0)
60 #define STATUS_LINE_SDA BIT(14)
61 #define STATUS_LINE_SCL BIT(13)
62 #define STATUS_GEN_CALL BIT(12)
63 #define STATUS_BUS_BUSY BIT(11)
64 #define STATUS_ACK BIT(10)
65 #define STATUS_CMPL BIT(9)
66 #define STATUS_BYTE_RECV BIT(8)
67 #define STATUS_BYTE_TRANS BIT(7)
68 #define STATUS_START BIT(6)
69 #define STATUS_STOP BIT(5)
70 #define STATUS_ARB_LOSE BIT(4)
71 #define STATUS_ADDR_HIT BIT(3)
72 #define STATUS_FIFO_HALF BIT(2)
73 #define STATUS_FIFO_FULL BIT(1)
74 #define STATUS_FIFO_EMPTY BIT(0)
77 #define CTRL_PHASE_START BIT(12)
78 #define CTRL_PHASE_ADDR BIT(11)
79 #define CTRL_PHASE_DATA BIT(10)
80 #define CTRL_PHASE_STOP BIT(9)
81 #define CTRL_DIR BIT(8)
94 #define SETUP_T_SUDAT (BIT_MASK(5) << 24)
97 #define SETUP_T_SCL_RATIO BIT(13)
99 #define SETUP_DMA_EN BIT(3)
100 #define SETUP_CONTROLLER BIT(2)
101 #define SETUP_ADDRESSING BIT(1)
102 #define SETUP_I2C_EN BIT(0)
172 #define SETUP_SPEED_STD ((SETUP_T_SUDAT_STD << 24) | \
178 #define SETUP_SPEED_FAST ((SETUP_T_SUDAT_FAST << 24) | \
184 #define SETUP_SPEED_FAST_PLUS ((SETUP_T_SUDAT_FAST_P << 24) | \
202 I2C_DRV_INIT = BIT(0),
203 I2C_DRV_POWER = BIT(1),
204 I2C_DRV_CFG_PARAM = BIT(2),
205 I2C_DRV_CONTROLLER_TX = BIT(3),
206 I2C_DRV_CONTROLLER_RX = BIT(4),
207 I2C_DRV_TARGET_TX = BIT(5),
208 I2C_DRV_TARGET_RX = BIT(6),
209 I2C_DRV_CONTROLLER_TX_CMPL = BIT(7),
210 I2C_DRV_CONTROLLER_RX_CMPL = BIT(8),
211 I2C_DRV_TARGET_TX_CMPL = BIT(9),
212 I2C_DRV_TARGET_RX_CMPL = BIT(10),