Lines Matching +full:24 +full:- +full:bit

2  * (C) Copyright 2020-2021 SiFive, Inc.
5  * SPDX-License-Identifier: Apache-2.0
8  * https://github.com/sifive/freedom-u540-c000-bootloader
25 #define OPTIMAL_RMODW_EN		BIT(0)
26 #define DISABLE_RD_INTERLEAVE		BIT(16)
27 #define OUT_OF_RANGE			BIT(1)
28 #define MULTIPLE_OUT_OF_RANGE		BIT(2)
29 #define PORT_COMMAND_CHANNEL_ERROR	BIT(7)
30 #define MC_INIT_COMPLETE		BIT(8)
31 #define LEVELING_OPERATION_COMPLETED	BIT(22)
32 #define DFI_PHY_WRLELV_MODE		BIT(24)
33 #define DFI_PHY_RDLVL_MODE		BIT(24)
34 #define DFI_PHY_RDLVL_GATE_MODE		BIT(0)
35 #define VREF_EN				BIT(24)
36 #define PORT_ADDR_PROTECTION_EN		BIT(0)
37 #define AXI0_ADDRESS_RANGE_ENABLE	BIT(8)
38 #define AXI0_RANGE_PROT_BITS_0		(BIT(24) | BIT(25));
39 #define RDLVL_EN			BIT(16)
40 #define RDLVL_GATE_EN			BIT(24)
41 #define WRLVL_EN			BIT(0)
46 #define DDR_CTL_REG(d, i) (*(d->ddrctl + i))
47 #define DDR_PHY_REG(d, i) (*(d->ddrphy + i))
88 	uint32_t bit, dq;  in check_errata()  local
90 	for (bit = 0, dq = 0; bit < 2; bit++, dq++) {  in check_errata()
93 		if (bit == 0) {  in check_errata()
143 	struct ddr_ctrl_data *ddr_ctrl = dev->data;  in ddr_init()
145 	LOG_DBG("start: 0x%lx", (uintptr_t)ddr_ctrl->ddr_start);  in ddr_init()
146 	LOG_DBG("size:  0x%lx", ddr_ctrl->ddr_size);  in ddr_init()
167 	size_t end_addr_16Kblocks = ((ddr_ctrl->ddr_size >> 14) & 0x7FFFFF) - 1;  in ddr_init()
183 	/* WAIT for initialization complete : bit 8 of INT_STATUS (DENALI_CTL_132) 0x210 */  in ddr_init()
188 	uint64_t ddr_end = (uint64_t)ddr_ctrl->ddr_start + ddr_ctrl->ddr_size;  in ddr_init()
191 	volatile uint64_t *filterreg = (volatile uint64_t *)ddr_ctrl->ddr_physical_filter;  in ddr_init()