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/Zephyr-latest/include/zephyr/devicetree/
Dclocks.h9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-clocks Devicetree Clocks API
26 * @brief Test if a node has a clocks phandle-array property at a given index
28 * This expands to 1 if the given index is valid clocks property phandle-array index.
33 * n1: node-1 {
37 * n2: node-2 {
43 * DT_CLOCKS_HAS_IDX(DT_NODELABEL(n1), 0) // 1
44 * DT_CLOCKS_HAS_IDX(DT_NODELABEL(n1), 1) // 1
46 * DT_CLOCKS_HAS_IDX(DT_NODELABEL(n2), 1) // 0
49 * @param idx index of a clocks property phandle-array whose existence to check
[all …]
Ddma.h9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-dmas Devicetree DMA API
36 * dmas = <&dma1 1 2 0x400 0x3>,
43 * DT_DMAS_CTLR_BY_IDX(DT_NODELABEL(n), 1) // DT_NODELABEL(dma2)
64 * dmas = <&dma1 1 2 0x400 0x3>,
66 * dma-names = "tx", "rx";
75 * @param name lowercase-and-underscores name of a dmas element
76 * as defined by the node's dma-names property
109 * @param name lowercase-and-underscores name of a dmas element
110 * as defined by the node's dma-names property
[all …]
Dpwms.h9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-pwms Devicetree PWMs API
31 * pwm1: pwm-controller@... { ... };
33 * pwm2: pwm-controller@... { ... };
36 * pwms = <&pwm1 1 PWM_POLARITY_NORMAL>,
43 * DT_PWMS_CTLR_BY_IDX(DT_NODELABEL(n), 1) // DT_NODELABEL(pwm2)
60 * pwm1: pwm-controller@... { ... };
62 * pwm2: pwm-controller@... { ... };
65 * pwms = <&pwm1 1 PWM_POLARITY_NORMAL>,
67 * pwm-names = "alpha", "beta";
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Dreset.h7 * Copyright (c) 2022, Andrei-Edward Popa
9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-reset-controller Devicetree Reset Controller API
27 * "resets" phandle-array property at an index
31 * reset1: reset-controller@... { ... };
33 * reset2: reset-controller@... { ... };
42 * DT_RESET_CTLR_BY_IDX(DT_NODELABEL(n), 1)) // DT_NODELABEL(reset2)
65 * resets phandle-array property by name
69 * reset1: reset-controller@... { ... };
71 * reset2: reset-controller@... { ... };
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Dgpio.h10 * SPDX-License-Identifier: Apache-2.0
21 * @defgroup devicetree-gpio Devicetree GPIO API
28 * gpio phandle-array property at an index
43 * DT_GPIO_CTLR_BY_IDX(DT_NODELABEL(n), gpios, 1) // DT_NODELABEL(gpio2)
46 * @param gpio_pha lowercase-and-underscores GPIO property with
47 * type "phandle-array"
59 * @param gpio_pha lowercase-and-underscores GPIO property with
60 * type "phandle-array"
69 * @brief Get a GPIO specifier's pin cell at an index
78 * #gpio-cells = <2>;
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Dio-channels.h9 * SPDX-License-Identifier: Apache-2.0
20 * @defgroup devicetree-io-channels Devicetree IO Channels API
28 * io-channels property at an index
37 * io-channels = <&adc1 10>, <&adc2 20>;
43 * DT_IO_CHANNELS_CTLR_BY_IDX(DT_NODELABEL(n), 1) // DT_NODELABEL(adc2)
45 * @param node_id node identifier for a node with an io-channels property
46 * @param idx logical index into io-channels property
55 * io-channels property by name
64 * io-channels = <&adc1 10>, <&adc2 20>;
65 * io-channel-names = "SENSOR", "BANDGAP";
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/Zephyr-latest/drivers/sensor/maxim/max17055/
Dmax17055.h4 * SPDX-License-Identifier: Apache-2.0
48 /* Current cell voltage in units of 1.25/16mV */
50 /* Current cell open circuit voltage in units of 1.25/16mV */
56 /* Internal temperature in units of 1/256 degrees C */
66 /* Cycle count in 1/100ths (number of charge/discharge cycles) */
76 /* The design capacity (aka label capacity) of the cell in mAh */
78 /* Design voltage of cell in mV */
80 /* Desired voltage of cell in mV */
86 /* The empty voltage of the cell in mV */
/Zephyr-latest/samples/drivers/ethernet/eth_ivshmem/
DREADME.rst1 .. zephyr:code-sample:: eth-ivshmem
2 :name: Inter-VM Shared Memory (ivshmem) Ethernet
3 :relevant-api: ivshmem ethernet
5 Communicate with another "cell" in the Jailhouse hypervisor using IVSHMEM Ethernet.
11 another "cell" in the Jailhouse hypervisor. Currently only the qemu_cortex_a53
20 .. code-block:: console
22 git clone https://github.com/siemens/jailhouse-images.git
23 cd jailhouse-images
29 .. code-block:: console
31 ./kas-container menu
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/Zephyr-latest/drivers/display/
DKconfig.sdl4 # SPDX-License-Identifier: Apache-2.0
32 bool "Mono Black=1"
63 int "Transparency grid cell size"
69 hex "Transparency grid cell color 1"
75 hex "Transparency grid cell color 2"
/Zephyr-latest/dts/bindings/test/
Dvnd,gpio-one-cell.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Test GPIO node with one cell
6 compatible: "vnd,gpio-one-cell"
8 include: [gpio-controller.yaml, base.yaml]
14 "#gpio-cells":
15 const: 1
17 gpio-cells:
18 - pin
/Zephyr-latest/boards/nxp/ls1046ardb/doc/
Dindex.rst6 The LS1046A reference design board (RDB) is a high-performance computing,
10 of high-speed SerDes ports.
12 The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72
13 cores with packet processing acceleration and high-speed peripherals. The
25 - Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed
26 - Supports 8 GB DDR4 SDRAM memory
27 - SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi
29 - One 512 MB SLC NAND flash with ECC support (1.8 V)
30 - CPLD connection: 8-bit registers in CPLD to configure mux/demux selections
31 - Support two 64 MB onboard QSPI NOR flash memories
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/Zephyr-latest/doc/_doxygen/
Ddoxygen-awesome-zephyr.js3 * SPDX-License-Identifier: Apache-2.0
7 /* re-inject project version at a custom location */
10 let cell = titleTable.insertRow(1).insertCell(0);
11 cell.innerHTML = '<div id="projectversion">' + version + '</div>';
/Zephyr-latest/include/zephyr/
Ddevicetree.h2 * SPDX-License-Identifier: Apache-2.0
39 * -----------------
42 * part in DT_N_<path-id>_P_<property-id> macros, or the "prop-suf"
60 * _IDX_<i>_VAL_<val>_EXISTS: cell value exists, by index
64 * _NAME_<name>_VAL_<val>_EXISTS: cell value exists, by name
71 * @defgroup devicetree-generic-id Node identifiers and helpers
96 * The arguments to this macro are the names of non-root nodes in the
98 * Non-alphanumeric characters in each name must be converted to
108 * current-speed = <115200>;
119 * Example usage with DT_PROP() to get the `current-speed` property:
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/Zephyr-latest/include/zephyr/drivers/dma/
Ddma_esp32.h4 * SPDX-License-Identifier: Apache-2.0
11 ESP_GDMA_TRIG_PERIPH_M2M = -1,
13 ESP_GDMA_TRIG_PERIPH_SPI3 = 1,
32 #define ESP32_DT_INST_DMA_CELL(n, name, cell) \ argument
34 (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)), \
/Zephyr-latest/boards/nxp/imx8mn_evk/doc/
Dindex.rst7 processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M7 core.
8 Zephyr OS is ported to run on the Cortex®-A53 core.
10 - Board features:
12 - RAM: 2GB LPDDR4
13 - Storage:
15 - SanDisk 16GB eMMC5.1
16 - Micron 32MB QSPI NOR
17 - microSD Socket
18 - Wireless:
20 - WiFi: 2.4/5GHz IEEE 802.11b/g/n
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/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
22 - bit 10: Memory address increase
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Datmel,sam0-dmac.yaml3 compatible: "atmel,sam0-dmac"
5 include: dma-controller.yaml
14 "#dma-cells":
17 # #dma-cells : Must be <2>.
18 # The 1st cell specifies the DMAC channel to be used for the data transfer.
21 # The 2nd cell defines the peripheral trigger which is the source of the transfer.
31 # dma-names = "rx", "tx";
37 dma-cells:
38 - channel
39 - trigsrc
Dmicrochip,xec-dmac.yaml3 compatible: "microchip,xec-dmac"
5 include: dma-controller.yaml
24 aggregated-girq:
30 "#dma-cells":
33 "pcr-cells":
37 "girq-cells":
41 # #dma-cells : Must be <2>.
42 # The 1st cell specifies the DMAC channel to be used for the data transfer.
45 # The 2nd cell defines the peripheral trigger which is the source of the transfer.
55 # dma-names = "rx", "tx";
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/Zephyr-latest/drivers/sensor/maxim/max17262/
Dmax17262.h4 * SPDX-License-Identifier: Apache-2.0
51 /* Current cell voltage in units of 1.25/16mV */
59 /* Internal temperature in units of 1/256 degrees C */
69 /* Cycle count in 1/100ths (number of charge/discharge cycles) */
81 /* Design voltage of cell in mV */
83 /* Desired voltage of cell in mV */
/Zephyr-latest/dts/bindings/retention/
Dzephyr,retention.yaml2 # SPDX-License-Identifier: Apache-2.0
6 64-byte area with 2-byte prefix and 1-byte checksum with 61 usable bytes
10 compatible = "zephyr,memory-region", "mmio-sram";
12 zephyr,memory-region = "RetainedMem";
16 compatible = "zephyr,retained-ram";
18 #address-cells = <1>;
19 #size-cells = <1>;
26 checksum = <1>;
36 "#address-cells":
37 const: 1
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/Zephyr-latest/dts/bindings/adc/
Datmel,sam-adc.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam-adc"
8 include: [adc-controller.yaml, pinctrl-device.yaml]
25 startup-time:
32 settling-time:
37 or differential input parameters of the analog cell change
38 between two channels, the analog cell may need a specific
42 tracking-time:
49 enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
51 "#io-channel-cells":
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/Zephyr-latest/include/zephyr/drivers/misc/ft8xx/
Dft8xx_dl.h4 * SPDX-License-Identifier: Apache-2.0
29 #define FT8XX_BITMAPS 1U
30 /** Anti-aliased points, point radius is 1-256 pixels */
33 * Anti-aliased lines, with width from 0 to 4095 1/16th of pixel units.
37 /** Anti-aliased lines, connected head-to-tail */
48 * Round-cornered rectangles, curvature of the corners can be adjusted using
57 * - @ref FT8XX_BITMAPS
58 * - @ref FT8XX_POINTS
59 * - @ref FT8XX_LINES
60 * - @ref FT8XX_LINE_STRIP
[all …]
/Zephyr-latest/boards/contextualelectronics/abc/
Dcontextualelectronics_abc.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "contextualelectronics_abc-pinctrl.dtsi"
13 model = "nRF52840 BLE Cell";
14 compatible = "nordic,nrf52840-ble-cell";
18 zephyr,shell-uart = &uart0;
27 regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
31 gpio-as-nreset;
47 compatible = "nordic,nrf-uart";
49 current-speed = <115200>;
[all …]
/Zephyr-latest/drivers/dma/
DKconfig.stm326 # SPDX-License-Identifier: Apache-2.0
43 peripheral request must be specified in the dma slot of the dma cell
45 a parameter of the dma-cell.
61 Enable shared IRQ support on devices where channels share 1 IRQ.
/Zephyr-latest/doc/safety/images/
DIEC-61508-basis.svg1-0.5 -0.5 802 515" style="background-color: rgb(255, 255, 255);"><defs><linearGradient x1="0%" y1=…

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