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6 The LS1046A reference design board (RDB) is a high-performance computing,
10 of high-speed SerDes ports.
12 The Layerscape LS1046A processor integrates four 64-bit Arm(R) Cortex(R) A72
13 cores with packet processing acceleration and high-speed peripherals. The
25 - Four 32/64-bit Arm(R) Cortex(R)V8 A72 CPUs, up to 1.6 GHz core speed
26 - Supports 8 GB DDR4 SDRAM memory
27 - SDHC port connects directly to an adapter card slot, featuring 4 GB eMMCi
29 - One 512 MB SLC NAND flash with ECC support (1.8 V)
30 - CPLD connection: 8-bit registers in CPLD to configure mux/demux selections
31 - Support two 64 MB onboard QSPI NOR flash memories
32 - USB:
33 - Two USB 3.0 controllers with integrated PHYs.
34 - One USB1 3.0 port is connected to a Type A host connector.
35 - One USB1 3.0 port is configured as On-The-Go (OTG) with a Micro-AB connector.
36 - One USB2.0 is connected to miniPCIe connector .
37 - Ethernet:
38 - Supports SGMII 1G PHYs at Lane 2 and Lane 3
39 - Supports SFP+module with XFI retimers
40 - Supports AQR106/107 10G PHY with XFI/2.5G SGMII
41 - PCIe and SATA:
42 - Mini PCIe express x1 (Gen1/2/3)card
43 - Standard PCIe x1 (Gen1/2/3) card
44 - Standard PCIe x1 (Gen1/2/3) card
45 - One SATA 3.0 connector
53 +-----------+------------+--------------------------------------+
56 | GIC-400 | on-chip | GICv2 interrupt controller |
57 +-----------+------------+--------------------------------------+
58 | ARM TIMER | on-chip | System Clock |
59 +-----------+------------+--------------------------------------+
60 | UART | on-chip | NS16550 compatible serial port |
61 +-----------+------------+--------------------------------------+
65 The default configuration can be found in the defconfig file for NON-SMP:
84 kernel tests on LS1046A RDB board. For example, with the :zephyr:code-sample:`synchronization` samp…
86 1. Non-SMP mode
88 .. zephyr-app-commands::
89 :zephyr-app: samples/synchronization
90 :host-os: unix
96 Use u-boot to load and kick Zephyr.bin to CPU Core0:
98 .. code-block:: console
104 .. code-block:: console
111 .. code-block:: console
113 *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 ***
120 .. zephyr-app-commands::
121 :zephyr-app: samples/synchronization
122 :host-os: unix
128 Use u-boot to load and kick Zephyr.bin to CPU Core0:
130 .. code-block:: console
136 .. code-block:: console
138 *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 ***
139 Secondary CPU core 1 (MPID:0x1) is up
143 thread_b: Hello World from cpu 1 on nxp_ls1046ardb!
148 .. zephyr-app-commands::
149 :zephyr-app: samples/synchronization
150 :host-os: unix
156 Use u-boot to load and kick Zephyr.bin to CPU Core2:
158 .. code-block:: console
164 .. code-block:: console
166 *** Booting Zephyr OS build zephyr-v2.5.0-1922-g3265b69d47e7 ***
167 Secondary CPU core 1 (MPID:0x3) is up
169 thread_b: Hello World from cpu 1 on nxp_ls1046ardb!
172 4. Running Zephyr on Jailhouse inmate Cell
175 inmate Cell to use a single Core for Zephyr non-SMP mode, or use Core2 and Core3
178 1) Use root Cell dts to boot root Cell Linux.
182 .. code-block:: console
186 3) Run Zephyr demo in inmate Cell:
188 .. code-block:: console
190 jailhouse enable ls1046a-rdb.cell
191 jailhouse cell create ls1046a-rdb-inmate-demo.cell
192 jailhouse cell load 1 zephyr.bin --address 0xc0000000
193 jailhouse cell start 1
210 …n Board <https://www.nxp.com/design/qoriq-developer-resources/layerscape-ls1046a-reference-design-…