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/Zephyr-latest/samples/shields/x_nucleo_53l0a1/src/
Ddisplay_7seg.h7 * SPDX-License-Identifier: Apache-2.0
15 * ---
17 * -2-
19 * ---
25 #define CHAR_0 (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
26 #define CHAR_1 (BIT(5) | BIT(6))
27 #define CHAR_2 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
28 #define CHAR_3 (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
29 #define CHAR_4 (BIT(1) | BIT(2) | BIT(5) | BIT(6))
30 #define CHAR_5 (BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(6))
[all …]
/Zephyr-latest/tests/kernel/common/src/
Dbitfield.c4 * SPDX-License-Identifier: Apache-2.0
14 #define BIT_INDEX(bit) ((3 - ((bit >> 3) & 0x3)) + 4*(bit >> 5)) argument
16 #define BIT_INDEX(bit) (bit >> 3) argument
18 #define BIT_VAL(bit) (1 << (bit & 0x7)) argument
41 unsigned int bit; in ZTEST()
46 for (bit = 0U; bit < 32; ++bit) { in ZTEST()
47 sys_set_bit((mem_addr_t)&b1, bit); in ZTEST()
49 zassert_equal(b1, (1 << bit), in ZTEST()
50 "sys_set_bit failed on bit %d\n", bit); in ZTEST()
52 zassert_true(sys_test_bit((mem_addr_t)&b1, bit), in ZTEST()
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_mcr20a_regs.h1 /* ieee802154_mcr20a_regs.h - Registers definition for NXP MCR20A */
6 * SPDX-License-Identifier: Apache-2.0
11 * which are used in the macros for the bit field manipulation.
47 #define MCR20A_REG_READ (BIT(7))
48 #define MCR20A_BUF_READ (BIT(7) | BIT(6))
49 #define MCR20A_BUF_BYTE_READ (BIT(7) | BIT(6) | BIT(5))
51 #define MCR20A_BUF_WRITE (BIT(6))
52 #define MCR20A_BUF_BYTE_WRITE (BIT(6) | BIT(5))
93 /* ---------------- (0x27) */
112 /* ---------------- (0x3a) */
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
[all …]
Dmec172x_i2c_smb.h4 * SPDX-License-Identifier: Apache-2.0
36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
47 /* Status Read-only */
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
[all …]
/Zephyr-latest/soc/neorv32/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
21 #define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
22 #define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
23 #define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
24 #define NEORV32_SYSINFO_CPU_ZBB BIT(3)
25 #define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
26 #define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
27 #define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
28 #define NEORV32_SYSINFO_CPU_PMP BIT(8)
29 #define NEORV32_SYSINFO_CPU_HPM BIT(9)
[all …]
/Zephyr-latest/drivers/gpio/
Dgpio_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
35 /* gpio port data register (bit mapping to pin) */
39 /* gpio port data mirror register (bit mapping to pin) */
41 /* gpio port output type register (bit mapping to pin) */
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on in wuesr()
[all …]
/Zephyr-latest/drivers/sensor/st/lps25hb/
Dlps25hb.h1 /* sensor_lps25hb.h - header file for LPS25HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
26 #define LPS25HB_MASK_RES_CONF_AVGT (BIT(3) | BIT(2))
28 #define LPS25HB_MASK_RES_CONF_AVGP (BIT(1) | BIT(0))
32 #define LPS25HB_MASK_CTRL_REG1_PD BIT(7)
34 #define LPS25HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4))
36 #define LPS25HB_MASK_CTRL_REG1_DIFF_EN BIT(3)
38 #define LPS25HB_MASK_CTRL_REG1_BDU BIT(2)
40 #define LPS25HB_MASK_CTRL_REG1_RESET_AZ BIT(1)
42 #define LPS25HB_MASK_CTRL_REG1_SIM BIT(0)
[all …]
/Zephyr-latest/drivers/sensor/st/lsm9ds0_gyro/
Dlsm9ds0_gyro.h1 /* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */
6 * SPDX-License-Identifier: Apache-2.0
23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
27 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_PD BIT(3)
29 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_ZEN BIT(2)
31 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_XEN BIT(1)
33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
39 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPCF (BIT(3) | BIT(2) | BIT(1) | \
[all …]
/Zephyr-latest/include/zephyr/math/
Dilog2.h4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
[all …]
/Zephyr-latest/drivers/usb_c/ppc/
Dnxp_nx20p3483_priv.h3 * SPDX-License-Identifier: Apache-2.0
14 #include<zephyr/dt-bindings/usb-c/nxp_nx20p3483.h>
16 /** Register address - device id */
18 /** Bit mask for vendor id */
20 /** Bit mask for version id */
23 /** Register address - device status */
25 /** Bit mask for device mode */
30 /** Value for high-voltage sink mode */
34 /** Value for high-voltage source mode */
39 /** Register address - switch control */
[all …]
/Zephyr-latest/drivers/sensor/st/lps22hb/
Dlps22hb.h1 /* sensor_lps25hb.h - header file for LPS22HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
22 #define LPS22HB_MASK_INTERRUPT_CFG_AUTORIFP BIT(7)
24 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_ARP BIT(6)
26 #define LPS22HB_MASK_INTERRUPT_CFG_AUTOZERO BIT(5)
28 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_AZ BIT(4)
30 #define LPS22HB_MASK_INTERRUPT_CFG_DIFF_EN BIT(3)
32 #define LPS22HB_MASK_INTERRUPT_CFG_LIR BIT(2)
34 #define LPS22HB_MASK_INTERRUPT_CFG_PL_E BIT(1)
36 #define LPS22HB_MASK_INTERRUPT_CFG_PH_E BIT(0)
[all …]
/Zephyr-latest/drivers/audio/
Dtas6422dac.h4 * SPDX-License-Identifier: Apache-2.0
18 #define MODE_CTRL_RESET BIT(7)
19 #define MODE_CTRL_RESET_MASK BIT(7)
20 #define MODE_CTRL_PBTL_CH12 BIT(4)
21 #define MODE_CTRL_PBTL_CH12_MASK BIT(4)
22 #define MODE_CTRL_CH1_LO_MODE BIT(3)
23 #define MODE_CTRL_CH1_LO_MODE_MASK BIT(3)
24 #define MODE_CTRL_CH2_LO_MODE BIT(2)
25 #define MODE_CTRL_CH2_LO_MODE_MASK BIT(2)
29 #define MISC_CTRL_1_HPF_BYPASS BIT(7)
[all …]
/Zephyr-latest/drivers/sensor/apds9960/
Dapds9960.h5 * SPDX-License-Identifier: Apache-2.0
14 #define APDS9960_ENABLE_GEN BIT(6)
15 #define APDS9960_ENABLE_PIEN BIT(5)
16 #define APDS9960_ENABLE_AIEN BIT(4)
17 #define APDS9960_ENABLE_WEN BIT(3)
18 #define APDS9960_ENABLE_PEN BIT(2)
19 #define APDS9960_ENABLE_AEN BIT(1)
20 #define APDS9960_ENABLE_PON BIT(0)
32 #define APDS9960_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
33 #define APDS9960_APERS_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
48 #define SSCR0_ACS BIT(30)
[all …]
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
47 #define SSCR0_ACS BIT(30)
[all …]
/Zephyr-latest/drivers/ipm/
Dipm_nrfx_ipc.h4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
52 [0] = BIT(0),
53 [1] = BIT(1),
54 [2] = BIT(2),
55 [3] = BIT(3),
56 [4] = BIT(4),
57 [5] = BIT(5),
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dapds9253.h5 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/dt-util.h>
19 #define APDS9253_RESOLUTION_19BIT_200MS BIT(4)
20 #define APDS9253_RESOLUTION_18BIT_100MS BIT(5) /* default */
21 #define APDS9253_RESOLUTION_17BIT_50MS (BIT(5) | BIT(4))
22 #define APDS9253_RESOLUTION_16BIT_25MS BIT(6)
23 #define APDS9253_RESOLUTION_13BIT_3MS (BIT(6) | BIT(4))
32 #define APDS9253_MEASUREMENT_RATE_2000MS (BIT(2) | BIT(1) | BIT(0))
33 #define APDS9253_MEASUREMENT_RATE_1000MS (BIT(2) | BIT(0))
34 #define APDS9253_MEASUREMENT_RATE_500MS BIT(2)
[all …]
/Zephyr-latest/drivers/sensor/st/lsm9ds0_mfd/
Dlsm9ds0_mfd.h1 /* sensor_lsm9ds0_mfd.h - header file for LSM9DS0 accelerometer, magnetometer
8 * SPDX-License-Identifier: Apache-2.0
22 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7)
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5)
28 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMOR BIT(4)
30 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMDA BIT(3)
32 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMDA BIT(2)
34 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMDA BIT(1)
36 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMDA BIT(0)
[all …]
/Zephyr-latest/drivers/sensor/ams/tmd2620/
Dtmd2620.h4 * SPDX-License-Identifier: Apache-2.0
15 #define TMD2620_ENABLE_WEN BIT(3)
16 #define TMD2620_ENABLE_PEN BIT(2)
17 #define TMD2620_ENABLE_PON BIT(0)
28 * If the WLONG bit is set:
57 #define TMD2620_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
60 #define TMD2620_CFG0_WLONG BIT(2)
65 #define TMD2620_PCFG0_PPULSE_LEN_8US BIT(6)
66 #define TMD2620_PCFG0_PPULSE_LEN_16US BIT(7)
67 #define TMD2620_PCFG0_PPULSE_LEN_32US (BIT(6) | BIT(7))
[all …]
/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/nrfx_glue/
Dbt_ctlr_used_resources.h2 * Copyright (c) 2021-2024 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
23 (BIT(HAL_RADIO_ENABLE_TX_ON_TICK_PPI) | \
24 BIT(HAL_RADIO_ENABLE_RX_ON_TICK_PPI) | \
25 BIT(HAL_RADIO_RECV_TIMEOUT_CANCEL_PPI) | \
26 BIT(HAL_RADIO_DISABLE_ON_HCTO_PPI) | \
27 BIT(HAL_RADIO_END_TIME_CAPTURE_PPI) | \
28 BIT(HAL_EVENT_TIMER_START_PPI) | \
29 BIT(HAL_RADIO_READY_TIME_CAPTURE_PPI) | \
30 BIT(HAL_TRIGGER_CRYPT_PPI) | \
[all …]
/Zephyr-latest/soc/renesas/rzt2m/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
16 #define CNTCR_EN BIT(0)
17 #define CNTCR_HDBG BIT(1)
20 #define PRCRS_CLK BIT(0)
21 #define PRCRS_LPC_RESET BIT(1)
22 #define PRCRS_GPIO BIT(2)
23 #define PRCRS_SYS_CTRL BIT(3)
25 /* Non-safety area protect register */
26 #define PRCRN_PRC0 BIT(0)
27 #define PRCRN_PRC1 BIT(1)
[all …]
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_kbc.h4 * SPDX-License-Identifier: Apache-2.0
13 /* ---- EM8042 Keyboard Controller (KBC) ---- */
15 /* EC_KBC_STS and KBC_STS_RD bit definitions */
17 #define MCHP_KBC_STS_OBF BIT(MCHP_KBC_STS_OBF_POS)
19 #define MCHP_KBC_STS_IBF BIT(MCHP_KBC_STS_IBF_POS)
21 #define MCHP_KBC_STS_UD0 BIT(MCHP_KBC_STS_UD0_POS)
23 #define MCHP_KBC_STS_CD BIT(MCHP_KBC_STS_CD_POS)
25 #define MCHP_KBC_STS_UD1 BIT(MCHP_KBC_STS_UD1_POS)
27 #define MCHP_KBC_STS_AUXOBF BIT(MCHP_KBC_STS_AUXOBF_POS)
32 #define MCHP_KBC_STS_UD2_0 BIT(6)
[all …]
/Zephyr-latest/include/zephyr/bluetooth/
Dbyteorder.h8 * SPDX-License-Identifier: Apache-2.0
26 /** @brief Encode 16-bit value into array values in little-endian format.
28 * Helper macro to encode 16-bit values into comma separated values.
32 * @param _v 16-bit integer in host endianness.
34 * @return The comma separated values for the 16-bit value.
40 /** @brief Encode 24-bit value into array values in little-endian format.
42 * Helper macro to encode 24-bit values into comma separated values.
46 * @param _v 24-bit integer in host endianness.
48 * @return The comma separated values for the 24-bit value.
54 /** @brief Encode 32-bit value into array values in little-endian format.
[all …]
/Zephyr-latest/drivers/sensor/apds9253/
Dapds9253.h5 * SPDX-License-Identifier: Apache-2.0
15 #define APDS9253_MAIN_CTRL_SAI_LS BIT(5)
16 #define APDS9253_MAIN_CTRL_SW_RESET BIT(4)
17 #define APDS9253_MAIN_CTRL_RGB_MODE BIT(2)
18 #define APDS9253_MAIN_CTRL_LS_EN BIT(1)
23 #define APDS9253_LS_MEAS_RATE_RES_19BIT_200MS BIT(4)
24 #define APDS9253_LS_MEAS_RATE_RES_18BIT_100MS BIT(5) /* default */
25 #define APDS9253_LS_MEAS_RATE_RES_17BIT_50MS (BIT(5) | BIT(4))
26 #define APDS9253_LS_MEAS_RATE_RES_16BIT_25MS BIT(6)
27 #define APDS9253_LS_MEAS_RATE_RES_13_3MS (BIT(6) | BIT(4))
[all …]

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