1/* 2 * Copyright (c) 2023 Nuvoton Technology Corporation. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7/* npcx4 series pinmux mapping table */ 8#include "npcx4/npcx4-alts-map.dtsi" 9/* npcx4 series mapping table between MIWU wui bits and source device */ 10#include "npcx4/npcx4-miwus-wui-map.dtsi" 11/* npcx4 series mapping table between MIWU groups and interrupts */ 12#include "npcx4/npcx4-miwus-int-map.dtsi" 13/* npcx4 series eSPI VW mapping table */ 14#include "npcx4/npcx4-espi-vws-map.dtsi" 15/* npcx4 series low-voltage io controls mapping table */ 16#include "npcx4/npcx4-lvol-ctrl-map.dtsi" 17/* npcx4 series reset mapping table */ 18#include "zephyr/dt-bindings/reset/npcx4_reset.h" 19 20/* Device tree declarations of npcx soc family */ 21#include "npcx.dtsi" 22 23/ { 24 def-io-conf-list { 25 pinmux = <&alt0_gpio_no_spip 26 &alt0_gpio_no_fpip 27 &alt1_no_pwrgd 28 &alt7_no_ksi0_sl 29 &alt7_no_ksi1_sl 30 &alt7_no_ksi2_sl 31 &alt7_no_ksi3_sl 32 &alt7_no_ksi4_sl 33 &alt7_no_ksi5_sl 34 &alt7_no_ksi6_sl 35 &alt7_no_ksi7_sl 36 &alt8_no_kso00_sl 37 &alt8_no_kso01_sl 38 &alt8_no_kso02_sl 39 &alt8_no_kso03_sl 40 &alt8_no_kso04_sl 41 &alt8_no_kso05_sl 42 &alt8_no_kso06_sl 43 &alt8_no_kso07_sl 44 &alt9_no_kso08_sl 45 &alt9_no_kso09_sl 46 &alt9_no_kso10_sl 47 &alt9_no_kso11_sl 48 &alt9_no_kso12_sl 49 &alt9_no_kso13_sl 50 &alt9_no_kso14_sl 51 &alt9_no_kso15_sl 52 &alta_no_kso16_sl 53 &alta_no_kso17_sl 54 &alta_no_peci_en 55 &altc_gpio97_sl_inv 56 &altd_npsl_in1_sl 57 &altd_npsl_in2_sl 58 &altd_psl_in3_sl 59 &altd_psl_in4_sl 60 &altg_psl_gpo_sl>; 61 }; 62 63 soc { 64 compatible = "nuvoton,npcx4", "nuvoton,npcx", "simple-bus"; 65 66 /* 67 * Writing to BKUP_STS register might affect the value stored in 68 * the first byte of the BBRAM. 69 * Workaround it by not using the first byte of the BBRAM. 70 * (See npcx4 Errata 2.27) 71 */ 72 bbram: bb-ram@400af001 { 73 compatible = "nuvoton,npcx-bbram"; 74 reg = <0x400af001 0x7F 75 0x400af100 0x1>; 76 reg-names = "memory", "status"; 77 }; 78 79 /* Specific soc devices in npcx4 series */ 80 itims: timer@400b0000 { 81 compatible = "nuvoton,npcx-itim-timer"; 82 reg = <0x400b0000 0x2000 83 0x400be000 0x2000>; 84 reg-names = "evt_itim", "sys_itim"; 85 clocks = <&pcc NPCX_CLOCK_BUS_LFCLK NPCX_PWDWN_CTL4 0 86 &pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL7 5>; 87 interrupts = <28 1>; /* Event timer interrupt */ 88 }; 89 90 uart1: serial@400e0000 { 91 compatible = "nuvoton,npcx-uart"; 92 /* Index 0: UART1 register, Index 1: MDMA1 register */ 93 reg = <0x400E0000 0x2000 0x40011100 0x100>; 94 interrupts = <33 3>; 95 /* Index 0: UART1 clock, Index 1: MDMA1 clock */ 96 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL1 4 97 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 0>; 98 uart-rx = <&wui_cr_sin1>; 99 status = "disabled"; 100 }; 101 102 uart2: serial@400e2000 { 103 compatible = "nuvoton,npcx-uart"; 104 /* Index 0: UART2 register, Index 1: MDMA2 register */ 105 reg = <0x400E2000 0x2000 0x40011200 0x100>; 106 interrupts = <32 3>; 107 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 6>; 108 uart-rx = <&wui_cr_sin2>; 109 status = "disabled"; 110 }; 111 112 uart3: serial@400e4000 { 113 compatible = "nuvoton,npcx-uart"; 114 /* Index 0: UART3 register, Index 1: MDMA3 register */ 115 reg = <0x400E4000 0x2000 0x40011300 0x100>; 116 interrupts = <38 3>; 117 /* Index 0: UART3 clock, Index 1: MDMA3 clock */ 118 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 4 119 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 2>; 120 uart-rx = <&wui_cr_sin3>; 121 status = "disabled"; 122 }; 123 124 uart4: serial@400e6000 { 125 compatible = "nuvoton,npcx-uart"; 126 /* Index 0: UART4 register, Index 1: MDMA4 register */ 127 reg = <0x400E6000 0x2000 0x40011400 0x100>; 128 interrupts = <39 3>; 129 /* Index 0: UART4 clock, Index 1: MDMA4 clock */ 130 clocks = <&pcc NPCX_CLOCK_BUS_APB4 NPCX_PWDWN_CTL7 3 131 &pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 3>; 132 uart-rx = <&wui_cr_sin4>; 133 status = "disabled"; 134 }; 135 136 /* Default clock and power settings in npcx4 series */ 137 pcc: clock-controller@4000d000 { 138 clock-frequency = <DT_FREQ_M(120)>; /* OFMCLK runs at 120MHz */ 139 core-prescaler = <8>; /* CORE_CLK runs at 15MHz */ 140 apb1-prescaler = <8>; /* APB1_CLK runs at 15MHz */ 141 apb2-prescaler = <8>; /* APB2_CLK runs at 15MHz */ 142 apb3-prescaler = <8>; /* APB3_CLK runs at 15MHz */ 143 apb4-prescaler = <8>; /* APB4_CLK runs at 15MHz */ 144 ram-pd-depth = <8>; /* Valid bit-depth of RAM_PDn reg */ 145 pwdwn-ctl-val = <0xfb 146 0xff 147 0x1f /* No GDMA1_PD/GDMA2_PD */ 148 0xff 149 0xfa 150 0x7f /* No ESPI_PD */ 151 0xff 152 0xcf>; /* No FIU_PD */ 153 }; 154 155 /* Wake-up input source mapping for GPIOs in npcx4 series */ 156 gpio0: gpio@40081000 { 157 wui-maps = <&wui_io00 &wui_io01 &wui_io02 &wui_io03 158 &wui_io04 &wui_io05 &wui_io06 &wui_io07>; 159 160 lvol-maps = <&lvol_io00 &lvol_io01 &lvol_io02 &lvol_io03 161 &lvol_io04 &lvol_io05 &lvol_io06 &lvol_io07>; 162 }; 163 164 gpio1: gpio@40083000 { 165 wui-maps = <&wui_io10 &wui_io11 &wui_io12 &wui_io13 166 &wui_io14 &wui_io15 &wui_io16 &wui_io17>; 167 168 lvol-maps = <&lvol_io10 &lvol_io11 &lvol_none &lvol_io13 169 &lvol_io14 &lvol_io15 &lvol_io16 &lvol_io17>; 170 }; 171 172 gpio2: gpio@40085000 { 173 wui-maps = <&wui_io20 &wui_io21 &wui_io22 &wui_io23 174 &wui_io24 &wui_io25 &wui_io26 &wui_io27>; 175 176 lvol-maps = <&lvol_io20 &lvol_io21 &lvol_io22 &lvol_io23 177 &lvol_none &lvol_none &lvol_none &lvol_none>; 178 }; 179 180 gpio3: gpio@40087000 { 181 wui-maps = <&wui_io30 &wui_io31 &wui_none &wui_io33 182 &wui_io34 &wui_none &wui_io36 &wui_io37>; 183 184 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_io33 185 &lvol_io34 &lvol_none &lvol_io36 &lvol_io37>; 186 }; 187 188 gpio4: gpio@40089000 { 189 wui-maps = <&wui_io40 &wui_io41 &wui_io42 &wui_io43 190 &wui_io44 &wui_io45 &wui_io46 &wui_io47>; 191 192 lvol-maps = <&lvol_io40 &lvol_io41 &lvol_io42 &lvol_io43 193 &lvol_io44 &lvol_io45 &lvol_none &lvol_none>; 194 }; 195 196 gpio5: gpio@4008b000 { 197 wui-maps = <&wui_io50 &wui_io51 &wui_io52 &wui_io53 198 &wui_io54 &wui_io55 &wui_io56 &wui_io57>; 199 200 lvol-maps = <&lvol_io50 &lvol_none &lvol_none &lvol_none 201 &lvol_none &lvol_none &lvol_none &lvol_none>; 202 }; 203 204 gpio6: gpio@4008d000 { 205 wui-maps = <&wui_io60 &wui_io61 &wui_io62 &wui_io63 206 &wui_io64 &wui_none &wui_io66 &wui_io67>; 207 208 lvol-maps = <&lvol_io60 &lvol_io61 &lvol_io62 &lvol_io63 209 &lvol_io64 &lvol_none &lvol_io66 &lvol_io67>; 210 }; 211 212 gpio7: gpio@4008f000 { 213 wui-maps = <&wui_io70 &wui_none &wui_io72 &wui_io73 214 &wui_io74 &wui_io75 &wui_io76 &wui_none>; 215 216 lvol-maps = <&lvol_io70 &lvol_none &lvol_io72 &lvol_io73 217 &lvol_io74 &lvol_io75 &lvol_io76 &lvol_none>; 218 }; 219 220 gpio8: gpio@40091000 { 221 wui-maps = <&wui_io80 &wui_io81 &wui_io82 &wui_io83 222 &wui_none &wui_none &wui_none &wui_io87>; 223 224 lvol-maps = <&lvol_io80 &lvol_none &lvol_io82 &lvol_io83 225 &lvol_none &lvol_none &lvol_none &lvol_io87>; 226 }; 227 228 gpio9: gpio@40093000 { 229 wui-maps = <&wui_io90 &wui_io91 &wui_io92 &wui_io93 230 &wui_io94 &wui_io95 &wui_io96 &wui_io97>; 231 232 lvol-maps = <&lvol_io90 &lvol_io91 &lvol_io92 &lvol_none 233 &lvol_none &lvol_none &lvol_none &lvol_none>; 234 }; 235 236 gpioa: gpio@40095000 { 237 wui-maps = <&wui_ioa0 &wui_ioa1 &wui_ioa2 &wui_ioa3 238 &wui_ioa4 &wui_ioa5 &wui_ioa6 &wui_ioa7>; 239 240 lvol-maps = <&lvol_none &lvol_none &lvol_none &lvol_none 241 &lvol_none &lvol_none &lvol_none &lvol_none>; 242 }; 243 244 gpiob: gpio@40097000 { 245 wui-maps = <&wui_iob0 &wui_iob1 &wui_iob2 &wui_iob3 246 &wui_iob4 &wui_iob5 &wui_iob6 &wui_iob7>; 247 248 lvol-maps = <&lvol_none &lvol_iob1 &lvol_iob2 &lvol_iob3 249 &lvol_iob4 &lvol_iob5 &lvol_iob6 &lvol_iob7>; 250 }; 251 252 gpioc: gpio@40099000 { 253 wui-maps = <&wui_ioc0 &wui_ioc1 &wui_ioc2 &wui_ioc3 254 &wui_ioc4 &wui_ioc5 &wui_ioc6 &wui_ioc7>; 255 256 lvol-maps = <&lvol_ioc0 &lvol_ioc1 &lvol_ioc2 &lvol_ioc3 257 &lvol_ioc4 &lvol_ioc5 &lvol_ioc6 &lvol_ioc7>; 258 }; 259 260 gpiod: gpio@4009b000 { 261 wui-maps = <&wui_iod0 &wui_iod1 &wui_iod2 &wui_iod3 262 &wui_iod4 &wui_iod5 &wui_iod6 &wui_none>; 263 264 lvol-maps = <&lvol_iod0 &lvol_iod1 &lvol_iod2 &lvol_iod3 265 &lvol_iod4 &lvol_iod5 &lvol_iod6 &lvol_none>; 266 }; 267 268 gpioe: gpio@4009d000 { 269 wui-maps = <&wui_ioe0 &wui_ioe1 &wui_ioe2 &wui_ioe3 270 &wui_ioe4 &wui_ioe5 &wui_none &wui_ioe7>; 271 272 lvol-maps = <&lvol_ioe0 &lvol_ioe1 &lvol_ioe2 &lvol_ioe3 273 &lvol_ioe4 &lvol_ioe5 &lvol_none &lvol_ioe7>; 274 }; 275 276 gpiof: gpio@4009f000 { 277 wui-maps = <&wui_iof0 &wui_iof1 &wui_iof2 &wui_iof3 278 &wui_iof4 &wui_iof5 &wui_none &wui_none>; 279 280 lvol-maps = <&lvol_iof0 &lvol_iof1 &lvol_iof2 &lvol_iof3 281 &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>; 282 }; 283 284 /* ADC0 comparator configuration in npcx4 series */ 285 adc0: adc@400d1000 { 286 channel-count = <26>; 287 threshold-count = <6>; 288 }; 289 290 /* ADC1 which reference voltage is AVCC */ 291 adc1: adc@400d5000 { 292 compatible = "nuvoton,npcx-adc"; 293 #io-channel-cells = <1>; 294 reg = <0x400d5000 0x2000>; 295 interrupts = <22 3>; 296 clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL4 3>; 297 vref-mv = <3300>; 298 channel-count = <26>; 299 threshold-count = <6>; 300 status = "disabled"; 301 }; 302 303 /* FIU0 configuration in npcx4 series */ 304 qspi_fiu0: quadspi@40020000 { 305 clocks = <&pcc NPCX_CLOCK_BUS_FIU0 NPCX_PWDWN_CTL8 5>; 306 }; 307 308 /* FIU1 configuration in npcx4 series */ 309 qspi_fiu1: quadspi@40021000 { 310 compatible = "nuvoton,npcx-fiu-qspi"; 311 #address-cells = <1>; 312 #size-cells = <0>; 313 reg = <0x40021000 0x1000>; 314 clocks = <&pcc NPCX_CLOCK_BUS_FIU0 NPCX_PWDWN_CTL8 6>; 315 }; 316 317 sha0: sha@148 { 318 compatible = "nuvoton,npcx-sha"; 319 reg = <0x148 0x4c>; 320 context-buffer-size = <240>; 321 status = "disabled"; 322 }; 323 324 shi0: shi@4000f000 { 325 compatible = "nuvoton,npcx-shi-enhanced"; 326 reg = <0x4000f000 0x120>; 327 interrupts = <18 1>; 328 clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>; 329 status = "disabled"; 330 buffer-rx-size = <128>; 331 buffer-tx-size = <128>; 332 shi-cs-wui =<&wui_io53>; 333 }; 334 335 espi0: espi@4000a000 { 336 rx-plsize = <64>; 337 tx-plsize = <64>; 338 339 espi_taf: espitaf@4000a000 { 340 compatible = "nuvoton,npcx-espi-taf"; 341 reg = <0x4000a000 0x2000>; 342 status = "disabled"; 343 }; 344 }; 345 346 rctl: reset-controller@400c3100 { 347 compatible = "nuvoton,npcx-rst"; 348 reg = <0x400c3100 0x14>; 349 #reset-cells = <1>; 350 status = "disabled"; 351 }; 352 353 i3c0: i3c@400f0000 { 354 compatible = "nuvoton,npcx-i3c"; 355 356 /* reg[0]: I3C_1 register, reg[1]: MDMA5 register */ 357 reg-names = "i3c1", "mdma5"; 358 reg = <0x400f0000 0x2000>, 359 <0x40011500 0x100>; 360 361 interrupts = <29 3>; 362 363 /* Reset controller */ 364 resets = <&rctl NPCX_RESET_I3C_1>; 365 366 /* clk[0]: I3C source clock, clk[1]: timeout reference clock */ 367 /* clk[2]: MDMA5 */ 368 clock-names = "mclkd", "apb4", "mdma5"; 369 clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 0>, 370 <&pcc NPCX_CLOCK_BUS_APB4 0 0>, 371 <&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 4>; 372 373 status = "disabled"; 374 #address-cells = <3>; 375 #size-cells = <0>; 376 }; 377 378 i3c1: i3c@400f2000 { 379 compatible = "nuvoton,npcx-i3c"; 380 381 /* reg[0]: I3C_2 register, reg[1]: MDMA6 register */ 382 reg-names = "i3c2", "mdma6"; 383 reg = <0x400f2000 0x2000>, 384 <0x40011600 0x100>; 385 386 interrupts = <66 3>; 387 388 /* Reset controller */ 389 resets = <&rctl NPCX_RESET_I3C_2>; 390 391 /* clk[0]: I3C source clock, clk[1]: timeout reference clock */ 392 /* clk[2]: MDMA6 */ 393 clock-names = "mclkd", "apb4", "mdma6"; 394 clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 2>, 395 <&pcc NPCX_CLOCK_BUS_APB4 0 0>, 396 <&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 5>; 397 398 status = "disabled"; 399 #address-cells = <3>; 400 #size-cells = <0>; 401 }; 402 403 i3c2: i3c@400f4000 { 404 compatible = "nuvoton,npcx-i3c"; 405 406 /* reg[0]: I3C_3 register, reg[1]: MDMA7 register */ 407 reg-names = "i3c1", "mdma7"; 408 reg = <0x400f4000 0x2000>, 409 <0x40011700 0x100>; 410 411 interrupts = <67 3>; 412 413 /* Reset controller */ 414 resets = <&rctl NPCX_RESET_I3C_3>; 415 416 /* clk[0]: I3C source clock, clk[1]: timeout reference clock */ 417 /* clk[2]: MDMA7 */ 418 clock-names = "mclkd", "apb4", "mdma7"; 419 clocks = <&pcc NPCX_CLOCK_BUS_MCLKD NPCX_PWDWN_CTL8 3>, 420 <&pcc NPCX_CLOCK_BUS_APB4 0 0>, 421 <&pcc NPCX_CLOCK_BUS_CORE NPCX_PWDWN_CTL9 6>; 422 423 status = "disabled"; 424 #address-cells = <3>; 425 #size-cells = <0>; 426 }; 427 }; 428 429 soc-if { 430 i2c4_0: io_i2c_ctrl4_port0 { 431 compatible = "nuvoton,npcx-i2c-port"; 432 #address-cells = <1>; 433 #size-cells = <0>; 434 port = <0x40>; 435 controller = <&i2c_ctrl4>; 436 status = "disabled"; 437 }; 438 439 i2c7_1: io_i2c_ctrl7_port1 { 440 compatible = "nuvoton,npcx-i2c-port"; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 port = <0x71>; 444 controller = <&i2c_ctrl7>; 445 status = "disabled"; 446 }; 447 }; 448 449 soc-id { 450 family-id = <0x23>; 451 chip-id = <0x0a>; 452 revision-reg = <0x0000FFFC 4>; 453 }; 454}; 455
