| /Zephyr-latest/soc/intel/intel_adsp/common/include/ |
| D | intel_adsp_hda.h | 36 #define HDA_ADDR(base, regblock_size, stream) ((base) + (stream)*(regblock_size)) argument
39 #define DGCS(base, regblock_size, stream) \ argument
57 #define DGBBA(base, regblock_size, stream) \ argument
61 #define DGBS(base, regblock_size, stream) \ argument
65 #define DGBFPI(base, regblock_size, stream) \ argument
69 #define DGBRP(base, regblock_size, stream) \ argument
73 #define DGBWP(base, regblock_size, stream) \ argument
77 #define DGBSP(base, regblock_size, stream) \ argument
81 #define DGMBS(base, regblock_size, stream) \ argument
85 #define DGLLPI(base, regblock_size, stream) \ argument
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| /Zephyr-latest/drivers/watchdog/ |
| D | wdt_dw.h | 305 static inline void dw_wdt_enable(const uint32_t base) in dw_wdt_enable()
325 static inline void dw_wdt_response_mode_set(const uint32_t base, const bool mode) in dw_wdt_response_mode_set()
344 static inline void dw_wdt_reset_pulse_length_set(const uint32_t base, const uint32_t pclk_cycles) in dw_wdt_reset_pulse_length_set()
360 static inline void dw_wdt_timeout_period_set(const uint32_t base, const uint32_t timeout_period) in dw_wdt_timeout_period_set()
375 static inline uint32_t dw_wdt_timeout_period_get(const uint32_t base) in dw_wdt_timeout_period_get()
386 static inline void dw_wdt_timeout_period_init_set(const uint32_t base, in dw_wdt_timeout_period_init_set()
403 static inline uint32_t dw_wdt_current_counter_value_register_get(const uint32_t base, in dw_wdt_current_counter_value_register_get()
419 static inline void dw_wdt_counter_restart(const uint32_t base) in dw_wdt_counter_restart()
431 static inline uint32_t dw_wdt_interrupt_status_register_get(const uint32_t base) in dw_wdt_interrupt_status_register_get()
443 static inline void dw_wdt_clear_interrupt(const uint32_t base) in dw_wdt_clear_interrupt()
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| D | wdt_intel_adsp.h | 89 static inline void intel_adsp_wdt_pause(uint32_t base, const uint32_t core) in intel_adsp_wdt_pause()
108 static inline void intel_adsp_wdt_resume(uint32_t base, const uint32_t core) in intel_adsp_wdt_resume()
127 static inline void intel_adsp_wdt_reset_set(uint32_t base, const uint32_t core, const bool enable) in intel_adsp_wdt_reset_set()
149 static inline uint32_t intel_adsp_wdt_pointer_get(uint32_t base, const uint32_t core) in intel_adsp_wdt_pointer_get()
162 static inline uint32_t intel_adsp_wdt_version_get(uint32_t base, const uint32_t core) in intel_adsp_wdt_version_get()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_andes_atcspi200.h | 30 #define SPI_TFMAT(base) (base + REG_TFMAT) argument
31 #define SPI_TCTRL(base) (base + REG_TCTRL) argument
32 #define SPI_CMD(base) (base + REG_CMD) argument
33 #define SPI_DATA(base) (base + REG_DATA) argument
34 #define SPI_CTRL(base) (base + REG_CTRL) argument
35 #define SPI_STAT(base) (base + REG_STAT) argument
36 #define SPI_INTEN(base) (base + REG_INTEN) argument
37 #define SPI_INTST(base) (base + REG_INTST) argument
38 #define SPI_TIMIN(base) (base + REG_TIMIN) argument
39 #define SPI_CONFIG(base) (base + REG_CONFIG) argument
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| /Zephyr-latest/drivers/flash/ |
| D | flash_andes_qspi.h | 30 #define QSPI_TFMAT(base) (base + 0x10) argument
31 #define QSPI_TCTRL(base) (base + 0x20) argument
32 #define QSPI_CMD(base) (base + 0x24) argument
33 #define QSPI_ADDR(base) (base + 0x28) argument
34 #define QSPI_DATA(base) (base + 0x2c) argument
35 #define QSPI_CTRL(base) (base + 0x30) argument
36 #define QSPI_STAT(base) (base + 0x34) argument
37 #define QSPI_INTEN(base) (base + 0x38) argument
38 #define QSPI_INTST(base) (base + 0x3c) argument
39 #define QSPI_TIMIN(base) (base + 0x40) argument
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| /Zephyr-latest/drivers/interrupt_controller/ |
| D | intc_gic_common_priv.h | 25 #define IGROUPR(base, n) (base + GIC_DIST_IGROUPR + (n) * 4) argument
26 #define ISENABLER(base, n) (base + GIC_DIST_ISENABLER + (n) * 4) argument
27 #define ICENABLER(base, n) (base + GIC_DIST_ICENABLER + (n) * 4) argument
28 #define ISPENDR(base, n) (base + GIC_DIST_ISPENDR + (n) * 4) argument
29 #define ICPENDR(base, n) (base + GIC_DIST_ICPENDR + (n) * 4) argument
30 #define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n) argument
31 #define ITARGETSR(base, n) (base + GIC_DIST_ITARGETSR + (n) * 4) argument
32 #define ICFGR(base, n) (base + GIC_DIST_ICFGR + (n) * 4) argument
33 #define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4) argument
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| /Zephyr-latest/drivers/counter/ |
| D | counter_imx_epit.c | 18 EPIT_Type *base; member
35 EPIT_Type *base = get_epit_config(dev)->base; in imx_epit_isr() local
49 EPIT_Type *base = config->base; in imx_epit_init() local
66 EPIT_Type *base = get_epit_config(dev)->base; in imx_epit_start() local
82 EPIT_Type *base = get_epit_config(dev)->base; in imx_epit_stop() local
92 EPIT_Type *base = get_epit_config(dev)->base; in imx_epit_get_value() local
102 EPIT_Type *base = get_epit_config(dev)->base; in imx_epit_set_top_value() local
126 EPIT_Type *base = get_epit_config(dev)->base; in imx_epit_get_pending_int() local
133 EPIT_Type *base = get_epit_config(dev)->base; in imx_epit_get_top_value() local
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| D | counter_mcux_gpt.c | 49 GPT_Type *base = get_base(dev); in mcux_gpt_start() local
58 GPT_Type *base = get_base(dev); in mcux_gpt_stop() local
67 GPT_Type *base = get_base(dev); in mcux_gpt_get_value() local
76 GPT_Type *base = get_base(dev); in mcux_gpt_set_alarm() local
107 GPT_Type *base = get_base(dev); in mcux_gpt_cancel_alarm() local
123 GPT_Type *base = get_base(dev); in mcux_gpt_isr() local
148 GPT_Type *base = get_base(dev); in mcux_gpt_get_pending_int() local
157 GPT_Type *base = get_base(dev); in mcux_gpt_set_top_value() local
186 GPT_Type *base; in mcux_gpt_init() local
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| /Zephyr-latest/tests/ztest/base/ |
| D | CMakeLists.txt | 6 project(base) project
13 project(base) project
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| /Zephyr-latest/tests/ztest/zexpect/ |
| D | CMakeLists.txt | 6 project(base) project
11 project(base) project
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| /Zephyr-latest/drivers/dp/ |
| D | swdp_ll_pin.h | 39 static ALWAYS_INLINE void swdp_ll_pin_input(void *const base, uint8_t pin) in swdp_ll_pin_input()
48 static ALWAYS_INLINE void swdp_ll_pin_output(void *const base, uint8_t pin) in swdp_ll_pin_output()
58 static ALWAYS_INLINE void swdp_ll_pin_set(void *const base, uint8_t pin) in swdp_ll_pin_set()
67 static ALWAYS_INLINE void swdp_ll_pin_clr(void *const base, uint8_t pin) in swdp_ll_pin_clr()
76 static ALWAYS_INLINE uint32_t swdp_ll_pin_get(void *const base, uint8_t pin) in swdp_ll_pin_get()
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| /Zephyr-latest/drivers/serial/ |
| D | leuart_gecko.c | 27 LEUART_TypeDef *base; member
52 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_poll_in() local
65 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_poll_out() local
75 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_err_check() local
103 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_fifo_fill() local
118 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_fifo_read() local
132 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_irq_tx_enable() local
140 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_irq_tx_disable() local
148 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_irq_tx_complete() local
156 LEUART_TypeDef *base = DEV_BASE(dev); in leuart_gecko_irq_tx_ready() local
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| D | uart_rzt2m.h | 14 #define RDR(base) ((volatile uint32_t *)(base)) argument
15 #define TDR(base) ((volatile uint32_t *)(base + 0x04)) argument
16 #define CCR0(base) ((volatile uint32_t *)(base + 0x08)) argument
17 #define CCR1(base) ((volatile uint32_t *)(base + 0x0c)) argument
18 #define CCR2(base) ((volatile uint32_t *)(base + 0x10)) argument
19 #define CCR3(base) ((volatile uint32_t *)(base + 0x14)) argument
20 #define CCR4(base) ((volatile uint32_t *)(base + 0x18)) argument
21 #define FCR(base) ((volatile uint32_t *)(base + 0x24)) argument
22 #define CSR(base) ((volatile uint32_t *)(base + 0x48)) argument
23 #define FRSR(base) ((volatile uint32_t *)(base + 0x50)) argument
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| /Zephyr-latest/tests/ztest/fail/core/ |
| D | CMakeLists.txt | 28 project(base) project
35 project(base) project
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| /Zephyr-latest/drivers/i3c/ |
| D | i3c_mcux.c | 73 I3C_Type *base; member
207 static uint32_t mcux_i3c_interrupt_disable(I3C_Type *base) in mcux_i3c_interrupt_disable()
223 static void mcux_i3c_interrupt_enable(I3C_Type *base, uint32_t mask) in mcux_i3c_interrupt_enable()
236 static bool mcux_i3c_has_error(I3C_Type *base) in mcux_i3c_has_error()
265 static inline bool mcux_i3c_error_is_timeout(I3C_Type *base) in mcux_i3c_error_is_timeout()
286 static inline bool mcux_i3c_error_is_nack(I3C_Type *base) in mcux_i3c_error_is_nack()
306 static inline bool mcux_i3c_status_is_set(I3C_Type *base, uint32_t mask) in mcux_i3c_status_is_set()
319 static inline void mcux_i3c_status_wait(I3C_Type *base, uint32_t mask) in mcux_i3c_status_wait()
337 static inline int mcux_i3c_status_wait_timeout(I3C_Type *base, uint32_t mask, in mcux_i3c_status_wait_timeout()
351 static inline void mcux_i3c_status_clear(I3C_Type *base, uint32_t mask) in mcux_i3c_status_clear()
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| /Zephyr-latest/drivers/gpio/ |
| D | gpio_stellaris.c | 23 uint32_t base; member
34 #define GPIO_REG_ADDR(base, offset) (base + offset) argument
36 #define GPIO_RW_ADDR(base, offset, p) \ argument
39 #define GPIO_RW_MASK_ADDR(base, offset, mask) \ argument
58 uint32_t base = cfg->base; in gpio_stellaris_isr() local
70 uint32_t base = cfg->base; in gpio_stellaris_configure() local
116 uint32_t base = cfg->base; in gpio_stellaris_get_config() local
142 uint32_t base = cfg->base; in gpio_stellaris_port_get_raw() local
154 uint32_t base = cfg->base; in gpio_stellaris_port_set_masked_raw() local
165 uint32_t base = cfg->base; in gpio_stellaris_port_set_bits_raw() local
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| D | gpio_ifx_cat1.c | 53 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_configure() local
103 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_get_raw() local
114 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_set_masked_raw() local
125 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_set_bits_raw() local
136 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_clear_bits_raw() local
147 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_port_toggle_bits() local
157 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_get_pending_int() local
165 GPIO_PRT_Type *const base = cfg->regs; in gpio_isr_handler() local
185 GPIO_PRT_Type *const base = cfg->regs; in gpio_cat1_pin_interrupt_configure() local
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| D | gpio_rp1.c | 15 #define GPIO_STATUS(base, n) (base + 0x8 * n) argument
16 #define GPIO_CTRL(base, n) (GPIO_STATUS(base, n) + 0x4) argument
30 #define RIO_OUT(base) (base) argument
31 #define RIO_OE(base) (base + 0x4) argument
32 #define RIO_IN(base) (base + 0x8) argument
37 #define RIO_OUT_SET(base) (RIO_OUT(base) + RIO_SET) argument
38 #define RIO_OUT_CLR(base) (RIO_OUT(base) + RIO_CLR) argument
40 #define RIO_OE_SET(base) (RIO_OE(base) + RIO_SET) argument
41 #define RIO_OE_CLR(base) (RIO_OE(base) + RIO_CLR) argument
43 #define PADS_CTRL(base, n) (base + 0x4 * (n + 1)) argument
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/ |
| D | flash_clock_setup.c | 11 static void flash_deinit(FLEXSPI_Type *base) in flash_deinit()
27 static void flash_init(FLEXSPI_Type *base) in flash_init()
78 void flexspi_setup_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) in flexspi_setup_clock()
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| /Zephyr-latest/drivers/usb/device/ |
| D | usb_dc_dw.c | 63 #define USB_DW_EP_FIFO(base, idx) \ argument
67 struct usb_dwc2_reg *const base; member
185 struct usb_dwc2_reg *const base = usb_dw_cfg.base; in usb_dw_reg_dump() local
253 struct usb_dwc2_reg *const base = usb_dw_cfg.base; in usb_dw_reset() local
288 struct usb_dwc2_reg *const base = usb_dw_cfg.base; in usb_dw_num_dev_eps() local
295 struct usb_dwc2_reg *const base = usb_dw_cfg.base; in usb_dw_flush_tx_fifo() local
305 struct usb_dwc2_reg *const base = usb_dw_cfg.base; in usb_dw_tx_fifo_avail() local
313 struct usb_dwc2_reg *const base = usb_dw_cfg.base; in usb_dw_set_fifo() local
362 struct usb_dwc2_reg *const base = usb_dw_cfg.base; in usb_dw_ep_set() local
448 struct usb_dwc2_reg *const base = usb_dw_cfg.base; in usb_dw_prep_rx() local
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| /Zephyr-latest/soc/nxp/imxrt/imxrt6xx/cm33/ |
| D | flash_clock_setup.c | 17 static void flash_deinit(FLEXSPI_Type *base) in flash_deinit()
27 static void flash_init(FLEXSPI_Type *base) in flash_init()
79 void flexspi_setup_clock(FLEXSPI_Type *base, uint32_t src, uint32_t divider) in flexspi_setup_clock()
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| /Zephyr-latest/drivers/regulator/ |
| D | regulator_nxp_vref.c | 26 VREF_Type *base; member
35 VREF_Type *const base = config->base; in regulator_nxp_vref_enable() local
60 VREF_Type *const base = config->base; in regulator_nxp_vref_disable() local
74 VREF_Type *const base = config->base; in regulator_nxp_vref_set_mode() local
111 VREF_Type *const base = config->base; in regulator_nxp_vref_get_mode() local
143 VREF_Type *const base = config->base; in regulator_nxp_vref_set_voltage() local
162 VREF_Type *const base = config->base; in regulator_nxp_vref_get_voltage() local
188 VREF_Type *const base = config->base; in regulator_nxp_vref_init() local
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| /Zephyr-latest/soc/sensry/ganymed/sy1xx/common/ |
| D | udma.c | 110 int32_t sy1xx_udma_cancel(uint32_t base, uint32_t channel) in sy1xx_udma_cancel()
120 int32_t sy1xx_udma_is_ready(uint32_t base, uint32_t channel) in sy1xx_udma_is_ready()
130 int32_t sy1xx_udma_wait_for_finished(uint32_t base, uint32_t channel) in sy1xx_udma_wait_for_finished()
148 int32_t sy1xx_udma_wait_for_status(uint32_t base) in sy1xx_udma_wait_for_status()
164 int32_t sy1xx_udma_start(uint32_t base, uint32_t channel, uint32_t saddr, uint32_t size, in sy1xx_udma_start()
177 int32_t sy1xx_udma_get_remaining(uint32_t base, uint32_t channel) in sy1xx_udma_get_remaining()
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| /Zephyr-latest/tests/bluetooth/audio/bap_base/src/ |
| D | main.c | 110 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(&fixture->valid_base_ad); in ZTEST_F() local
117 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(&fixture->invalid_base_ad); in ZTEST_F() local
124 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(NULL); in ZTEST_F() local
131 const struct bt_bap_base *base; in ZTEST_F() local
142 const struct bt_bap_base *base; in ZTEST_F() local
153 const struct bt_bap_base *base; in ZTEST_F() local
166 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(&fixture->valid_base_ad); in ZTEST_F() local
185 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(&fixture->valid_base_ad); in ZTEST_F() local
204 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(&fixture->valid_base_ad); in ZTEST_F() local
223 const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(&fixture->valid_base_ad); in ZTEST_F() local
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| /Zephyr-latest/soc/nxp/imxrt/imxrt7xx/cm33/ |
| D | flash_clock_setup.c | 39 static void flash_deinit(XSPI_Type *base, CACHE64_CTRL_Type *cache) in flash_deinit()
60 static void flash_init(XSPI_Type *base, CACHE64_CTRL_Type *cache) in flash_init()
114 void xspi_setup_clock(XSPI_Type *base, uint32_t src, uint32_t divider) in xspi_setup_clock()
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