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Searched refs:SET_BIT (Results 1 – 25 of 84) sorted by relevance

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/trusted-firmware-m-3.4.0/platform/ext/target/stm/common/stm32u5xx/hal/Inc/
Dstm32u5xx_hal.h208 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STO…
213 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STO…
218 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STO…
223 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STO…
228 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STO…
233 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STO…
238 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STO…
243 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STO…
248 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_…
253 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_…
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Dstm32u5xx_hal_rcc.h676 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \
683 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \
690 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \
697 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
704 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
711 … SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \
718 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
726 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \
734 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \
742 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \
[all …]
Dstm32u5xx_hal_pwr_ex.h260 #define __HAL_PWR_UVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM)
272 #define __HAL_PWR_UVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM)
284 #define __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM)
296 #define __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM)
330 #define __HAL_PWR_UVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_UVM)
353 #define __HAL_PWR_IO2VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM)
365 #define __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM)
377 #define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM)
389 #define __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM)
423 #define __HAL_PWR_IO2VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_IO2VM)
[all …]
Dstm32u5xx_hal_pwr.h411 ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \
412 ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \
413 ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \
414 ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \
415 ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \
416 ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \
417 ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \
418 ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \
419 ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \
420 ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \
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Dstm32u5xx_hal_flash.h699 #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN)
711 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
740 { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \
742 … { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
746 { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \
748 … { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
753 { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \
755 … { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\
847 … { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\
849 … { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\
[all …]
/trusted-firmware-m-3.4.0/platform/ext/target/stm/common/stm32u5xx/hal/Src/
Dstm32u5xx_hal_pwr_ex.c400 SET_BIT(PWR->CR3, PWR_CR3_REGSEL); in HAL_PWREx_ConfigSupply()
433 SET_BIT(PWR->CR3, PWR_CR3_FSTEN); in HAL_PWREx_EnableFastSoftStart()
613 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP1Mode()
662 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP2Mode()
712 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSTOP3Mode()
750 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWREx_EnterSHUTDOWNMode()
788 SET_BIT(PWR->CR1, PWR_CR1_ULPMEN); in HAL_PWREx_EnableUltraLowPowerMode()
815 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1); in HAL_PWREx_S3WU_IRQHandler()
828 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2); in HAL_PWREx_S3WU_IRQHandler()
841 SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3); in HAL_PWREx_S3WU_IRQHandler()
[all …]
Dstm32u5xx_hal_pwr.c218 SET_BIT(PWR->DBPR, PWR_DBPR_DBP); in HAL_PWR_EnableBkUpAccess()
442 SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); in HAL_PWR_EnablePVD()
484 SET_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin)); in HAL_PWR_EnableWakeUpPin()
601 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTOPMode()
645 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTANDBYMode()
668 SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); in HAL_PWR_EnableSleepOnExit()
694 SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); in HAL_PWR_EnableSEVOnPend()
848 SET_BIT(PWR->SECCFGR, Item); in HAL_PWR_ConfigAttributes()
849 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); in HAL_PWR_ConfigAttributes()
853 SET_BIT(PWR->SECCFGR, Item); in HAL_PWR_ConfigAttributes()
[all …]
Dstm32u5xx_hal_icache.c221 SET_BIT(ICACHE->CR, ICACHE_CR_EN); in HAL_ICACHE_Enable()
284 SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); in HAL_ICACHE_Invalidate()
315 SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); in HAL_ICACHE_Invalidate_IT()
318 SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); in HAL_ICACHE_Invalidate_IT()
376 SET_BIT(ICACHE->CR, MonitorType); in HAL_ICACHE_Monitor_Start()
416 SET_BIT(ICACHE->CR, (MonitorType << 2U)); in HAL_ICACHE_Monitor_Reset()
Dstm32u5xx_hal_gtzc.c248 SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL); in HAL_GTZC_TZSC_ConfigPeriphAttributes()
249 SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL); in HAL_GTZC_TZSC_ConfigPeriphAttributes()
250 SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL); in HAL_GTZC_TZSC_ConfigPeriphAttributes()
251 SET_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL); in HAL_GTZC_TZSC_ConfigPeriphAttributes()
269 SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL); in HAL_GTZC_TZSC_ConfigPeriphAttributes()
270 SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL); in HAL_GTZC_TZSC_ConfigPeriphAttributes()
271 SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL); in HAL_GTZC_TZSC_ConfigPeriphAttributes()
272 SET_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL); in HAL_GTZC_TZSC_ConfigPeriphAttributes()
296 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); in HAL_GTZC_TZSC_ConfigPeriphAttributes()
313 SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); in HAL_GTZC_TZSC_ConfigPeriphAttributes()
[all …]
Dstm32u5xx_hal.c470 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); in HAL_DBGMCU_EnableDBGStopMode()
488 SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); in HAL_DBGMCU_EnableDBGStandbyMode()
578 SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); in HAL_SYSCFG_EnableVREFBUF()
612 SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); in HAL_SYSCFG_EnableIOAnalogSwitchBooster()
/trusted-firmware-m-3.4.0/platform/ext/target/stm/common/stm32l5xx/hal/Inc/
Dstm32l5xx_hal_rcc.h656 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN); \
664 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN); \
672 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMAMUX1EN); \
679 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \
687 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \
695 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \
703 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZCEN); \
738 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOAEN); \
746 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOBEN); \
754 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_GPIOCEN); \
[all …]
Dstm32l5xx_hal.h275 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STO…
280 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STO…
285 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STO…
290 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STO…
295 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STO…
300 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STO…
305 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP)
310 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STO…
315 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STO…
320 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STO…
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Dstm32l5xx_hal_pwr_ex.h315 #define __HAL_PWR_PVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM1)
327 #define __HAL_PWR_PVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM1)
339 #define __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM1)
351 #define __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM1)
385 #define __HAL_PWR_PVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM1)
408 #define __HAL_PWR_PVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR2, PWR_EXTI_LINE_PVM2)
420 #define __HAL_PWR_PVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR2, PWR_EVENT_LINE_PVM2)
432 #define __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR2, PWR_EXTI_LINE_PVM2)
444 #define __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR2, PWR_EXTI_LINE_PVM2)
478 #define __HAL_PWR_PVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER2, PWR_EXTI_LINE_PVM2)
[all …]
Dstm32l5xx_hal_flash.h617 SET_BIT(FLASH->ACR, FLASH_ACR_RUN_PD); \
635 #define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
663 …_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLAS…
664 …if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_…
675 …_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLAS…
676 …if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_I…
688 …_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { SET_BIT(FLASH->ECCR, FLAS…
689 …if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_I…
817 …(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) { SET_BIT(FLASH->ECCR, ((__…
818 …if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWE…
[all …]
Dstm32l5xx_hal_pwr.h257 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
269 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EVENT_LINE_PVD)
281 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
293 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
327 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
/trusted-firmware-m-3.4.0/platform/ext/target/stm/common/stm32l5xx/hal/Src/
Dstm32l5xx_hal_pwr_ex.c194 SET_BIT(PWR->CR4, PWR_CR4_VBE); in HAL_PWREx_EnableBatteryCharging()
216 SET_BIT(PWR->CR2, PWR_CR2_USV); in HAL_PWREx_EnableVddUSB()
237 SET_BIT(PWR->CR2, PWR_CR2_IOSV); in HAL_PWREx_EnableVddIO2()
280 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); in HAL_PWREx_EnableGPIOPullUp()
284 SET_BIT(PWR->PUCRB, GPIONumber); in HAL_PWREx_EnableGPIOPullUp()
288 SET_BIT(PWR->PUCRC, GPIONumber); in HAL_PWREx_EnableGPIOPullUp()
292 SET_BIT(PWR->PUCRD, GPIONumber); in HAL_PWREx_EnableGPIOPullUp()
296 SET_BIT(PWR->PUCRE, GPIONumber); in HAL_PWREx_EnableGPIOPullUp()
300 SET_BIT(PWR->PUCRF, GPIONumber); in HAL_PWREx_EnableGPIOPullUp()
304 SET_BIT(PWR->PUCRG, GPIONumber); in HAL_PWREx_EnableGPIOPullUp()
[all …]
Dstm32l5xx_hal_pwr.c107 SET_BIT(PWR->CR1, PWR_CR1_DBP); in HAL_PWR_EnableBkUpAccess()
360 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in HAL_PWR_EnablePVD()
401 SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity)); in HAL_PWR_EnableWakeUpPin()
563 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); in HAL_PWR_EnterSTANDBYMode()
586 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); in HAL_PWR_EnableSleepOnExit()
613 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); in HAL_PWR_EnableSEVOnPend()
685 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV); in HAL_PWR_ConfigAttributes()
702 SET_BIT(PWR_S->SECCFGR, Item); in HAL_PWR_ConfigAttributes()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_s1/Native_Driver/
Dtimer_cmsdk_drv.c20 #define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) macro
82 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_enable_external_input()
111 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_external()
126 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_enable()
147 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); in timer_cmsdk_enable_interrupt()
176 SET_BIT(register_map->intreg.intclear, in timer_cmsdk_clear_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/musca_b1/Native_Driver/
Dtimer_cmsdk_drv.c29 #define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) macro
91 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_enable_external_input()
120 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_external()
135 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_enable()
156 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); in timer_cmsdk_enable_interrupt()
185 SET_BIT(register_map->intreg.intclear, in timer_cmsdk_clear_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps2/an519/native_drivers/timer_cmsdk/
Dtimer_cmsdk.c29 #define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) macro
91 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in cmsdk_timer_enable_external_input()
120 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in cmsdk_timer_set_clock_to_external()
135 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in cmsdk_timer_enable()
156 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); in cmsdk_timer_enable_interrupt()
185 SET_BIT(register_map->intreg.intclear, in cmsdk_timer_clear_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an524/native_drivers/
Dtimer_cmsdk_drv.c29 #define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) macro
93 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in timer_cmsdk_enable_external_input()
122 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in timer_cmsdk_set_clock_to_external()
137 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in timer_cmsdk_enable()
158 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); in timer_cmsdk_enable_interrupt()
187 SET_BIT(register_map->intreg.intclear, in timer_cmsdk_clear_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps2/an521/native_drivers/timer_cmsdk/
Dtimer_cmsdk.c29 #define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) macro
91 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_ENABLE_INDEX); in cmsdk_timer_enable_external_input()
120 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_EXTERNAL_INPUT_CLOCK_INDEX); in cmsdk_timer_set_clock_to_external()
135 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_ENABLE_INDEX); in cmsdk_timer_enable()
156 SET_BIT(register_map->ctrl, CTRL_REG_ENUM_IRQ_ENABLE_INDEX); in cmsdk_timer_enable_interrupt()
185 SET_BIT(register_map->intreg.intclear, in cmsdk_timer_clear_interrupt()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/rss/common/native_drivers/
Dsyscounter_armv8-m_cntrl_drv.c51 #define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) macro
207 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_EN_OFF); in syscounter_armv8_m_cntrl_enable_counter()
232 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_HDBG_OFF); in syscounter_armv8_m_cntrl_enable_halt_on_debug()
257 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_SCEN_OFF); in syscounter_armv8_m_cntrl_enable_scale()
282 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRMASK_OFF); in syscounter_armv8_m_cntrl_enable_interrupt()
307 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_PSLVERRDIS_OFF); in syscounter_armv8_m_cntrl_enable_pslverr()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/corstone310/common/native_drivers/
Dsyscounter_armv8-m_cntrl_drv.c52 #define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) macro
155 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_EN_OFF); in syscounter_armv8_m_cntrl_enable_counter()
180 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_HDBG_OFF); in syscounter_armv8_m_cntrl_enable_halt_on_debug()
205 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_SCEN_OFF); in syscounter_armv8_m_cntrl_enable_scale()
230 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRMASK_OFF); in syscounter_armv8_m_cntrl_enable_interrupt()
255 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_PSLVERRDIS_OFF); in syscounter_armv8_m_cntrl_enable_pslverr()
/trusted-firmware-m-3.4.0/platform/ext/target/arm/mps3/an552/native_drivers/
Dsyscounter_armv8-m_cntrl_drv.c51 #define SET_BIT(WORD, BIT_INDEX) ((WORD) |= (1U << (BIT_INDEX))) macro
207 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_EN_OFF); in syscounter_armv8_m_cntrl_enable_counter()
232 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_HDBG_OFF); in syscounter_armv8_m_cntrl_enable_halt_on_debug()
257 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_SCEN_OFF); in syscounter_armv8_m_cntrl_enable_scale()
282 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_INTRMASK_OFF); in syscounter_armv8_m_cntrl_enable_interrupt()
307 SET_BIT(p_cnt->cntcr, SYSCOUNTER_ARMV8M_CNTCR_PSLVERRDIS_OFF); in syscounter_armv8_m_cntrl_enable_pslverr()

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