1 /** 2 ****************************************************************************** 3 * @file stm32l5xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * <h2><center>© Copyright (c) 2019 STMicroelectronics. 11 * All rights reserved.</center></h2> 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef STM32L5xx_HAL_H 23 #define STM32L5xx_HAL_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32l5xx_hal_conf.h" 31 32 /** @addtogroup STM32L5xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup HAL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup HAL_Exported_Types HAL Exported Types 42 * @{ 43 */ 44 45 /** @defgroup HAL_TICK_FREQ Tick Frequency 46 * @{ 47 */ 48 typedef enum 49 { 50 HAL_TICK_FREQ_10HZ = 100U, 51 HAL_TICK_FREQ_100HZ = 10U, 52 HAL_TICK_FREQ_1KHZ = 1U, 53 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 54 } HAL_TickFreqTypeDef; 55 /** 56 * @} 57 */ 58 59 /** 60 * @} 61 */ 62 63 /* Exported constants --------------------------------------------------------*/ 64 /** @defgroup HAL_Exported_Constants HAL Exported Constants 65 * @{ 66 */ 67 68 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 69 * @{ 70 */ 71 72 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 73 * @{ 74 */ 75 #define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 76 #define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 77 #define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 78 #define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 79 #define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 80 #define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 81 82 /** 83 * @} 84 */ 85 86 /** @defgroup SYSCFG_SRAM2WRP_0_31 SRAM2 Page Write protection (0 to 31) 87 * @{ 88 */ 89 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_P0WP /*!< SRAM2 Write protection page 0 */ 90 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_P1WP /*!< SRAM2 Write protection page 1 */ 91 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_P2WP /*!< SRAM2 Write protection page 2 */ 92 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_P3WP /*!< SRAM2 Write protection page 3 */ 93 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_P4WP /*!< SRAM2 Write protection page 4 */ 94 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_P5WP /*!< SRAM2 Write protection page 5 */ 95 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_P6WP /*!< SRAM2 Write protection page 6 */ 96 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_P7WP /*!< SRAM2 Write protection page 7 */ 97 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_P8WP /*!< SRAM2 Write protection page 8 */ 98 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_P9WP /*!< SRAM2 Write protection page 9 */ 99 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_P10WP /*!< SRAM2 Write protection page 10 */ 100 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_P11WP /*!< SRAM2 Write protection page 11 */ 101 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_P12WP /*!< SRAM2 Write protection page 12 */ 102 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_P13WP /*!< SRAM2 Write protection page 13 */ 103 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_P14WP /*!< SRAM2 Write protection page 14 */ 104 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_P15WP /*!< SRAM2 Write protection page 15 */ 105 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_P16WP /*!< SRAM2 Write protection page 16 */ 106 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_P17WP /*!< SRAM2 Write protection page 17 */ 107 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_P18WP /*!< SRAM2 Write protection page 18 */ 108 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_P19WP /*!< SRAM2 Write protection page 19 */ 109 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_P20WP /*!< SRAM2 Write protection page 20 */ 110 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_P21WP /*!< SRAM2 Write protection page 21 */ 111 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_P22WP /*!< SRAM2 Write protection page 22 */ 112 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_P23WP /*!< SRAM2 Write protection page 23 */ 113 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_P24WP /*!< SRAM2 Write protection page 24 */ 114 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_P25WP /*!< SRAM2 Write protection page 25 */ 115 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_P26WP /*!< SRAM2 Write protection page 26 */ 116 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_P27WP /*!< SRAM2 Write protection page 27 */ 117 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_P28WP /*!< SRAM2 Write protection page 28 */ 118 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_P29WP /*!< SRAM2 Write protection page 29 */ 119 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_P30WP /*!< SRAM2 Write protection page 30 */ 120 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_P31WP /*!< SRAM2 Write protection page 31 */ 121 /** 122 * @} 123 */ 124 125 /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) 126 * @{ 127 */ 128 #define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_P32WP /*!< SRAM2 Write protection page 32 */ 129 #define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_P33WP /*!< SRAM2 Write protection page 33 */ 130 #define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_P34WP /*!< SRAM2 Write protection page 34 */ 131 #define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_P35WP /*!< SRAM2 Write protection page 35 */ 132 #define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_P36WP /*!< SRAM2 Write protection page 36 */ 133 #define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_P37WP /*!< SRAM2 Write protection page 37 */ 134 #define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_P38WP /*!< SRAM2 Write protection page 38 */ 135 #define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_P39WP /*!< SRAM2 Write protection page 39 */ 136 #define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_P40WP /*!< SRAM2 Write protection page 40 */ 137 #define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_P41WP /*!< SRAM2 Write protection page 41 */ 138 #define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_P42WP /*!< SRAM2 Write protection page 42 */ 139 #define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_P43WP /*!< SRAM2 Write protection page 43 */ 140 #define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_P44WP /*!< SRAM2 Write protection page 44 */ 141 #define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_P45WP /*!< SRAM2 Write protection page 45 */ 142 #define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_P46WP /*!< SRAM2 Write protection page 46 */ 143 #define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_P47WP /*!< SRAM2 Write protection page 47 */ 144 #define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_P48WP /*!< SRAM2 Write protection page 48 */ 145 #define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_P49WP /*!< SRAM2 Write protection page 49 */ 146 #define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_P50WP /*!< SRAM2 Write protection page 50 */ 147 #define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_P51WP /*!< SRAM2 Write protection page 51 */ 148 #define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_P52WP /*!< SRAM2 Write protection page 52 */ 149 #define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_P53WP /*!< SRAM2 Write protection page 53 */ 150 #define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_P54WP /*!< SRAM2 Write protection page 54 */ 151 #define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_P55WP /*!< SRAM2 Write protection page 55 */ 152 #define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_P56WP /*!< SRAM2 Write protection page 56 */ 153 #define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_P57WP /*!< SRAM2 Write protection page 57 */ 154 #define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_P58WP /*!< SRAM2 Write protection page 58 */ 155 #define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_P59WP /*!< SRAM2 Write protection page 59 */ 156 #define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_P60WP /*!< SRAM2 Write protection page 60 */ 157 #define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_P61WP /*!< SRAM2 Write protection page 61 */ 158 #define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_P62WP /*!< SRAM2 Write protection page 62 */ 159 #define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_P63WP /*!< SRAM2 Write protection page 63 */ 160 /** 161 * @} 162 */ 163 164 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 165 * @{ 166 */ 167 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 0U /*!< Voltage reference scale 0 (VREF_OUT1) */ 168 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ 169 170 /** 171 * @} 172 */ 173 174 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 175 * @{ 176 */ 177 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE 0U /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 178 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 179 180 /** 181 * @} 182 */ 183 184 /** @defgroup SYSCFG_flags_definition Flags 185 * @{ 186 */ 187 188 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 189 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 190 191 /** 192 * @} 193 */ 194 195 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 196 * @{ 197 */ 198 199 /** @brief Fast-mode Plus driving capability on a specific GPIO 200 */ 201 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 202 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 203 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 204 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 205 206 /** 207 * @} 208 */ 209 210 /** @defgroup SYSCFG_Lock_items SYSCFG Lock items 211 * @brief SYSCFG items to set lock on 212 * @{ 213 */ 214 #define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ 215 #define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ 216 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 217 #define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ 218 #define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ 219 #define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ 220 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */ 221 #else 222 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 223 #endif /* __ARM_FEATURE_CMSE */ 224 /** 225 * @} 226 */ 227 228 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 229 230 /** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items 231 * @brief SYSCFG items to configure secure or non-secure attributes on 232 * @{ 233 */ 234 #define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */ 235 #define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */ 236 #define SYSCFG_SRAM2 SYSCFG_SECCFGR_SRAM2SEC /*!< SRAM2 */ 237 #define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */ 238 #define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_SRAM2 | SYSCFG_FPU) /*!< All */ 239 /** 240 * @} 241 */ 242 243 /** @defgroup SYSCFG_attributes SYSCFG attributes 244 * @brief SYSCFG secure or non-secure attributes 245 * @{ 246 */ 247 #define SYSCFG_SEC 0x00000001U /*!< Secure attribute */ 248 #define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */ 249 /** 250 * @} 251 */ 252 253 #endif /* __ARM_FEATURE_CMSE */ 254 255 /** 256 * @} 257 */ 258 259 /** 260 * @} 261 */ 262 263 /* Exported macros -----------------------------------------------------------*/ 264 /** @defgroup HAL_Exported_Macros HAL Exported Macros 265 * @{ 266 */ 267 268 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 269 * @{ 270 */ 271 272 /** @brief Freeze/Unfreeze Peripherals in Debug mode 273 */ 274 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 275 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 276 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 277 #endif 278 279 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 280 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 281 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 282 #endif 283 284 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 285 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 286 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 287 #endif 288 289 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 290 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 291 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 292 #endif 293 294 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 295 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 296 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 297 #endif 298 299 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 300 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 301 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 302 #endif 303 304 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) 305 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 306 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 307 #endif 308 309 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 310 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 311 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 312 #endif 313 314 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 315 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 316 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 317 #endif 318 319 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 320 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 321 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 322 #endif 323 324 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 325 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 326 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 327 #endif 328 329 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) 330 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 331 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 332 #endif 333 334 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 335 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 336 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 337 #endif 338 339 #if defined(DBGMCU_APB1FZR1_DBG_FDCAN1_STOP) 340 #define __HAL_DBGMCU_FREEZE_FDCAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_FDCAN1_STOP) 341 #define __HAL_DBGMCU_UNFREEZE_FDCAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_FDCAN1_STOP) 342 #endif 343 344 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 345 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 346 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 347 #endif 348 349 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 350 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 351 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 352 #endif 353 354 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM3_STOP) 355 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM3_STOP) 356 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM3_STOP) 357 #endif 358 359 #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) 360 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 361 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 362 #endif 363 364 #if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) 365 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 366 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 367 #endif 368 369 #if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) 370 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 371 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 372 #endif 373 374 #if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) 375 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 376 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 377 #endif 378 379 #if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) 380 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 381 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 382 #endif 383 384 /** 385 * @} 386 */ 387 388 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 389 * @{ 390 */ 391 392 /** @brief SRAM2 page 0 to 31 write protection enable macro 393 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_0_31 394 * @note Write protection can only be disabled by a system reset 395 */ 396 #define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 397 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ 398 }while(0) 399 400 /** @brief SRAM2 page 32 to 63 write protection enable macro 401 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 402 * @note Write protection can only be disabled by a system reset 403 */ 404 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 405 SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ 406 }while(0) 407 408 /** @brief SRAM2 page write protection unlock prior to erase 409 * @note Writing a wrong key reactivates the write protection 410 */ 411 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ 412 SYSCFG->SKR = 0x53;\ 413 }while(0) 414 415 /** @brief SRAM2 erase 416 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase 417 */ 418 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) 419 420 /** @brief Floating Point Unit interrupt enable/disable macros 421 * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts 422 */ 423 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 424 SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 425 }while(0) 426 427 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 428 CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 429 }while(0) 430 431 /** @brief SYSCFG Break ECC lock. 432 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 433 * @note The selected configuration is locked and can be unlocked only by system reset. 434 */ 435 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 436 437 /** @brief SYSCFG Break Cortex-M33 Lockup lock. 438 * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 439 * @note The selected configuration is locked and can be unlocked only by system reset. 440 */ 441 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 442 443 /** @brief SYSCFG Break PVD lock. 444 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 445 * @note The selected configuration is locked and can be unlocked only by system reset. 446 */ 447 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 448 449 /** @brief SYSCFG Break SRAM2 parity lock. 450 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 451 * @note The selected configuration is locked and can be unlocked by system reset. 452 */ 453 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 454 455 /** @brief Check SYSCFG flag is set or not. 456 * @param __FLAG__ specifies the flag to check. 457 * This parameter can be one of the following values: 458 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 459 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 460 * @retval The new state of __FLAG__ (TRUE or FALSE). 461 */ 462 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ 463 & (__FLAG__))!= 0U) ? 1U : 0U) 464 465 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 466 */ 467 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 468 469 /** @brief Fast-mode Plus driving capability enable/disable macros 470 * @param __FASTMODEPLUS__ This parameter can be a value of : 471 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 472 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 473 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 474 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 475 */ 476 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 477 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 478 }while(0) 479 480 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 481 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 482 }while(0) 483 484 /** 485 * @} 486 */ 487 488 /** 489 * @} 490 */ 491 492 /* Private macros ------------------------------------------------------------*/ 493 /** @defgroup HAL_Private_Macros HAL Private Macros 494 * @{ 495 */ 496 497 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 498 * @{ 499 */ 500 501 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 502 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 503 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 504 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 505 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 506 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 507 508 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 509 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 510 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 511 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 512 513 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFUL)) 514 515 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 516 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 517 518 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 519 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 520 521 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 522 523 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 524 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 525 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 526 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 527 528 529 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 530 531 #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ 532 ((__ATTRIBUTES__) == SYSCFG_NSEC)) 533 534 #define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_CLK) == SYSCFG_CLK) || \ 535 (((__ITEM__) & SYSCFG_CLK) == SYSCFG_CLASSB) || \ 536 (((__ITEM__) & SYSCFG_SRAM2) == SYSCFG_SRAM2) || \ 537 (((__ITEM__) & SYSCFG_FPU) == SYSCFG_CLK) || \ 538 (((__ITEM__) & ~(SYSCFG_ALL)) == 0U)) 539 540 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 541 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 542 (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \ 543 (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \ 544 (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC) || \ 545 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 546 547 #else 548 549 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 550 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 551 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 552 553 554 #endif /* __ARM_FEATURE_CMSE */ 555 556 /** 557 * @} 558 */ 559 560 /** 561 * @} 562 */ 563 564 /* Exported variables --------------------------------------------------------*/ 565 566 /** @addtogroup HAL_Exported_Variables 567 * @{ 568 */ 569 extern __IO uint32_t uwTick; 570 extern uint32_t uwTickPrio; 571 extern HAL_TickFreqTypeDef uwTickFreq; 572 /** 573 * @} 574 */ 575 576 /* Exported functions --------------------------------------------------------*/ 577 578 /** @addtogroup HAL_Exported_Functions 579 * @{ 580 */ 581 582 /** @addtogroup HAL_Exported_Functions_Group1 583 * @{ 584 */ 585 586 /* Initialization and de-initialization functions ******************************/ 587 HAL_StatusTypeDef HAL_Init(void); 588 HAL_StatusTypeDef HAL_DeInit(void); 589 void HAL_MspInit(void); 590 void HAL_MspDeInit(void); 591 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 592 593 /** 594 * @} 595 */ 596 597 /** @addtogroup HAL_Exported_Functions_Group2 598 * @{ 599 */ 600 601 /* Peripheral Control functions ************************************************/ 602 void HAL_IncTick(void); 603 void HAL_Delay(uint32_t Delay); 604 uint32_t HAL_GetTick(void); 605 uint32_t HAL_GetTickPrio(void); 606 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 607 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 608 void HAL_SuspendTick(void); 609 void HAL_ResumeTick(void); 610 uint32_t HAL_GetHalVersion(void); 611 uint32_t HAL_GetREVID(void); 612 uint32_t HAL_GetDEVID(void); 613 uint32_t HAL_GetUIDw0(void); 614 uint32_t HAL_GetUIDw1(void); 615 uint32_t HAL_GetUIDw2(void); 616 617 /** 618 * @} 619 */ 620 621 /** @addtogroup HAL_Exported_Functions_Group3 622 * @{ 623 */ 624 625 /* DBGMCU Peripheral Control functions *****************************************/ 626 void HAL_DBGMCU_EnableDBGStopMode(void); 627 void HAL_DBGMCU_DisableDBGStopMode(void); 628 void HAL_DBGMCU_EnableDBGStandbyMode(void); 629 void HAL_DBGMCU_DisableDBGStandbyMode(void); 630 631 /** 632 * @} 633 */ 634 635 /** @addtogroup HAL_Exported_Functions_Group4 636 * @{ 637 */ 638 639 /* SYSCFG Control functions ****************************************************/ 640 void HAL_SYSCFG_SRAM2Erase(void); 641 642 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 643 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 644 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 645 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 646 void HAL_SYSCFG_DisableVREFBUF(void); 647 648 void HAL_SYSCFG_EnableIOAnalogBooster(void); 649 void HAL_SYSCFG_DisableIOAnalogBooster(void); 650 void HAL_SYSCFG_EnableIOAnalogSwitchVdd(void); 651 void HAL_SYSCFG_DisableIOAnalogSwitchVdd(void); 652 653 /** 654 * @} 655 */ 656 657 /** @addtogroup HAL_Exported_Functions_Group5 658 * @{ 659 */ 660 661 /* SYSCFG Lock functions ********************************************/ 662 void HAL_SYSCFG_Lock(uint32_t Item); 663 HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); 664 665 /** 666 * @} 667 */ 668 669 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 670 671 /** @addtogroup HAL_Exported_Functions_Group6 672 * @{ 673 */ 674 675 /* SYSCFG Attributes functions ********************************************/ 676 void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); 677 HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 678 679 /** 680 * @} 681 */ 682 683 #endif /* __ARM_FEATURE_CMSE */ 684 685 /** 686 * @} 687 */ 688 689 /** 690 * @} 691 */ 692 693 /** 694 * @} 695 */ 696 697 #ifdef __cplusplus 698 } 699 #endif 700 701 #endif /* STM32L5xx_HAL_H */ 702 703 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 704
