1 /** 2 ****************************************************************************** 3 * @file stm32u5xx_hal.h 4 * @author MCD Application Team 5 * @brief This file contains all the functions prototypes for the HAL 6 * module driver. 7 ****************************************************************************** 8 * @attention 9 * 10 * Copyright (c) 2021 STMicroelectronics. 11 * All rights reserved. 12 * 13 * This software component is licensed by ST under BSD 3-Clause license, 14 * the "License"; You may not use this file except in compliance with the 15 * License. You may obtain a copy of the License at: 16 * opensource.org/licenses/BSD-3-Clause 17 * 18 ****************************************************************************** 19 */ 20 21 /* Define to prevent recursive inclusion -------------------------------------*/ 22 #ifndef __STM32U5xx_HAL_H 23 #define __STM32U5xx_HAL_H 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 /* Includes ------------------------------------------------------------------*/ 30 #include "stm32u5xx_hal_conf.h" 31 32 /** @addtogroup STM32U5xx_HAL_Driver 33 * @{ 34 */ 35 36 /** @addtogroup HAL 37 * @{ 38 */ 39 40 /* Exported types ------------------------------------------------------------*/ 41 /** @defgroup HAL_Exported_Types HAL Exported Types 42 * @{ 43 */ 44 45 /** @defgroup HAL_TICK_FREQ Tick Frequency 46 * @{ 47 */ 48 typedef enum 49 { 50 HAL_TICK_FREQ_10HZ = 100U, 51 HAL_TICK_FREQ_100HZ = 10U, 52 HAL_TICK_FREQ_1KHZ = 1U, 53 HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ 54 } HAL_TickFreqTypeDef; 55 /** 56 * @} 57 */ 58 59 /** 60 * @} 61 */ 62 63 /* Exported variables --------------------------------------------------------*/ 64 /** @defgroup HAL_Exported_Variables HAL Exported Variables 65 * @{ 66 */ 67 extern __IO uint32_t uwTick; 68 extern uint32_t uwTickPrio; 69 extern HAL_TickFreqTypeDef uwTickFreq; 70 /** 71 * @} 72 */ 73 74 /* Exported constants --------------------------------------------------------*/ 75 /** @defgroup REV_ID device revision ID 76 * @{ 77 */ 78 #define REV_ID_A 0x1000U /*!< STM32U5 rev.A */ 79 #define REV_ID_B 0x2000U /*!< STM32U5 rev.B */ 80 /** 81 * @} 82 */ 83 84 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 85 * @{ 86 */ 87 88 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 89 * @{ 90 */ 91 #define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 92 #define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 93 #define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 94 #define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 95 #define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 96 #define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 97 98 /** 99 * @} 100 */ 101 102 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 103 * @{ 104 */ 105 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 106 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ 107 #define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ 108 #define SYSCFG_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ 109 110 /** 111 * @} 112 */ 113 114 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 115 * @{ 116 */ 117 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to 118 Voltage reference buffer output */ 119 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 120 121 /** 122 * @} 123 */ 124 125 /** @defgroup SYSCFG_flags_definition Flags 126 * @{ 127 */ 128 129 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 130 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 131 132 /** 133 * @} 134 */ 135 136 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 137 * @{ 138 */ 139 140 /** @brief Fast-mode Plus driving capability on a specific GPIO 141 */ 142 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 143 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 144 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 145 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 146 147 /** 148 * @} 149 */ 150 151 /** @defgroup SYSCFG_Lock_items SYSCFG Lock items 152 * @brief SYSCFG items to set lock on 153 * @{ 154 */ 155 #define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ 156 #define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ 157 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 158 #define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ 159 #define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ 160 #define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ 161 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */ 162 #else 163 #define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ 164 #endif /* __ARM_FEATURE_CMSE */ 165 /** 166 * @} 167 */ 168 169 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 170 171 /** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items 172 * @brief SYSCFG items to configure secure or non-secure attributes on 173 * @{ 174 */ 175 #define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */ 176 #define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */ 177 #define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */ 178 #define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */ 179 /** 180 * @} 181 */ 182 183 /** @defgroup SYSCFG_attributes SYSCFG attributes 184 * @brief SYSCFG secure or non-secure attributes 185 * @{ 186 */ 187 #define SYSCFG_SEC 0x00000001U /*!< Secure attribute */ 188 #define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */ 189 /** 190 * @} 191 */ 192 193 #endif /* __ARM_FEATURE_CMSE */ 194 195 /** 196 * @} 197 */ 198 199 /* Exported macros -----------------------------------------------------------*/ 200 201 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 202 * @{ 203 */ 204 205 /** @brief Freeze/Unfreeze Peripherals in Debug mode 206 */ 207 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 208 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 209 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 210 #endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ 211 212 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 213 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 214 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 215 #endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ 216 217 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 218 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 219 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 220 #endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ 221 222 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 223 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 224 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 225 #endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ 226 227 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 228 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 229 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 230 #endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ 231 232 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 233 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 234 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 235 #endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ 236 237 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 238 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 239 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 240 #endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ 241 242 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 243 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 244 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 245 #endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ 246 247 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 248 #define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 249 #define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 250 #endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ 251 252 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 253 #define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 254 #define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 255 #endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ 256 257 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 258 #define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 259 #define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 260 #endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ 261 262 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 263 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 264 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 265 #endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ 266 267 #if defined(DBGMCU_APB1FZR2_DBG_FDCAN_STOP) 268 #define __HAL_DBGMCU_FREEZE_FDCAN() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP) 269 #define __HAL_DBGMCU_UNFREEZE_FDCAN() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_FDCAN_STOP) 270 #endif /* DBGMCU_APB1FZR2_DBG_FDCAN_STOP */ 271 272 #if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) 273 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 274 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) 275 #endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ 276 277 #if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) 278 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 279 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) 280 #endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */ 281 282 #if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) 283 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 284 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) 285 #endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */ 286 287 #if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) 288 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 289 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) 290 #endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ 291 292 #if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) 293 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 294 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) 295 #endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ 296 297 #if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP) 298 #define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 299 #define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) 300 #endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */ 301 302 #if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 303 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 304 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) 305 #endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */ 306 307 #if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 308 #define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 309 #define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) 310 #endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */ 311 312 #if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 313 #define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 314 #define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) 315 #endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */ 316 317 #if defined(DBGMCU_APB3FZR_DBG_RTC_STOP) 318 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 319 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) 320 #endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */ 321 322 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 323 #define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 324 #define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) 325 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA0_STOP */ 326 327 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 328 #define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 329 #define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) 330 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_STOP */ 331 332 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 333 #define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 334 #define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) 335 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_STOP */ 336 337 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 338 #define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 339 #define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) 340 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA3_STOP */ 341 342 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 343 #define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 344 #define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) 345 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA4_STOP */ 346 347 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 348 #define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 349 #define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) 350 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA5_STOP */ 351 352 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 353 #define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 354 #define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) 355 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA6_STOP */ 356 357 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 358 #define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 359 #define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) 360 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA7_STOP */ 361 362 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 363 #define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 364 #define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) 365 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA8_STOP */ 366 367 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 368 #define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 369 #define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) 370 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA9_STOP */ 371 372 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 373 #define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 374 #define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) 375 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA10_STOP */ 376 377 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 378 #define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 379 #define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) 380 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA11_STOP */ 381 382 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 383 #define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 384 #define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) 385 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA12_STOP */ 386 387 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 388 #define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 389 #define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) 390 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA13_STOP */ 391 392 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 393 #define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 394 #define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) 395 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA14_STOP */ 396 397 #if defined(DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 398 #define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 399 #define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) 400 #endif /* DBGMCU_AHB1FZR_DBG_GPDMA15_STOP */ 401 402 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 403 #define __HAL_DBGMCU_FREEZE_LPDMA0() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 404 #define __HAL_DBGMCU_UNFREEZE_LPDMA0() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) 405 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA0_STOP */ 406 407 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 408 #define __HAL_DBGMCU_FREEZE_LPDMA1() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 409 #define __HAL_DBGMCU_UNFREEZE_LPDMA1() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) 410 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA1_STOP */ 411 412 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 413 #define __HAL_DBGMCU_FREEZE_LPDMA2() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 414 #define __HAL_DBGMCU_UNFREEZE_LPDMA2() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) 415 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA2_STOP */ 416 417 #if defined(DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 418 #define __HAL_DBGMCU_FREEZE_LPDMA3() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 419 #define __HAL_DBGMCU_UNFREEZE_LPDMA3() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) 420 #endif /* DBGMCU_AHB3FZR_DBG_LPDMA3_STOP */ 421 422 /** 423 * @} 424 */ 425 426 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 427 * @{ 428 */ 429 430 /** @brief Floating Point Unit interrupt enable/disable macros 431 * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts 432 */ 433 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 434 SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 435 }while(0) 436 437 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 438 CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ 439 }while(0) 440 441 /** @brief SYSCFG Break ECC lock. 442 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 443 * @note The selected configuration is locked and can be unlocked only by system reset. 444 */ 445 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 446 447 /** @brief SYSCFG Break Cortex-M33 Lockup lock. 448 * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 449 * @note The selected configuration is locked and can be unlocked only by system reset. 450 */ 451 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 452 453 /** @brief SYSCFG Break PVD lock. 454 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in 455 * the PWR_CR2 register. 456 * @note The selected configuration is locked and can be unlocked only by system reset. 457 */ 458 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 459 460 /** @brief SYSCFG Break SRAM2 parity lock. 461 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 462 * @note The selected configuration is locked and can be unlocked by system reset. 463 */ 464 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 465 466 /** @brief Check SYSCFG flag is set or not. 467 * @param __FLAG__: specifies the flag to check. 468 * This parameter can be one of the following values: 469 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 470 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 471 * @retval The new state of __FLAG__ (TRUE or FALSE). 472 */ 473 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ 474 & (__FLAG__))!= 0) ? 1 : 0) 475 476 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 477 */ 478 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 479 480 /** @brief Fast-mode Plus driving capability enable/disable macros 481 * @param __FASTMODEPLUS__: This parameter can be a value of : 482 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 483 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 484 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 485 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 486 */ 487 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ 488 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 489 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 490 }while(0) 491 492 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ 493 do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 494 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 495 }while(0) 496 497 /** 498 * @} 499 */ 500 501 /* Private macros ------------------------------------------------------------*/ 502 503 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 504 * @{ 505 */ 506 507 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 508 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 509 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 510 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 511 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 512 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 513 514 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 515 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 516 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 517 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 518 519 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 520 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ 521 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ 522 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) 523 524 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 525 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 526 527 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 528 529 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 530 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 531 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 532 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 533 534 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 535 536 #define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ 537 ((__ATTRIBUTES__) == SYSCFG_NSEC)) 538 539 #define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_CLK) == SYSCFG_CLK) || \ 540 (((__ITEM__) & SYSCFG_CLASSB) == SYSCFG_CLASSB) || \ 541 (((__ITEM__) & SYSCFG_FPU) == SYSCFG_FPU) || \ 542 (((__ITEM__) & ~(SYSCFG_ALL)) == 0U)) 543 544 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 545 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 546 (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \ 547 (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \ 548 (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC) || \ 549 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 550 551 #else 552 553 #define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ 554 (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ 555 (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) 556 557 558 #endif /* __ARM_FEATURE_CMSE */ 559 /** 560 * @} 561 */ 562 563 /** @defgroup HAL_Private_Macros HAL Private Macros 564 * @{ 565 */ 566 #define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ 567 ((FREQ) == HAL_TICK_FREQ_100HZ) || \ 568 ((FREQ) == HAL_TICK_FREQ_1KHZ)) 569 /** 570 * @} 571 */ 572 /* Exported functions --------------------------------------------------------*/ 573 574 /** @addtogroup HAL_Exported_Functions 575 * @{ 576 */ 577 578 /** @addtogroup HAL_Exported_Functions_Group1 579 * @{ 580 */ 581 582 /* Initialization and de-initialization functions ******************************/ 583 HAL_StatusTypeDef HAL_Init(void); 584 HAL_StatusTypeDef HAL_DeInit(void); 585 void HAL_MspInit(void); 586 void HAL_MspDeInit(void); 587 HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); 588 589 /** 590 * @} 591 */ 592 593 /** @addtogroup HAL_Exported_Functions_Group2 594 * @{ 595 */ 596 597 /* Peripheral Control functions ************************************************/ 598 void HAL_IncTick(void); 599 void HAL_Delay(uint32_t Delay); 600 uint32_t HAL_GetTick(void); 601 uint32_t HAL_GetTickPrio(void); 602 HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); 603 HAL_TickFreqTypeDef HAL_GetTickFreq(void); 604 void HAL_SuspendTick(void); 605 void HAL_ResumeTick(void); 606 uint32_t HAL_GetHalVersion(void); 607 uint32_t HAL_GetREVID(void); 608 uint32_t HAL_GetDEVID(void); 609 610 /** 611 * @} 612 */ 613 614 /** @addtogroup HAL_Exported_Functions_Group3 615 * @{ 616 */ 617 618 /* DBGMCU Peripheral Control functions *****************************************/ 619 void HAL_DBGMCU_EnableDBGStopMode(void); 620 void HAL_DBGMCU_DisableDBGStopMode(void); 621 void HAL_DBGMCU_EnableDBGStandbyMode(void); 622 void HAL_DBGMCU_DisableDBGStandbyMode(void); 623 624 /** 625 * @} 626 */ 627 628 /** @addtogroup HAL_Exported_Functions_Group4 629 * @{ 630 */ 631 632 /* SYSCFG Control functions ****************************************************/ 633 void HAL_SYSCFG_SRAM2Erase(void); 634 635 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 636 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 637 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 638 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 639 void HAL_SYSCFG_DisableVREFBUF(void); 640 641 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 642 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 643 644 /** 645 * @} 646 */ 647 648 /** @addtogroup HAL_Exported_Functions_Group5 649 * @{ 650 */ 651 652 /* SYSCFG Lock functions ********************************************/ 653 void HAL_SYSCFG_Lock(uint32_t Item); 654 HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); 655 656 /** 657 * @} 658 */ 659 660 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 661 662 /** @addtogroup HAL_Exported_Functions_Group6 663 * @{ 664 */ 665 666 /* SYSCFG Attributes functions ********************************************/ 667 void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); 668 HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); 669 670 /** 671 * @} 672 */ 673 674 #endif /* __ARM_FEATURE_CMSE */ 675 676 /** 677 * @} 678 */ 679 680 /** 681 * @} 682 */ 683 684 /** 685 * @} 686 */ 687 688 #ifdef __cplusplus 689 } 690 #endif 691 692 #endif /* __STM32U5xx_HAL_H */ 693
