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Searched refs:uint32_t (Results 1 – 25 of 1349) sorted by relevance

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/trusted-firmware-a-latest/plat/intel/soc/common/include/
Dsocfpga_handoff.h24 uint32_t header_magic;
25 uint32_t header_device;
26 uint32_t _pad_0x08_0x10[2];
29 uint32_t pinmux_sel_magic;
30 uint32_t pinmux_sel_length;
31 uint32_t _pad_0x18_0x20[2];
32 uint32_t pinmux_sel_array[96]; /* offset, value */
35 uint32_t pinmux_io_magic;
36 uint32_t pinmux_io_length;
37 uint32_t _pad_0x1a8_0x1b0[2];
[all …]
Dsocfpga_fcs.h100 uint32_t session_id;
101 uint32_t context_id;
102 uint32_t crypto_header;
103 uint32_t size;
107 uint32_t first_word;
108 uint32_t src_addr;
109 uint32_t src_size;
110 uint32_t dst_addr;
111 uint32_t dst_size;
115 uint32_t first_word;
[all …]
/trusted-firmware-a-latest/drivers/renesas/common/emmc/
Demmc_hal.h122 0U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
123 (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC |
124 (uint32_t) HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
125 (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
128 1U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 |
129 (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
130 (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
131 (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
134 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
135 (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
[all …]
/trusted-firmware-a-latest/include/drivers/st/
Dstm32mp1_ddr.h16 uint32_t mstr;
17 uint32_t mrctrl0;
18 uint32_t mrctrl1;
19 uint32_t derateen;
20 uint32_t derateint;
21 uint32_t pwrctl;
22 uint32_t pwrtmg;
23 uint32_t hwlpctl;
24 uint32_t rfshctl0;
25 uint32_t rfshctl3;
[all …]
Dstm32mp_ddrctrl_regs.h17 uint32_t mstr ; /* 0x0 Master */
18 uint32_t stat; /* 0x4 Operating Mode Status */
20 uint32_t mrctrl0; /* 0x10 Control 0 */
21 uint32_t mrctrl1; /* 0x14 Control 1 */
22 uint32_t mrstat; /* 0x18 Status */
23 uint32_t mrctrl2; /* 0x1c Control 2 */
24 uint32_t derateen; /* 0x20 Temperature Derate Enable */
25 uint32_t derateint; /* 0x24 Temperature Derate Interval */
26 uint32_t reserved028;
27 uint32_t deratectl; /* 0x2c Temperature Derate Control */
[all …]
Dstm32mp1_ddr_regs.h15 uint32_t ridr; /* 0x00 R Revision Identification */
16 uint32_t pir; /* 0x04 R/W PHY Initialization */
17 uint32_t pgcr; /* 0x08 R/W PHY General Configuration */
18 uint32_t pgsr; /* 0x0C PHY General Status */
19 uint32_t dllgcr; /* 0x10 R/W DLL General Control */
20 uint32_t acdllcr; /* 0x14 R/W AC DLL Control */
21 uint32_t ptr0; /* 0x18 R/W PHY Timing 0 */
22 uint32_t ptr1; /* 0x1C R/W PHY Timing 1 */
23 uint32_t ptr2; /* 0x20 R/W PHY Timing 2 */
24 uint32_t aciocr; /* 0x24 AC I/O Configuration */
[all …]
Dbsec.h93 uint32_t bsec_probe(void);
94 uint32_t bsec_get_base(void);
96 uint32_t bsec_set_config(struct bsec_config *cfg);
97 uint32_t bsec_get_config(struct bsec_config *cfg);
99 uint32_t bsec_shadow_register(uint32_t otp);
100 uint32_t bsec_read_otp(uint32_t *val, uint32_t otp);
101 uint32_t bsec_write_otp(uint32_t val, uint32_t otp);
102 uint32_t bsec_program_otp(uint32_t val, uint32_t otp);
103 uint32_t bsec_permanent_lock_otp(uint32_t otp);
105 void bsec_write_debug_conf(uint32_t val);
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8173/drivers/pmic/
Dpmic_wrap_init.h13 int32_t pwrap_read(uint32_t adr, uint32_t *rdata);
14 int32_t pwrap_write(uint32_t adr, uint32_t wdata);
28 uint32_t mux_sel;
29 uint32_t wrap_en;
30 uint32_t dio_en;
31 uint32_t sidly;
32 uint32_t rddmy;
33 uint32_t si_ck_con;
34 uint32_t cshext_write;
35 uint32_t cshext_read;
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8173/include/
Dmcucfg.h14 uint32_t mp0_ca7l_cache_config;
16 uint32_t mem_delsel0;
17 uint32_t mem_delsel1;
19 uint32_t mp0_cache_mem_delsel0;
20 uint32_t mp0_cache_mem_delsel1;
21 uint32_t mp0_axi_config;
22 uint32_t mp0_misc_config[2];
24 uint32_t rv_addr_lw;
25 uint32_t rv_addr_hw;
27 uint32_t mp0_ca7l_cfg_dis;
[all …]
/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t186/drivers/include/
Dmce_private.h89 int32_t (*enter_cstate)(uint32_t ari_base, uint32_t state,
90 uint32_t wake_time);
95 int32_t (*update_cstate_info)(uint32_t ari_base,
96 uint32_t cluster,
97 uint32_t ccplex,
98 uint32_t system,
100 uint32_t wake_mask,
107 int32_t (*update_crossover_time)(uint32_t ari_base,
108 uint32_t type,
109 uint32_t time);
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8183/include/
Dmcucfg.h14 uint32_t mp0_ca7l_cache_config; /* 0x0 */
16 uint32_t mem_delsel0;
17 uint32_t mem_delsel1;
19 uint32_t mp0_cache_mem_delsel0; /* 0x24 */
20 uint32_t mp0_cache_mem_delsel1; /* 0x28 */
21 uint32_t mp0_axi_config; /* 0x2C */
22 uint32_t mp0_misc_config[10]; /* 0x30 */
23 uint32_t mp0_ca7l_cfg_dis; /* 0x58 */
24 uint32_t mp0_ca7l_clken_ctrl; /* 0x5C */
25 uint32_t mp0_ca7l_rst_ctrl; /* 0x60 */
[all …]
/trusted-firmware-a-latest/plat/imx/common/include/
Dimx_snvs.h15 uint32_t hplr;
16 uint32_t hpcomr;
17 uint32_t hpcr;
18 uint32_t hpsicr;
19 uint32_t hpsvcr;
20 uint32_t hpsr;
21 uint32_t hpsvsr;
22 uint32_t hphacivr;
23 uint32_t hphacr;
24 uint32_t hprtcmr;
[all …]
/trusted-firmware-a-latest/plat/xilinx/common/include/
Dpm_api_sys.h25 enum pm_ret_status pm_handle_eemi_call(uint32_t flag, uint32_t x0, uint32_t x1,
26 uint32_t x2, uint32_t x3, uint32_t x4,
27 uint32_t x5, uint64_t *result);
28 enum pm_ret_status pm_self_suspend(uint32_t nid,
29 uint32_t latency,
30 uint32_t state,
31 uintptr_t address, uint32_t flag);
32 enum pm_ret_status pm_abort_suspend(enum pm_abort_reason reason, uint32_t flag);
33 enum pm_ret_status pm_req_suspend(uint32_t target,
35 uint32_t latency,
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/trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/dram/
Ddram_spec_timing.h63 uint32_t mhz;
65 uint32_t tinit1;
66 uint32_t tinit2;
67 uint32_t tinit3;
68 uint32_t tinit4;
69 uint32_t tinit5;
71 uint32_t trstl;
73 uint32_t trsth;
74 uint32_t trefi;
76 uint32_t trcd;
[all …]
/trusted-firmware-a-latest/include/drivers/nxp/auth/csf_hdr_parser/
Dcsf_hdr.h22 uint32_t srk_tbl_off; /* 0x04 SRK Table Offset */
31 uint32_t uid_flag;
33 uint32_t psign; /* 0x10 signature offset */
34 uint32_t sign_len; /* 0x14 length of signature */
38 uint32_t sg_table_offset; /* 0x18 SG Table Offset */
39 uint32_t sg_entries; /* 0x1c no of entries in SG */
46 uint32_t img_size; /* ESBC client img size in bytes */
47 uint32_t ie_key_sel;
52 uint32_t fsl_uid_0; /* 0x28 Freescale unique id 0 */
53 uint32_t fsl_uid_1; /* 0x2c Freescale unique id 1 */
[all …]
/trusted-firmware-a-latest/drivers/renesas/rcar/pfc/D3/
Dpfc_init_d3.c171 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
172 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
173 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
174 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
175 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
176 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
177 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
178 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
237 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
238 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
[all …]
/trusted-firmware-a-latest/plat/xilinx/zynqmp/pm_service/
Dzynqmp_pm_api_sys.h42 pl[0] = (uint32_t)(arg0); \
46 pl[1] = (uint32_t)(arg1); \
51 pl[2] = (uint32_t)(arg2); \
56 pl[3] = (uint32_t)(arg3); \
61 pl[4] = (uint32_t)(arg4); \
66 pl[5] = (uint32_t)(arg5); \
75 uint32_t latency,
76 uint32_t state);
79 uint32_t latency,
80 uint32_t state,
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/trusted-firmware-a-latest/plat/st/stm32mp2/include/
Dboot_api.h224 uint32_t chip_ver;
227 uint32_t cut_ver;
230 uint32_t rom_mask_ver;
233 uint32_t bootrom_ver;
236 uint32_t for_chip_design_rtl_ver;
239 uint32_t platform_type_ver;
253 uint32_t boot_partition_used_toboot;
255 uint32_t reserved1[3];
264 uint32_t sd_err_internal_timeout_cnt;
265 uint32_t sd_err_dcrc_fail_cnt;
[all …]
/trusted-firmware-a-latest/drivers/arm/ethosn/
Dethosn_big_fw.h15 uint32_t fw_magic;
16 uint32_t fw_ver_major;
17 uint32_t fw_ver_minor;
18 uint32_t fw_ver_patch;
19 uint32_t arch_min;
20 uint32_t arch_max;
21 uint32_t offset;
22 uint32_t size;
23 uint32_t code_offset;
24 uint32_t code_size;
[all …]
/trusted-firmware-a-latest/plat/st/stm32mp1/include/
Dboot_api.h220 uint32_t reserved1[12];
223 uint32_t reserved1[13];
225 uint32_t otp_afmux_values[3];
226 uint32_t reserved[3];
228 uint32_t reserved2[2];
230 uint32_t auth_status;
237 uint32_t reserved3;
238 uint32_t (*bootrom_ecdsa_verify_signature)(uint8_t *hash_in,
241 uint32_t ecc_algo);
242 uint32_t reserved4;
[all …]
/trusted-firmware-a-latest/plat/rockchip/rk3368/drivers/ddr/
Dddr_rk3368.c36 uint32_t ddrfreq;
37 uint32_t TOGCNT1U;
38 uint32_t TINIT;
39 uint32_t TRSTH;
40 uint32_t TOGCNT100N;
41 uint32_t TREFI;
42 uint32_t TMRD;
43 uint32_t TRFC;
44 uint32_t TRP;
45 uint32_t TRTW;
[all …]
/trusted-firmware-a-latest/plat/ti/k3/common/drivers/ti_sci/
Dti_sci.h52 int ti_sci_device_get(uint32_t id);
53 int ti_sci_device_get_exclusive(uint32_t id);
54 int ti_sci_device_idle(uint32_t id);
55 int ti_sci_device_idle_exclusive(uint32_t id);
56 int ti_sci_device_put(uint32_t id);
57 int ti_sci_device_put_no_wait(uint32_t id);
58 int ti_sci_device_is_valid(uint32_t id);
59 int ti_sci_device_get_clcnt(uint32_t id, uint32_t *count);
60 int ti_sci_device_is_idle(uint32_t id, bool *r_state);
61 int ti_sci_device_is_stop(uint32_t id, bool *r_state, bool *curr_state);
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/spmc/
Dmtspmc.h14 void spm_poweron_cpu(uint32_t cluster, uint32_t cpu);
15 void spm_poweroff_cpu(uint32_t cluster, uint32_t cpu);
17 void spm_poweroff_cluster(uint32_t cluster);
18 void spm_poweron_cluster(uint32_t cluster);
20 bool spm_get_cpu_powerstate(uint32_t cluster, uint32_t cpu);
21 bool spm_get_cluster_powerstate(uint32_t cluster);
22 bool spm_get_powerstate(uint32_t mask);
24 void mcucfg_init_archstate(uint32_t cluster, uint32_t cpu, bool arm64);
25 void mcucfg_set_bootaddr(uint32_t cluster, uint32_t cpu, uintptr_t bootaddr);
26 uintptr_t mcucfg_get_bootaddr(uint32_t cluster, uint32_t cpu);
[all …]
/trusted-firmware-a-latest/drivers/renesas/rcar/pfc/H3/
Dpfc_init_h3_v2.c168 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
169 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
170 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
171 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
172 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
173 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
174 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
175 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
234 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
235 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
[all …]
/trusted-firmware-a-latest/drivers/renesas/rcar/pfc/M3N/
Dpfc_init_m3n.c170 #define IPSR_28_FUNC(x) ((uint32_t)(x) << 28U)
171 #define IPSR_24_FUNC(x) ((uint32_t)(x) << 24U)
172 #define IPSR_20_FUNC(x) ((uint32_t)(x) << 20U)
173 #define IPSR_16_FUNC(x) ((uint32_t)(x) << 16U)
174 #define IPSR_12_FUNC(x) ((uint32_t)(x) << 12U)
175 #define IPSR_8_FUNC(x) ((uint32_t)(x) << 8U)
176 #define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
177 #define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
236 #define DRVCTRL0_QSPI0_SPCLK(x) ((uint32_t)(x) << 28U)
237 #define DRVCTRL0_QSPI0_MOSI_IO0(x) ((uint32_t)(x) << 24U)
[all …]

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