Lines Matching refs:uint32_t
15 uint32_t ridr; /* 0x00 R Revision Identification */
16 uint32_t pir; /* 0x04 R/W PHY Initialization */
17 uint32_t pgcr; /* 0x08 R/W PHY General Configuration */
18 uint32_t pgsr; /* 0x0C PHY General Status */
19 uint32_t dllgcr; /* 0x10 R/W DLL General Control */
20 uint32_t acdllcr; /* 0x14 R/W AC DLL Control */
21 uint32_t ptr0; /* 0x18 R/W PHY Timing 0 */
22 uint32_t ptr1; /* 0x1C R/W PHY Timing 1 */
23 uint32_t ptr2; /* 0x20 R/W PHY Timing 2 */
24 uint32_t aciocr; /* 0x24 AC I/O Configuration */
25 uint32_t dxccr; /* 0x28 DATX8 Common Configuration */
26 uint32_t dsgcr; /* 0x2C DDR System General Configuration */
27 uint32_t dcr; /* 0x30 DRAM Configuration */
28 uint32_t dtpr0; /* 0x34 DRAM Timing Parameters0 */
29 uint32_t dtpr1; /* 0x38 DRAM Timing Parameters1 */
30 uint32_t dtpr2; /* 0x3C DRAM Timing Parameters2 */
31 uint32_t mr0; /* 0x40 Mode 0 */
32 uint32_t mr1; /* 0x44 Mode 1 */
33 uint32_t mr2; /* 0x48 Mode 2 */
34 uint32_t mr3; /* 0x4C Mode 3 */
35 uint32_t odtcr; /* 0x50 ODT Configuration */
36 uint32_t dtar; /* 0x54 data training address */
37 uint32_t dtdr0; /* 0x58 */
38 uint32_t dtdr1; /* 0x5c */
40 uint32_t dcuar; /* 0xc0 Address */
41 uint32_t dcudr; /* 0xc4 DCU Data */
42 uint32_t dcurr; /* 0xc8 DCU Run */
43 uint32_t dculr; /* 0xcc DCU Loop */
44 uint32_t dcugcr; /* 0xd0 DCU General Configuration */
45 uint32_t dcutpr; /* 0xd4 DCU Timing Parameters */
46 uint32_t dcusr0; /* 0xd8 DCU Status 0 */
47 uint32_t dcusr1; /* 0xdc DCU Status 1 */
49 uint32_t bistrr; /* 0x100 BIST Run */
50 uint32_t bistmskr0; /* 0x104 BIST Mask 0 */
51 uint32_t bistmskr1; /* 0x108 BIST Mask 0 */
52 uint32_t bistwcr; /* 0x10c BIST Word Count */
53 uint32_t bistlsr; /* 0x110 BIST LFSR Seed */
54 uint32_t bistar0; /* 0x114 BIST Address 0 */
55 uint32_t bistar1; /* 0x118 BIST Address 1 */
56 uint32_t bistar2; /* 0x11c BIST Address 2 */
57 uint32_t bistupdr; /* 0x120 BIST User Data Pattern */
58 uint32_t bistgsr; /* 0x124 BIST General Status */
59 uint32_t bistwer; /* 0x128 BIST Word Error */
60 uint32_t bistber0; /* 0x12c BIST Bit Error 0 */
61 uint32_t bistber1; /* 0x130 BIST Bit Error 1 */
62 uint32_t bistber2; /* 0x134 BIST Bit Error 2 */
63 uint32_t bistwcsr; /* 0x138 BIST Word Count Status */
64 uint32_t bistfwr0; /* 0x13c BIST Fail Word 0 */
65 uint32_t bistfwr1; /* 0x140 BIST Fail Word 1 */
67 uint32_t gpr0; /* 0x178 General Purpose 0 (GPR0) */
68 uint32_t gpr1; /* 0x17C General Purpose 1 (GPR1) */
69 uint32_t zq0cr0; /* 0x180 zq 0 control 0 */
70 uint32_t zq0cr1; /* 0x184 zq 0 control 1 */
71 uint32_t zq0sr0; /* 0x188 zq 0 status 0 */
72 uint32_t zq0sr1; /* 0x18C zq 0 status 1 */
74 uint32_t dx0gcr; /* 0x1c0 Byte lane 0 General Configuration */
75 uint32_t dx0gsr0; /* 0x1c4 Byte lane 0 General Status 0 */
76 uint32_t dx0gsr1; /* 0x1c8 Byte lane 0 General Status 1 */
77 uint32_t dx0dllcr; /* 0x1cc Byte lane 0 DLL Control */
78 uint32_t dx0dqtr; /* 0x1d0 Byte lane 0 DQ Timing */
79 uint32_t dx0dqstr; /* 0x1d4 Byte lane 0 DQS Timing */
81 uint32_t dx1gcr; /* 0x200 Byte lane 1 General Configuration */
82 uint32_t dx1gsr0; /* 0x204 Byte lane 1 General Status 0 */
83 uint32_t dx1gsr1; /* 0x208 Byte lane 1 General Status 1 */
84 uint32_t dx1dllcr; /* 0x20c Byte lane 1 DLL Control */
85 uint32_t dx1dqtr; /* 0x210 Byte lane 1 DQ Timing */
86 uint32_t dx1dqstr; /* 0x214 Byte lane 1 QS Timing */
89 uint32_t dx2gcr; /* 0x240 Byte lane 2 General Configuration */
90 uint32_t dx2gsr0; /* 0x244 Byte lane 2 General Status 0 */
91 uint32_t dx2gsr1; /* 0x248 Byte lane 2 General Status 1 */
92 uint32_t dx2dllcr; /* 0x24c Byte lane 2 DLL Control */
93 uint32_t dx2dqtr; /* 0x250 Byte lane 2 DQ Timing */
94 uint32_t dx2dqstr; /* 0x254 Byte lane 2 QS Timing */
96 uint32_t dx3gcr; /* 0x280 Byte lane 3 General Configuration */
97 uint32_t dx3gsr0; /* 0x284 Byte lane 3 General Status 0 */
98 uint32_t dx3gsr1; /* 0x288 Byte lane 3 General Status 1 */
99 uint32_t dx3dllcr; /* 0x28c Byte lane 3 DLL Control */
100 uint32_t dx3dqtr; /* 0x290 Byte lane 3 DQ Timing */
101 uint32_t dx3dqstr; /* 0x294 Byte lane 3 QS Timing */