Lines Matching refs:uint32_t
17 uint32_t mstr ; /* 0x0 Master */
18 uint32_t stat; /* 0x4 Operating Mode Status */
20 uint32_t mrctrl0; /* 0x10 Control 0 */
21 uint32_t mrctrl1; /* 0x14 Control 1 */
22 uint32_t mrstat; /* 0x18 Status */
23 uint32_t mrctrl2; /* 0x1c Control 2 */
24 uint32_t derateen; /* 0x20 Temperature Derate Enable */
25 uint32_t derateint; /* 0x24 Temperature Derate Interval */
26 uint32_t reserved028;
27 uint32_t deratectl; /* 0x2c Temperature Derate Control */
28 uint32_t pwrctl; /* 0x30 Low Power Control */
29 uint32_t pwrtmg; /* 0x34 Low Power Timing */
30 uint32_t hwlpctl; /* 0x38 Hardware Low Power Control */
32 uint32_t rfshctl0; /* 0x50 Refresh Control 0 */
33 uint32_t rfshctl1; /* 0x54 Refresh Control 1 */
34 uint32_t reserved058; /* 0x58 Refresh Control 2 */
35 uint32_t reserved05C;
36 uint32_t rfshctl3; /* 0x60 Refresh Control 0 */
37 uint32_t rfshtmg; /* 0x64 Refresh Timing */
38 uint32_t rfshtmg1; /* 0x68 Refresh Timing 1 */
40 uint32_t crcparctl0; /* 0xc0 CRC Parity Control0 */
41 uint32_t crcparctl1; /* 0xc4 CRC Parity Control1 */
42 uint32_t reserved0c8; /* 0xc8 CRC Parity Control2 */
43 uint32_t crcparstat; /* 0xcc CRC Parity Status */
44 uint32_t init0; /* 0xd0 SDRAM Initialization 0 */
45 uint32_t init1; /* 0xd4 SDRAM Initialization 1 */
46 uint32_t init2; /* 0xd8 SDRAM Initialization 2 */
47 uint32_t init3; /* 0xdc SDRAM Initialization 3 */
48 uint32_t init4; /* 0xe0 SDRAM Initialization 4 */
49 uint32_t init5; /* 0xe4 SDRAM Initialization 5 */
50 uint32_t init6; /* 0xe8 SDRAM Initialization 6 */
51 uint32_t init7; /* 0xec SDRAM Initialization 7 */
52 uint32_t dimmctl; /* 0xf0 DIMM Control */
53 uint32_t rankctl; /* 0xf4 Rank Control */
55 uint32_t dramtmg0; /* 0x100 SDRAM Timing 0 */
56 uint32_t dramtmg1; /* 0x104 SDRAM Timing 1 */
57 uint32_t dramtmg2; /* 0x108 SDRAM Timing 2 */
58 uint32_t dramtmg3; /* 0x10c SDRAM Timing 3 */
59 uint32_t dramtmg4; /* 0x110 SDRAM Timing 4 */
60 uint32_t dramtmg5; /* 0x114 SDRAM Timing 5 */
61 uint32_t dramtmg6; /* 0x118 SDRAM Timing 6 */
62 uint32_t dramtmg7; /* 0x11c SDRAM Timing 7 */
63 uint32_t dramtmg8; /* 0x120 SDRAM Timing 8 */
64 uint32_t dramtmg9; /* 0x124 SDRAM Timing 9 */
65 uint32_t dramtmg10; /* 0x128 SDRAM Timing 10 */
66 uint32_t dramtmg11; /* 0x12c SDRAM Timing 11 */
67 uint32_t dramtmg12; /* 0x130 SDRAM Timing 12 */
68 uint32_t dramtmg13; /* 0x134 SDRAM Timing 13 */
69 uint32_t dramtmg14; /* 0x138 SDRAM Timing 14 */
70 uint32_t dramtmg15; /* 0x13c SDRAM Timing 15 */
72 uint32_t zqctl0; /* 0x180 ZQ Control 0 */
73 uint32_t zqctl1; /* 0x184 ZQ Control 1 */
74 uint32_t zqctl2; /* 0x188 ZQ Control 2 */
75 uint32_t zqstat; /* 0x18c ZQ Status */
76 uint32_t dfitmg0; /* 0x190 DFI Timing 0 */
77 uint32_t dfitmg1; /* 0x194 DFI Timing 1 */
78 uint32_t dfilpcfg0; /* 0x198 DFI Low Power Configuration 0 */
79 uint32_t dfilpcfg1; /* 0x19c DFI Low Power Configuration 1 */
80 uint32_t dfiupd0; /* 0x1a0 DFI Update 0 */
81 uint32_t dfiupd1; /* 0x1a4 DFI Update 1 */
82 uint32_t dfiupd2; /* 0x1a8 DFI Update 2 */
83 uint32_t reserved1ac;
84 uint32_t dfimisc; /* 0x1b0 DFI Miscellaneous Control */
85 uint32_t dfitmg2; /* 0x1b4 DFI Timing 2 */
86 uint32_t dfitmg3; /* 0x1b8 DFI Timing 3 */
87 uint32_t dfistat; /* 0x1bc DFI Status */
88 uint32_t dbictl; /* 0x1c0 DM/DBI Control */
89 uint32_t dfiphymstr; /* 0x1c4 DFI PHY Master interface */
91 uint32_t addrmap0; /* 0x200 Address Map 0 */
92 uint32_t addrmap1; /* 0x204 Address Map 1 */
93 uint32_t addrmap2; /* 0x208 Address Map 2 */
94 uint32_t addrmap3; /* 0x20c Address Map 3 */
95 uint32_t addrmap4; /* 0x210 Address Map 4 */
96 uint32_t addrmap5; /* 0x214 Address Map 5 */
97 uint32_t addrmap6; /* 0x218 Address Map 6 */
98 uint32_t addrmap7; /* 0x21c Address Map 7 */
99 uint32_t addrmap8; /* 0x220 Address Map 8 */
100 uint32_t addrmap9; /* 0x224 Address Map 9 */
101 uint32_t addrmap10; /* 0x228 Address Map 10 */
102 uint32_t addrmap11; /* 0x22C Address Map 11 */
104 uint32_t odtcfg; /* 0x240 ODT Configuration */
105 uint32_t odtmap; /* 0x244 ODT/Rank Map */
107 uint32_t sched; /* 0x250 Scheduler Control */
108 uint32_t sched1; /* 0x254 Scheduler Control 1 */
109 uint32_t reserved258;
110 uint32_t perfhpr1; /* 0x25c High Priority Read CAM 1 */
111 uint32_t reserved260;
112 uint32_t perflpr1; /* 0x264 Low Priority Read CAM 1 */
113 uint32_t reserved268;
114 uint32_t perfwr1; /* 0x26c Write CAM 1 */
116 uint32_t dbg0; /* 0x300 Debug 0 */
117 uint32_t dbg1; /* 0x304 Debug 1 */
118 uint32_t dbgcam; /* 0x308 CAM Debug */
119 uint32_t dbgcmd; /* 0x30c Command Debug */
120 uint32_t dbgstat; /* 0x310 Status Debug */
122 uint32_t swctl; /* 0x320 Software Programming Control Enable */
123 uint32_t swstat; /* 0x324 Software Programming Control Status */
125 uint32_t poisoncfg; /* 0x36c AXI Poison Configuration Register */
126 uint32_t poisonstat; /* 0x370 AXI Poison Status Register */
128 uint32_t deratestat; /* 0x3f0 Temperature Derate Status */
132 uint32_t pstat; /* 0x3fc Port Status */
133 uint32_t pccfg; /* 0x400 Port Common Configuration */
136 uint32_t pcfgr_0; /* 0x404 Configuration Read */
137 uint32_t pcfgw_0; /* 0x408 Configuration Write */
139 uint32_t pctrl_0; /* 0x490 Port Control Register */
140 uint32_t pcfgqos0_0; /* 0x494 Read QoS Configuration 0 */
141 uint32_t pcfgqos1_0; /* 0x498 Read QoS Configuration 1 */
142 uint32_t pcfgwqos0_0; /* 0x49c Write QoS Configuration 0 */
143 uint32_t pcfgwqos1_0; /* 0x4a0 Write QoS Configuration 1 */
148 uint32_t pcfgr_1; /* 0x4b4 Configuration Read */
149 uint32_t pcfgw_1; /* 0x4b8 Configuration Write */
151 uint32_t pctrl_1; /* 0x540 Port 2 Control Register */
152 uint32_t pcfgqos0_1; /* 0x544 Read QoS Configuration 0 */
153 uint32_t pcfgqos1_1; /* 0x548 Read QoS Configuration 1 */
154 uint32_t pcfgwqos0_1; /* 0x54c Write QoS Configuration 0 */
155 uint32_t pcfgwqos1_1; /* 0x550 Write QoS Configuration 1 */
159 uint32_t umctl2_ver_number; /* 0xff0 UMCTL2 Version Number */