| /trusted-firmware-a-latest/plat/rockchip/rk3399/drivers/dram/ |
| D | dram_spec_timing.c | 209 uint32_t tmp; in ddr3_get_parameter() local
216 tmp = 0; in ddr3_get_parameter()
218 tmp = 1; in ddr3_get_parameter()
220 tmp = 2; in ddr3_get_parameter()
222 tmp = 3; in ddr3_get_parameter()
224 tmp = 4; in ddr3_get_parameter()
226 tmp = 5; in ddr3_get_parameter()
228 tmp = 6; in ddr3_get_parameter()
235 pdram_timing->cl = (ddr3_cl_cwl[ddr_speed_bin][tmp] >> 4) & 0xf; in ddr3_get_parameter()
236 pdram_timing->cwl = ddr3_cl_cwl[ddr_speed_bin][tmp] & 0xf; in ddr3_get_parameter()
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| D | dfs.c | 106 uint32_t tmp; in get_dram_drv_odt_val() local
112 tmp = ((mr1_val >> 1) & 1) | ((mr1_val >> 4) & 1); in get_dram_drv_odt_val()
113 if (tmp) in get_dram_drv_odt_val()
117 tmp = ((mr1_val >> 2) & 1) | ((mr1_val >> 5) & 1) | in get_dram_drv_odt_val()
119 if (tmp == 0) in get_dram_drv_odt_val()
121 else if (tmp == 1) in get_dram_drv_odt_val()
123 else if (tmp == 3) in get_dram_drv_odt_val()
165 tmp = mr11_val & 0x7; in get_dram_drv_odt_val()
166 if ((tmp == 7) || (tmp == 0)) in get_dram_drv_odt_val()
169 drv_config->dram_side_dq_odt = 240 / tmp; in get_dram_drv_odt_val()
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| D | suspend.c | 191 uint32_t i, tmp; in data_training() local
233 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; in data_training()
246 if ((((tmp >> 11) & 0x1) == 0x1) && in data_training()
247 (((tmp >> 13) & 0x1) == 0x1) && in data_training()
248 (((tmp >> 5) & 0x1) == 0x0) && in data_training()
251 else if ((((tmp >> 5) & 0x1) == 0x1) || in data_training()
274 tmp = mmio_read_32(PI_REG(ch, 174)) >> 8; in data_training()
290 if ((((tmp >> 10) & 0x1) == 0x1) && in data_training()
291 (((tmp >> 13) & 0x1) == 0x1) && in data_training()
292 (((tmp >> 4) & 0x1) == 0x0) && in data_training()
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| /trusted-firmware-a-latest/plat/rockchip/px30/drivers/soc/ |
| D | soc.c | 88 uint32_t tmp; in soc_reset_config_all() local
91 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in soc_reset_config_all()
92 tmp |= CRU_GLB_RST_TSADC_FST | CRU_GLB_RST_WDT_FST; in soc_reset_config_all()
93 mmio_write_32(CRU_BASE + CRU_GLB_RST_CON, tmp); in soc_reset_config_all()
95 tmp = mmio_read_32(PMUGRF_BASE + PMUGRF_SOC_CON(3)); in soc_reset_config_all()
96 tmp &= ~(PMUGRF_FAILSAFE_SHTDN_TSADC | PMUGRF_FAILSAFE_SHTDN_WDT); in soc_reset_config_all()
97 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON(3), tmp); in soc_reset_config_all()
106 uint32_t tmp; in px30_soc_reset_config() local
109 tmp = mmio_read_32(CRU_BASE + CRU_GLB_RST_CON); in px30_soc_reset_config()
110 tmp |= BIT(CRU_GLB_RST_TSADC_EXT) | BIT(CRU_GLB_RST_WDT_EXT); in px30_soc_reset_config()
[all …]
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| /trusted-firmware-a-latest/plat/arm/board/juno/ |
| D | juno_trusted_boot.c | 28 uint32_t *src, tmp; in juno_get_rotpk_info_regs() local
69 tmp = src[words - 1 - i]; in juno_get_rotpk_info_regs()
71 *dst++ = (uint8_t)((tmp >> 24) & 0xFF); in juno_get_rotpk_info_regs()
72 *dst++ = (uint8_t)((tmp >> 16) & 0xFF); in juno_get_rotpk_info_regs()
73 *dst++ = (uint8_t)((tmp >> 8) & 0xFF); in juno_get_rotpk_info_regs()
74 *dst++ = (uint8_t)(tmp & 0xFF); in juno_get_rotpk_info_regs()
80 tmp = src[words - 1 - i]; in juno_get_rotpk_info_regs()
81 *dst++ = (uint8_t)((tmp >> 24) & 0xFF); in juno_get_rotpk_info_regs()
82 *dst++ = (uint8_t)((tmp >> 16) & 0xFF); in juno_get_rotpk_info_regs()
83 *dst++ = (uint8_t)((tmp >> 8) & 0xFF); in juno_get_rotpk_info_regs()
[all …]
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| /trusted-firmware-a-latest/lib/zlib/ |
| D | adler32.c | 27 unsigned long tmp = a >> 16; \
29 a += (tmp << 4) - tmp; \
43 z_off64_t tmp = a >> 32; \
45 a += (tmp << 8) - (tmp << 5) + tmp; \
46 tmp = a >> 16; \
48 a += (tmp << 4) - tmp; \
49 tmp = a >> 16; \
51 a += (tmp << 4) - tmp; \
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| /trusted-firmware-a-latest/include/arch/aarch64/ |
| D | asm_macros.S | 76 .macro dcache_line_size reg, tmp
77 mrs \tmp, ctr_el0
78 ubfx \tmp, \tmp, #16, #4
80 lsl \reg, \reg, \tmp
84 .macro icache_line_size reg, tmp
85 mrs \tmp, ctr_el0
86 and \tmp, \tmp, #0xf
88 lsl \reg, \reg, \tmp
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| /trusted-firmware-a-latest/include/lib/libfdt/ |
| D | libfdt.h | 1327 fdt32_t tmp = cpu_to_fdt32(val); in fdt_setprop_inplace_u32() local
1328 return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); in fdt_setprop_inplace_u32()
1362 fdt64_t tmp = cpu_to_fdt64(val); in fdt_setprop_inplace_u64() local
1363 return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp)); in fdt_setprop_inplace_u64()
1482 fdt32_t tmp = cpu_to_fdt32(val); in fdt_property_u32() local
1483 return fdt_property(fdt, name, &tmp, sizeof(tmp)); in fdt_property_u32()
1487 fdt64_t tmp = cpu_to_fdt64(val); in fdt_property_u64() local
1488 return fdt_property(fdt, name, &tmp, sizeof(tmp)); in fdt_property_u64()
1694 fdt32_t tmp = cpu_to_fdt32(val); in fdt_setprop_u32() local
1695 return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp)); in fdt_setprop_u32()
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| /trusted-firmware-a-latest/plat/imx/imx8qx/ |
| D | imx8qx_bl31_setup.c | 116 unsigned int diff1, diff2, tmp, rate; in lpuart32_serial_setbrg() local
148 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD); in lpuart32_serial_setbrg()
151 tmp |= LPUART_BAUD_BOTHEDGE_MASK; in lpuart32_serial_setbrg()
153 tmp &= ~LPUART_BAUD_OSR_MASK; in lpuart32_serial_setbrg()
154 tmp |= LPUART_BAUD_OSR(osr - 1); in lpuart32_serial_setbrg()
155 tmp &= ~LPUART_BAUD_SBR_MASK; in lpuart32_serial_setbrg()
156 tmp |= LPUART_BAUD_SBR(sbr); in lpuart32_serial_setbrg()
159 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); in lpuart32_serial_setbrg()
161 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp); in lpuart32_serial_setbrg()
166 unsigned int tmp; in lpuart32_serial_init() local
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| /trusted-firmware-a-latest/plat/brcm/board/stingray/driver/ext_sram_init/ |
| D | ext_sram_init.c | 181 unsigned int val, tmp; in brcm_stingray_pnor_sram_init() local
215 tmp = 0x0; in brcm_stingray_pnor_sram_init()
217 tmp |= (val & PNOR_REG_PERIPH_IDx_MASK); in brcm_stingray_pnor_sram_init()
219 tmp |= ((val & PNOR_REG_PERIPH_IDx_MASK) << 8); in brcm_stingray_pnor_sram_init()
221 tmp |= ((val & PNOR_REG_PERIPH_IDx_MASK) << 16); in brcm_stingray_pnor_sram_init()
223 tmp |= ((val & PNOR_REG_PERIPH_IDx_MASK) << 24); in brcm_stingray_pnor_sram_init()
224 INFO(" -- pnor primecell_id = 0x%x\n", tmp); in brcm_stingray_pnor_sram_init()
270 tmp = 0; in brcm_stingray_pnor_sram_init()
278 tmp++; in brcm_stingray_pnor_sram_init()
281 tmp, (NOR_SIZE / SRAM_CHECKS_GRANUL)); in brcm_stingray_pnor_sram_init()
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| /trusted-firmware-a-latest/include/arch/aarch32/ |
| D | asm_macros.S | 48 .macro dcache_line_size reg, tmp
49 ldcopr \tmp, CTR
50 ubfx \tmp, \tmp, #CTR_DMINLINE_SHIFT, #CTR_DMINLINE_WIDTH
52 lsl \reg, \reg, \tmp
55 .macro icache_line_size reg, tmp
56 ldcopr \tmp, CTR
57 and \tmp, \tmp, #CTR_IMINLINE_MASK
59 lsl \reg, \reg, \tmp
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| /trusted-firmware-a-latest/drivers/renesas/common/ddr/ddr_b/ |
| D | boot_init_dram.c | 685 uint32_t tmp; in ddr_setval_s() local
697 tmp = reg_ddrphy_read(ch, adr); in ddr_setval_s()
698 tmp = (tmp & (~msk)) | ((val << lsb) & msk); in ddr_setval_s()
699 reg_ddrphy_write(ch, adr, tmp); in ddr_setval_s()
708 uint32_t tmp; in ddr_getval_s() local
720 tmp = reg_ddrphy_read(ch, adr); in ddr_getval_s()
721 tmp = (tmp >> lsb) & msk; in ddr_getval_s()
723 return tmp; in ddr_getval_s()
794 uint32_t tmp; in ddrtbl_setval() local
813 tmp = tbl[adr & adrmsk]; in ddrtbl_setval()
[all …]
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| /trusted-firmware-a-latest/plat/st/common/ |
| D | stm32mp_trusted_boot.c | 50 uint32_t tmp; in copy_hash_from_otp() local
59 tmp = bswap32(otp_val); in copy_hash_from_otp()
60 memcpy(hash + i * sizeof(uint32_t), &tmp, sizeof(tmp)); in copy_hash_from_otp()
63 first = tmp; in copy_hash_from_otp()
71 if ((tmp != 0U) && (tmp != 0xFFFFFFFFU) && (tmp != first)) { in copy_hash_from_otp()
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| /trusted-firmware-a-latest/plat/imx/imx8qm/ |
| D | imx8qm_bl31_setup.c | 95 unsigned int diff1, diff2, tmp, rate; in lpuart32_serial_setbrg() local
127 tmp = mmio_read_32(IMX_BOOT_UART_BASE + BAUD); in lpuart32_serial_setbrg()
130 tmp |= LPUART_BAUD_BOTHEDGE_MASK; in lpuart32_serial_setbrg()
132 tmp &= ~LPUART_BAUD_OSR_MASK; in lpuart32_serial_setbrg()
133 tmp |= LPUART_BAUD_OSR(osr - 1); in lpuart32_serial_setbrg()
134 tmp &= ~LPUART_BAUD_SBR_MASK; in lpuart32_serial_setbrg()
135 tmp |= LPUART_BAUD_SBR(sbr); in lpuart32_serial_setbrg()
138 tmp &= ~(LPUART_BAUD_M10_MASK | LPUART_BAUD_SBNS_MASK); in lpuart32_serial_setbrg()
140 mmio_write_32(IMX_BOOT_UART_BASE + BAUD, tmp); in lpuart32_serial_setbrg()
145 unsigned int tmp; in lpuart32_serial_init() local
[all …]
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| /trusted-firmware-a-latest/lib/aarch32/ |
| D | misc_helpers.S | 59 tmp .req r12 /* Temporary scratch register */
79 orr tmp, cursor, #(8-1)
80 adds tmp, tmp, #1
84 cmp tmp, stop_address
90 cmp cursor, tmp
97 bic tmp, stop_address, #(8-1)
99 cmp cursor, tmp
105 cmp cursor, tmp
128 .unreq tmp
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| /trusted-firmware-a-latest/drivers/nxp/ddr/nxp-ddr/ |
| D | ddrc.c | 201 unsigned int tmp; in ddrc_set_regs() local
363 tmp = ddr_in32(&ddr->debug[28]); in ddrc_set_regs()
364 tmp &= U(0xff0fff00); in ddrc_set_regs()
365 tmp |= ddr_freq <= 1333U ? U(0x0080006a) : in ddrc_set_regs()
369 tmp &= ~0xff; in ddrc_set_regs()
370 tmp |= regs->debug[28] & 0xff; in ddrc_set_regs()
374 ddr_out32(&ddr->debug[28], tmp); in ddrc_set_regs()
380 tmp = ddr_in32(&ddr->debug[28]); in ddrc_set_regs()
381 ddr_out32(&ddr->debug[28], tmp | 0x000a0000); in ddrc_set_regs()
550 tmp = (regs->sdram_cfg[0] >> 19) & 0x3; in ddrc_set_regs()
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| /trusted-firmware-a-latest/plat/imx/imx8m/ddr/ |
| D | dram.c | 67 unsigned int tmp, drate_byte; in lpddr4_mr_read() local
69 tmp = mmio_read_32(DRC_PERF_MON_MRR0_DAT(0)); in lpddr4_mr_read()
70 mmio_write_32(DRC_PERF_MON_MRR0_DAT(0), tmp | 0x1); in lpddr4_mr_read()
72 tmp = mmio_read_32(DDRC_MRSTAT(0)); in lpddr4_mr_read()
73 } while (tmp & 0x1); in lpddr4_mr_read()
81 tmp = mmio_read_32(DDRC_MRSTAT(0)); in lpddr4_mr_read()
82 } while (tmp & 0x1); in lpddr4_mr_read()
85 tmp = mmio_read_32(DRC_PERF_MON_MRR0_DAT(0)); in lpddr4_mr_read()
86 } while (!(tmp & 0x8)); in lpddr4_mr_read()
87 tmp = mmio_read_32(DRC_PERF_MON_MRR1_DAT(0)); in lpddr4_mr_read()
[all …]
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| /trusted-firmware-a-latest/plat/qemu/common/ |
| D | qemu_spm.c | 65 spm_mm_mp_info_t *tmp = mp_info; in qemu_initialize_mp_info() local
69 tmp->mpidr = (0x80000000 | (i << MPIDR_AFF1_SHIFT)) + j; in qemu_initialize_mp_info()
74 tmp->linear_id = 0; in qemu_initialize_mp_info()
75 tmp->flags = 0; in qemu_initialize_mp_info()
76 tmp++; in qemu_initialize_mp_info()
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| /trusted-firmware-a-latest/plat/arm/common/ |
| D | arm_nor_psci_mem_protect.c | 40 int tmp; in arm_psci_read_mem_protect() local
42 tmp = *(int *) PLAT_ARM_MEM_PROT_ADDR; in arm_psci_read_mem_protect()
43 *enabled = (tmp == 1) ? 1 : 0; in arm_psci_read_mem_protect()
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| /trusted-firmware-a-latest/plat/arm/board/common/ |
| D | board_arm_trusted_boot.c | 62 uint32_t *src, tmp; in arm_get_rotpk_info_regs() local
78 tmp = src[words - 1 - i]; in arm_get_rotpk_info_regs()
80 *dst++ = (uint8_t)(tmp & 0xFF); in arm_get_rotpk_info_regs()
81 *dst++ = (uint8_t)((tmp >> 8) & 0xFF); in arm_get_rotpk_info_regs()
82 *dst++ = (uint8_t)((tmp >> 16) & 0xFF); in arm_get_rotpk_info_regs()
83 *dst++ = (uint8_t)((tmp >> 24) & 0xFF); in arm_get_rotpk_info_regs()
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| /trusted-firmware-a-latest/plat/socionext/uniphier/ |
| D | uniphier_scp.c | 33 uint32_t tmp; in uniphier_scp_start() local
39 tmp = mmio_read_32(UNIPHIER_ROM_RSV3); in uniphier_scp_start()
40 } while (!(tmp & BIT(8))); in uniphier_scp_start()
42 mmio_write_32(UNIPHIER_ROM_RSV3, tmp | BIT(9)); in uniphier_scp_start()
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| D | uniphier_emmc.c | 195 uint8_t tmp; in uniphier_emmc_load_image() local
203 tmp = mmio_read_8(host_base + SDHCI_HOST_CONTROL); in uniphier_emmc_load_image()
204 tmp &= ~SDHCI_CTRL_DMA_MASK; in uniphier_emmc_load_image()
205 tmp |= SDHCI_CTRL_SDMA; in uniphier_emmc_load_image()
206 mmio_write_8(host_base + SDHCI_HOST_CONTROL, tmp); in uniphier_emmc_load_image()
208 tmp = mmio_read_8(host_base + SDHCI_BLOCK_GAP_CONTROL); in uniphier_emmc_load_image()
209 tmp &= ~1; /* clear Stop At Block Gap Request */ in uniphier_emmc_load_image()
210 mmio_write_8(host_base + SDHCI_BLOCK_GAP_CONTROL, tmp); in uniphier_emmc_load_image()
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| /trusted-firmware-a-latest/plat/brcm/board/common/ |
| D | board_arm_trusted_boot.c | 145 uint32_t *src, tmp; in plat_get_rotpk_info() local
177 tmp = src[words - 1 - i]; in plat_get_rotpk_info()
179 *dst++ = (uint8_t)((tmp >> 24) & 0xFF); in plat_get_rotpk_info()
180 *dst++ = (uint8_t)((tmp >> 16) & 0xFF); in plat_get_rotpk_info()
181 *dst++ = (uint8_t)((tmp >> 8) & 0xFF); in plat_get_rotpk_info()
182 *dst++ = (uint8_t)(tmp & 0xFF); in plat_get_rotpk_info()
188 tmp = src[words - 1 - i]; in plat_get_rotpk_info()
189 *dst++ = (uint8_t)((tmp >> 24) & 0xFF); in plat_get_rotpk_info()
190 *dst++ = (uint8_t)((tmp >> 16) & 0xFF); in plat_get_rotpk_info()
191 *dst++ = (uint8_t)((tmp >> 8) & 0xFF); in plat_get_rotpk_info()
[all …]
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| /trusted-firmware-a-latest/drivers/nxp/crypto/caam/src/ |
| D | caam.c | 71 uint32_t tmp = sec_in32((g_nxp_caam_addr + SEC_REG_JRSTARTR_OFFSET)); in start_jr() local
89 tmp |= JRSTARTR_STARTJR0; in start_jr()
92 tmp |= JRSTARTR_STARTJR1; in start_jr()
95 tmp |= JRSTARTR_STARTJR2; in start_jr()
98 tmp |= JRSTARTR_STARTJR3; in start_jr()
104 sec_out32((g_nxp_caam_addr + SEC_REG_JRSTARTR_OFFSET), tmp); in start_jr()
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| /trusted-firmware-a-latest/drivers/nxp/ddr/fsl-mmdc/ |
| D | fsl_mmdc.c | 43 unsigned int tmp; in mmdc_init() local
65 tmp = priv->mdctl & ~(MDCTL_SDE0 | MDCTL_SDE1); in mmdc_init()
66 ddr_out32(&mmdc->mdctl, tmp); in mmdc_init()
74 ddr_out32(&mmdc->mdctl, tmp | MDCTL_SDE0); in mmdc_init()
76 ddr_out32(&mmdc->mdctl, tmp | MDCTL_SDE0 | MDCTL_SDE1); in mmdc_init()
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