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Searched refs:mask (Results 1 – 25 of 119) sorted by relevance

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/trusted-firmware-a-latest/drivers/marvell/comphy/
Dphy-comphy-cp110.c116 uint32_t reg, mask, field; in mvebu_cp110_comphy_clr_pipe_selector() local
120 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_clr_pipe_selector()
122 field = reg & mask; in mvebu_cp110_comphy_clr_pipe_selector()
125 reg &= ~mask; in mvebu_cp110_comphy_clr_pipe_selector()
135 uint32_t reg, mask, field; in mvebu_cp110_comphy_clr_phy_selector() local
139 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_clr_phy_selector()
141 field = reg & mask; in mvebu_cp110_comphy_clr_phy_selector()
149 reg &= ~mask; in mvebu_cp110_comphy_clr_phy_selector()
159 uint32_t reg, mask; in mvebu_cp110_comphy_set_phy_selector() local
174 mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; in mvebu_cp110_comphy_set_phy_selector()
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Dphy-comphy-3700.c218 uint16_t mask, bool is_sata) in comphy_set_indirect() argument
235 reg_set(addr + COMPHY_LANE2_INDIR_DATA_OFFSET, data, mask); in comphy_set_indirect()
240 uint16_t data, uint16_t mask) in comphy_sata_set_indirect() argument
242 comphy_set_indirect(addr, reg_offset, data, mask, true); in comphy_sata_set_indirect()
247 uint16_t data, uint16_t mask) in comphy_usb3_set_indirect() argument
249 comphy_set_indirect(addr, reg_offset, data, mask, false); in comphy_usb3_set_indirect()
254 uint16_t data, uint16_t mask) in comphy_usb3_set_direct() argument
256 reg_set16((reg_offset * PHY_SHFT(USB3) + addr), data, mask); in comphy_usb3_set_direct()
374 uint32_t mask, data; in mvebu_a3700_comphy_sgmii_power_on() local
405 mask = data | PIN_RESET_CORE_BIT | PIN_PU_PLL_BIT | PIN_PU_RX_BIT | in mvebu_a3700_comphy_sgmii_power_on()
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Dphy-comphy-common.h125 uint32_t mask, in polling_with_timeout() argument
134 data = mmio_read_16(addr) & mask; in polling_with_timeout()
136 data = mmio_read_32(addr) & mask; in polling_with_timeout()
145 static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) in reg_set() argument
148 addr, data, mask); in reg_set()
150 mmio_clrsetbits_32(addr, mask, data & mask); in reg_set()
156 uint16_t mask) in reg_set16() argument
160 addr, data, mask); in reg_set16()
162 mmio_clrsetbits_16(addr, mask, data & mask); in reg_set16()
/trusted-firmware-a-latest/plat/mediatek/drivers/cirq/
Dmt_cirq.c25 int mt_irq_mask_restore(struct mtk_irq_mask *mask) in mt_irq_mask_restore() argument
27 if (mask == NULL) { in mt_irq_mask_restore()
30 if (mask->header != IRQ_MASK_HEADER) { in mt_irq_mask_restore()
33 if (mask->footer != IRQ_MASK_FOOTER) { in mt_irq_mask_restore()
38 mask->mask1); in mt_irq_mask_restore()
40 mask->mask2); in mt_irq_mask_restore()
42 mask->mask3); in mt_irq_mask_restore()
44 mask->mask4); in mt_irq_mask_restore()
46 mask->mask5); in mt_irq_mask_restore()
48 mask->mask6); in mt_irq_mask_restore()
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/trusted-firmware-a-latest/services/std_svc/trng/
Dtrng_main.c25 uint32_t mask = ~0U; in trng_rnd32() local
37 mask >>= 32U - (nbits % 32U); in trng_rnd32()
42 SMC_RET4(handle, TRNG_E_SUCCESS, 0, 0, ent[0] & mask); in trng_rnd32()
45 SMC_RET4(handle, TRNG_E_SUCCESS, 0, (ent[0] >> 32) & mask, in trng_rnd32()
49 SMC_RET4(handle, TRNG_E_SUCCESS, ent[1] & mask, in trng_rnd32()
61 uint64_t mask = ~0ULL; in trng_rnd64() local
74 mask >>= 64U - (nbits % 64U); in trng_rnd64()
79 SMC_RET4(handle, TRNG_E_SUCCESS, 0, 0, ent[0] & mask); in trng_rnd64()
82 SMC_RET4(handle, TRNG_E_SUCCESS, 0, ent[1] & mask, ent[0]); in trng_rnd64()
85 SMC_RET4(handle, TRNG_E_SUCCESS, ent[2] & mask, ent[1], ent[0]); in trng_rnd64()
/trusted-firmware-a-latest/lib/cpus/aarch64/
Dcpuamu.c15 unsigned int mask; member
38 ctx->mask = cpuamu_read_cpuamcntenset_el0(); in cpuamu_context_save()
41 cpuamu_write_cpuamcntenclr_el0(ctx->mask); in cpuamu_context_save()
60 cpuamu_write_cpuamcntenclr_el0(ctx->mask); in cpuamu_context_restore()
69 cpuamu_write_cpuamcntenset_el0(ctx->mask); in cpuamu_context_restore()
/trusted-firmware-a-latest/plat/intel/soc/common/soc/
Dsocfpga_reset_manager.c98 static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match, uint32_t delay_ms) in poll_idle_status() argument
104 if ((mmio_read_32(addr) & mask) == match) { in poll_idle_status()
113 static int poll_idle_status_by_counter(uint32_t addr, uint32_t mask, in poll_idle_status_by_counter() argument
120 if ((mmio_read_32(addr) & mask) == match) { in poll_idle_status_by_counter()
133 static int poll_idle_status_by_clkcycles(uint32_t addr, uint32_t mask, in poll_idle_status_by_clkcycles() argument
140 if ((mmio_read_32(addr) & mask) == match) { in poll_idle_status_by_clkcycles()
148 static void socfpga_s2f_bridge_mask(uint32_t mask, in socfpga_s2f_bridge_mask() argument
155 if ((mask & SOC2FPGA_MASK) != 0U) { in socfpga_s2f_bridge_mask()
160 if ((mask & LWHPS2FPGA_MASK) != 0U) { in socfpga_s2f_bridge_mask()
166 static void socfpga_f2s_bridge_mask(uint32_t mask, in socfpga_f2s_bridge_mask() argument
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/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t210/
Dplat_psci_handlers.c275 uint32_t val, mask; in tegra_reset_all_dma_masters() local
307 mask = GPU_RESET_BIT; in tegra_reset_all_dma_masters()
308 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
311 mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT | in tegra_reset_all_dma_masters()
314 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
317 mask = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT | in tegra_reset_all_dma_masters()
321 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
324 mask = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT; in tegra_reset_all_dma_masters()
326 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
329 mask = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT | in tegra_reset_all_dma_masters()
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/trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/spmc/
Dmtspmc.c127 int spm_get_powerstate(uint32_t mask) in spm_get_powerstate() argument
129 return mmio_read_32(SPM_PWR_STATUS) & mask; in spm_get_powerstate()
134 uint32_t mask; in spm_get_cluster_powerstate() local
136 mask = cluster ? PWR_STATUS_MP1_CPUTOP : PWR_STATUS_MP0_CPUTOP; in spm_get_cluster_powerstate()
138 return spm_get_powerstate(mask); in spm_get_cluster_powerstate()
259 uint32_t mask; in spm_poweroff_cluster() local
266 mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK : in spm_poweroff_cluster()
268 mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_SET, mask); in spm_poweroff_cluster()
270 while ((mmio_read_32(INFRA_TOPAXI_PROTECTEN_STA1_1) & mask) != mask) in spm_poweroff_cluster()
278 mask = (cluster) ? MP1_SPMC_SRAM_DORMANT_EN : MP0_SPMC_SRAM_DORMANT_EN; in spm_poweroff_cluster()
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/trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/mcdi/
Dmtk_mcdi.h18 uint32_t mcdi_avail_cpu_mask_write(uint32_t mask);
19 uint32_t mcdi_avail_cpu_mask_set(uint32_t mask);
20 uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask);
Dmtk_mcdi.c48 uint32_t mcdi_avail_cpu_mask_write(uint32_t mask) in mcdi_avail_cpu_mask_write() argument
50 mcdi_mbox_write(MCDI_MBOX_AVAIL_CPU_MASK, mask); in mcdi_avail_cpu_mask_write()
52 return mask; in mcdi_avail_cpu_mask_write()
55 uint32_t mcdi_avail_cpu_mask_set(uint32_t mask) in mcdi_avail_cpu_mask_set() argument
60 m |= mask; in mcdi_avail_cpu_mask_set()
66 uint32_t mcdi_avail_cpu_mask_clr(uint32_t mask) in mcdi_avail_cpu_mask_clr() argument
71 m &= ~mask; in mcdi_avail_cpu_mask_clr()
/trusted-firmware-a-latest/plat/xilinx/zynqmp/pm_service/
Dpm_api_ioctl.c189 uint32_t mask, val; in pm_ioctl_sd_dll_reset() local
193 mask = ZYNQMP_SD0_DLL_RST_MASK; in pm_ioctl_sd_dll_reset()
196 mask = ZYNQMP_SD1_DLL_RST_MASK; in pm_ioctl_sd_dll_reset()
205 ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, val); in pm_ioctl_sd_dll_reset()
216 ret = pm_mmio_write(ZYNQMP_SD_DLL_CTRL, mask, 0); in pm_ioctl_sd_dll_reset()
243 uint32_t val, mask; in pm_ioctl_sd_set_tapdelay() local
247 mask = ZYNQMP_SD0_DLL_RST_MASK; in pm_ioctl_sd_set_tapdelay()
250 mask = ZYNQMP_SD1_DLL_RST_MASK; in pm_ioctl_sd_set_tapdelay()
260 if ((val & mask) == 0U) { in pm_ioctl_sd_set_tapdelay()
317 if ((val & mask) == 0) { in pm_ioctl_sd_set_tapdelay()
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/trusted-firmware-a-latest/plat/imx/common/sci/
Dimx8_mu.c46 uint32_t mask = MU_SR_TE0_MASK1 >> regIndex; in MU_SendMessage() local
49 while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) in MU_SendMessage()
56 uint32_t mask = MU_SR_RF0_MASK1 >> regIndex; in MU_ReceiveMsg() local
59 while (!(mmio_read_32(base + MU_ASR_OFFSET1) & mask)) in MU_ReceiveMsg()
/trusted-firmware-a-latest/plat/intel/soc/common/include/
Dsocfpga_vab.h33 #define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) argument
/trusted-firmware-a-latest/drivers/nxp/sfp/
Dfuse_prov.c24 uint32_t mask) in write_a_fuse() argument
29 if ((last_stored_val & mask) == mask) { in write_a_fuse()
34 sfp_write32(fuse_addr, last_stored_val | (*fuse_hdr_val & mask)); in write_a_fuse()
37 if (sfp_read32(fuse_addr) != (last_stored_val | (*fuse_hdr_val & mask))) { in write_a_fuse()
329 uint32_t mask = 0; in prog_ospr1() local
333 mask = OSPR1_MC_MASK; in prog_ospr1()
337 mask = mask | OSPR1_DBG_LVL_MASK; in prog_ospr1()
340 ret = write_a_fuse(&sfp_ccsr_regs->ospr1, &fuse_hdr->ospr1, mask); in prog_ospr1()
/trusted-firmware-a-latest/plat/socionext/uniphier/
Duniphier_soc_info.c15 static unsigned int uniphier_get_revision_field(unsigned int mask, in uniphier_get_revision_field() argument
25 return (mmio_read_32(reg) >> shift) & mask; in uniphier_get_revision_field()
/trusted-firmware-a-latest/drivers/arm/smmu/
Dsmmu_v3.c17 static int smmuv3_poll(uintptr_t smmu_reg, uint32_t mask, in smmuv3_poll() argument
27 if ((reg_val & mask) == value) in smmuv3_poll()
33 value == 0U ? reg_val & ~mask : reg_val | mask); in smmuv3_poll()
/trusted-firmware-a-latest/include/lib/cpus/aarch64/
Dcortex_a75.h51 void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
52 void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
Dcpuamu.h39 void cpuamu_write_cpuamcntenset_el0(unsigned int mask);
40 void cpuamu_write_cpuamcntenclr_el0(unsigned int mask);
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/spmc/
Dmtspmc.c68 bool spm_get_powerstate(uint32_t mask) in spm_get_powerstate() argument
70 return (mmio_read_32(SPM_CPU_PWR_STATUS) & mask); in spm_get_powerstate()
82 uint32_t mask = BIT(cpu); in spm_get_cpu_powerstate() local
86 return spm_get_powerstate(mask); in spm_get_cpu_powerstate()
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/spmc/
Dmtspmc.c66 bool spm_get_powerstate(uint32_t mask) in spm_get_powerstate() argument
68 return (mmio_read_32(MCUCFG_CPC_SPMC_PWR_STATUS) & mask) != 0U; in spm_get_powerstate()
80 uint32_t mask = BIT(cpu); in spm_get_cpu_powerstate() local
84 return spm_get_powerstate(mask); in spm_get_cpu_powerstate()
/trusted-firmware-a-latest/plat/allwinner/common/
Darisc_off.S19 # It expects the core number presented as a mask in the upper half of
26 # - Using that mask, activate the core output clamps by setting the
30 # - Using the negated mask, assert the core's reset line by clearing the
65 l.xori r6, r6, -1 # negate core mask
69 l.ff1 r6, r3 # get core number from high mask
83 l.movhi r3, 0 # FIXUP! with core mask
88 l.and r5, r5, r3 # mask requested core
92 l.srli r6, r3, 16 # move mask to lower 16 bits(ds)
/trusted-firmware-a-latest/plat/hisilicon/hikey960/
Dhikey960_bl1_setup.c111 unsigned int data, mask; in hikey960_ufs_reset() local
136 mask = SC_DIV_UFS_PERIBUS << 16; in hikey960_ufs_reset()
137 mmio_write_32(CRG_CLKDIV17_REG, mask); in hikey960_ufs_reset()
139 mask = SC_DIV_UFSPHY_CFG_MASK << 16; in hikey960_ufs_reset()
141 mmio_write_32(CRG_CLKDIV16_REG, mask | data); in hikey960_ufs_reset()
/trusted-firmware-a-latest/drivers/st/pmic/
Dstpmic1.c686 uint8_t mask; in stpmic1_regulator_voltage_set() local
700 mask = BUCK_VOLTAGE_MASK; in stpmic1_regulator_voltage_set()
703 mask = LDO_VOLTAGE_MASK; in stpmic1_regulator_voltage_set()
710 mask); in stpmic1_regulator_voltage_set()
819 uint8_t mask; in stpmic1_regulator_voltage_get() local
828 mask = BUCK_VOLTAGE_MASK; in stpmic1_regulator_voltage_get()
831 mask = LDO_VOLTAGE_MASK; in stpmic1_regulator_voltage_get()
841 value = (value & mask) >> LDO_BUCK_VOLTAGE_SHIFT; in stpmic1_regulator_voltage_get()
889 int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask) in stpmic1_register_update() argument
899 val = (val & ~mask) | (value & mask); in stpmic1_register_update()
/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/spmc/
Dmtspmc.c66 bool spm_get_powerstate(uint32_t mask) in spm_get_powerstate() argument
68 return (mmio_read_32(SPM_CPU_PWR_STATUS) & mask) != 0U; in spm_get_powerstate()
80 uint32_t mask = BIT(cpu); in spm_get_cpu_powerstate() local
84 return spm_get_powerstate(mask); in spm_get_cpu_powerstate()

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