Lines Matching refs:mask
275 uint32_t val, mask; in tegra_reset_all_dma_masters() local
307 mask = GPU_RESET_BIT; in tegra_reset_all_dma_masters()
308 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
311 mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT | in tegra_reset_all_dma_masters()
314 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
317 mask = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT | in tegra_reset_all_dma_masters()
321 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
324 mask = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT; in tegra_reset_all_dma_masters()
326 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
329 mask = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT | in tegra_reset_all_dma_masters()
332 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
336 mask = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT; in tegra_reset_all_dma_masters()
337 if ((val & mask) != mask) in tegra_reset_all_dma_masters()
563 uint32_t mask = CPU_CORE_RESET_MASK << cpu; in tegra_soc_pwr_domain_on() local
566 mmio_write_32(TEGRA_CAR_RESET_BASE + CPU_CMPLX_RESET_CLR, mask); in tegra_soc_pwr_domain_on()