127 int spm_get_powerstate(uint32_t mask)  in spm_get_powerstate()  argument
129 	return mmio_read_32(SPM_PWR_STATUS) & mask;  in spm_get_powerstate()
134 	uint32_t mask;  in spm_get_cluster_powerstate()  local
136 	mask = cluster ? PWR_STATUS_MP1_CPUTOP : PWR_STATUS_MP0_CPUTOP;  in spm_get_cluster_powerstate()
138 	return spm_get_powerstate(mask);  in spm_get_cluster_powerstate()
259 	uint32_t mask;  in spm_poweroff_cluster()  local
266 	mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :  in spm_poweroff_cluster()
268 	mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_SET, mask);  in spm_poweroff_cluster()
270 	while ((mmio_read_32(INFRA_TOPAXI_PROTECTEN_STA1_1) & mask) != mask)  in spm_poweroff_cluster()
278 	mask = (cluster) ? MP1_SPMC_SRAM_DORMANT_EN : MP0_SPMC_SRAM_DORMANT_EN;  in spm_poweroff_cluster()
279 	mmio_clrbits_32(SPM_SPMC_DORMANT_ENABLE, mask);  in spm_poweroff_cluster()
313 	uint32_t mask;  in spm_poweron_cluster()  local
360 	mask = (cluster) ? MP1_CPUTOP_PROT_STEP1_0_MASK :  in spm_poweron_cluster()
362 	mmio_write_32(INFRA_TOPAXI_PROTECTEN_1_CLR, mask);  in spm_poweron_cluster()