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Searched refs:SPM_BASE (Results 1 – 23 of 23) sorted by relevance

/trusted-firmware-a-latest/plat/mediatek/mt8188/include/
Dspm_reg.h13 #define MD32PCM_CFG_BASE (SPM_BASE + 0xA00)
14 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
15 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
16 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
17 #define SPM_CLK_CON (SPM_BASE + 0x00C)
18 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
19 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
20 #define PCM_CON0 (SPM_BASE + 0x018)
21 #define PCM_CON1 (SPM_BASE + 0x01C)
22 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
[all …]
Dplatform_def.h61 #define SPM_BASE (IO_PHYS + 0x00006000) macro
143 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/spm/
Dmt_spm_reg.h23 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
24 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
25 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
26 #define SPM_CLK_CON (SPM_BASE + 0x00C)
27 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
28 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
29 #define PCM_CON0 (SPM_BASE + 0x018)
30 #define PCM_CON1 (SPM_BASE + 0x01C)
31 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
32 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
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Dmt_spm_cond.c20 #define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/spm/
Dmt_spm_reg.h20 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
21 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
22 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
23 #define SPM_CLK_CON (SPM_BASE + 0x00C)
24 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
25 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
26 #define PCM_CON0 (SPM_BASE + 0x018)
27 #define PCM_CON1 (SPM_BASE + 0x01C)
28 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
29 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
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Dmt_spm_cond.c21 #define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/spm/
Dmt_spm_reg.h15 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
16 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
17 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
18 #define SPM_CLK_CON (SPM_BASE + 0x00C)
19 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
20 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
21 #define PCM_CON0 (SPM_BASE + 0x018)
22 #define PCM_CON1 (SPM_BASE + 0x01C)
23 #define SPM_POWER_ON_VAL2 (SPM_BASE + 0x020)
24 #define SPM_POWER_ON_VAL3 (SPM_BASE + 0x024)
[all …]
Dmt_spm_cond.c20 #define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
/trusted-firmware-a-latest/plat/mediatek/mt8173/drivers/spm/
Dspm.h9 #define SPM_POWERON_CONFIG_SET (SPM_BASE + 0x000)
10 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x010)
11 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x014)
12 #define SPM_CLK_SETTLE (SPM_BASE + 0x100)
13 #define SPM_CA7_CPU1_PWR_CON (SPM_BASE + 0x218)
14 #define SPM_CA7_CPU2_PWR_CON (SPM_BASE + 0x21c)
15 #define SPM_CA7_CPU3_PWR_CON (SPM_BASE + 0x220)
16 #define SPM_CA7_CPU1_L1_PDN (SPM_BASE + 0x264)
17 #define SPM_CA7_CPU2_L1_PDN (SPM_BASE + 0x26c)
18 #define SPM_CA7_CPU3_L1_PDN (SPM_BASE + 0x274)
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/spm/
Dspm.h14 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
15 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
16 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
17 #define SPM_CLK_CON (SPM_BASE + 0x00C)
18 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
19 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
20 #define PCM_CON0 (SPM_BASE + 0x018)
21 #define PCM_CON1 (SPM_BASE + 0x01C)
22 #define PCM_IM_PTR (SPM_BASE + 0x020)
23 #define PCM_IM_LEN (SPM_BASE + 0x024)
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8183/drivers/spmc/
Dmtspmc_private.h23 #define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
29 #define SPM_PWR_STATUS (SPM_BASE + 0x180)
30 #define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184)
32 #define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4)
33 #define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8)
35 #define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
36 #define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
37 #define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
38 #define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
39 #define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
[all …]
/trusted-firmware-a-latest/plat/mediatek/mt8186/include/
Dplatform_def.h27 #define SPM_BASE (IO_PHYS + 0x00006000) macro
44 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/trusted-firmware-a-latest/plat/mediatek/mt8183/
Dplat_dcm.c19 #define PWR_STATUS (SPM_BASE + 0x180)
/trusted-firmware-a-latest/plat/mediatek/mt8192/include/
Dplatform_def.h42 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/trusted-firmware-a-latest/plat/mediatek/mt8173/include/
Dmt8173_def.h22 #define SPM_BASE (IO_PHYS + 0x6000) macro
/trusted-firmware-a-latest/plat/mediatek/mt8195/include/
Dplatform_def.h36 #define SPM_BASE (IO_PHYS + 0x00006000) macro
/trusted-firmware-a-latest/plat/mediatek/mt8192/drivers/spmc/
Dmtspmc_private.h32 #define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
/trusted-firmware-a-latest/plat/mediatek/mt8186/drivers/spmc/
Dmtspmc_private.h30 #define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
/trusted-firmware-a-latest/plat/mediatek/mt8195/drivers/spmc/
Dmtspmc_private.h32 #define SPM_REG(ofs) (uint32_t)(SPM_BASE + (ofs))
/trusted-firmware-a-latest/plat/mediatek/mt8183/include/
Dplatform_def.h19 #define SPM_BASE (IO_PHYS + 0x6000) macro
/trusted-firmware-a-latest/plat/mediatek/drivers/spm/mt8188/
Dmt_spm_cond.c19 #define MT_LP_TZ_SPM_REG(ofs) (SPM_BASE + ofs)
Dmt_spm_internal.h90 #define MD32PCM_BASE (SPM_BASE + 0x0A00)
/trusted-firmware-a-latest/plat/mediatek/drivers/apusys/mt8188/
Dapusys_power.c432 mmio_clrbits_32(SPM_BASE + APUSYS_BUCK_ISOLATION, IPU_EXT_BUCK_ISO); in apu_aoc_init()