Lines Matching refs:SPM_BASE
14 #define POWERON_CONFIG_EN (SPM_BASE + 0x000)
15 #define SPM_POWER_ON_VAL0 (SPM_BASE + 0x004)
16 #define SPM_POWER_ON_VAL1 (SPM_BASE + 0x008)
17 #define SPM_CLK_CON (SPM_BASE + 0x00C)
18 #define SPM_CLK_SETTLE (SPM_BASE + 0x010)
19 #define SPM_AP_STANDBY_CON (SPM_BASE + 0x014)
20 #define PCM_CON0 (SPM_BASE + 0x018)
21 #define PCM_CON1 (SPM_BASE + 0x01C)
22 #define PCM_IM_PTR (SPM_BASE + 0x020)
23 #define PCM_IM_LEN (SPM_BASE + 0x024)
24 #define PCM_REG_DATA_INI (SPM_BASE + 0x028)
25 #define PCM_PWR_IO_EN (SPM_BASE + 0x02C)
26 #define PCM_TIMER_VAL (SPM_BASE + 0x030)
27 #define PCM_WDT_VAL (SPM_BASE + 0x034)
28 #define PCM_IM_HOST_RW_PTR (SPM_BASE + 0x038)
29 #define PCM_IM_HOST_RW_DAT (SPM_BASE + 0x03C)
30 #define PCM_EVENT_VECTOR0 (SPM_BASE + 0x040)
31 #define PCM_EVENT_VECTOR1 (SPM_BASE + 0x044)
32 #define PCM_EVENT_VECTOR2 (SPM_BASE + 0x048)
33 #define PCM_EVENT_VECTOR3 (SPM_BASE + 0x04C)
34 #define PCM_EVENT_VECTOR4 (SPM_BASE + 0x050)
35 #define PCM_EVENT_VECTOR5 (SPM_BASE + 0x054)
36 #define PCM_EVENT_VECTOR6 (SPM_BASE + 0x058)
37 #define PCM_EVENT_VECTOR7 (SPM_BASE + 0x05C)
38 #define PCM_EVENT_VECTOR8 (SPM_BASE + 0x060)
39 #define PCM_EVENT_VECTOR9 (SPM_BASE + 0x064)
40 #define PCM_EVENT_VECTOR10 (SPM_BASE + 0x068)
41 #define PCM_EVENT_VECTOR11 (SPM_BASE + 0x06C)
42 #define PCM_EVENT_VECTOR12 (SPM_BASE + 0x070)
43 #define PCM_EVENT_VECTOR13 (SPM_BASE + 0x074)
44 #define PCM_EVENT_VECTOR14 (SPM_BASE + 0x078)
45 #define PCM_EVENT_VECTOR15 (SPM_BASE + 0x07C)
46 #define PCM_EVENT_VECTOR_EN (SPM_BASE + 0x080)
47 #define SPM_SRAM_RSV_CON (SPM_BASE + 0x088)
48 #define SPM_SWINT (SPM_BASE + 0x08C)
49 #define SPM_SWINT_SET (SPM_BASE + 0x090)
50 #define SPM_SWINT_CLR (SPM_BASE + 0x094)
51 #define SPM_SCP_MAILBOX (SPM_BASE + 0x098)
52 #define SCP_SPM_MAILBOX (SPM_BASE + 0x09C)
53 #define SPM_TWAM_CON (SPM_BASE + 0x0A0)
54 #define SPM_TWAM_WINDOW_LEN (SPM_BASE + 0x0A4)
55 #define SPM_TWAM_IDLE_SEL (SPM_BASE + 0x0A8)
56 #define SPM_SCP_IRQ (SPM_BASE + 0x0AC)
57 #define SPM_CPU_WAKEUP_EVENT (SPM_BASE + 0x0B0)
58 #define SPM_IRQ_MASK (SPM_BASE + 0x0B4)
59 #define SPM_SRC_REQ (SPM_BASE + 0x0B8)
60 #define SPM_SRC_MASK (SPM_BASE + 0x0BC)
61 #define SPM_SRC2_MASK (SPM_BASE + 0x0C0)
62 #define SPM_WAKEUP_EVENT_MASK (SPM_BASE + 0x0C4)
63 #define SPM_WAKEUP_EVENT_EXT_MASK (SPM_BASE + 0x0C8)
64 #define SPM_TWAM_EVENT_CLEAR (SPM_BASE + 0x0CC)
65 #define SCP_CLK_CON (SPM_BASE + 0x0D0)
66 #define PCM_DEBUG_CON (SPM_BASE + 0x0D4)
67 #define DDR_EN_DBC_LEN (SPM_BASE + 0x0D8)
68 #define AHB_BUS_CON (SPM_BASE + 0x0DC)
69 #define SPM_SRC3_MASK (SPM_BASE + 0x0E0)
70 #define DDR_EN_EMI_DBC_CON (SPM_BASE + 0x0E4)
71 #define SSPM_CLK_CON (SPM_BASE + 0x0E8)
72 #define PCM_REG0_DATA (SPM_BASE + 0x100)
73 #define PCM_REG1_DATA (SPM_BASE + 0x104)
74 #define PCM_REG2_DATA (SPM_BASE + 0x108)
75 #define PCM_REG3_DATA (SPM_BASE + 0x10C)
76 #define PCM_REG4_DATA (SPM_BASE + 0x110)
77 #define PCM_REG5_DATA (SPM_BASE + 0x114)
78 #define PCM_REG6_DATA (SPM_BASE + 0x118)
79 #define PCM_REG7_DATA (SPM_BASE + 0x11C)
80 #define PCM_REG8_DATA (SPM_BASE + 0x120)
81 #define PCM_REG9_DATA (SPM_BASE + 0x124)
82 #define PCM_REG10_DATA (SPM_BASE + 0x128)
83 #define PCM_REG11_DATA (SPM_BASE + 0x12C)
84 #define PCM_REG12_DATA (SPM_BASE + 0x130)
85 #define PCM_REG13_DATA (SPM_BASE + 0x134)
86 #define PCM_REG14_DATA (SPM_BASE + 0x138)
87 #define PCM_REG15_DATA (SPM_BASE + 0x13C)
88 #define PCM_REG12_MASK_B_STA (SPM_BASE + 0x140)
89 #define PCM_REG12_EXT_DATA (SPM_BASE + 0x144)
90 #define PCM_REG12_EXT_MASK_B_STA (SPM_BASE + 0x148)
91 #define PCM_EVENT_REG_STA (SPM_BASE + 0x14C)
92 #define PCM_TIMER_OUT (SPM_BASE + 0x150)
93 #define PCM_WDT_OUT (SPM_BASE + 0x154)
94 #define SPM_IRQ_STA (SPM_BASE + 0x158)
95 #define SPM_WAKEUP_STA (SPM_BASE + 0x15C)
96 #define SPM_WAKEUP_EXT_STA (SPM_BASE + 0x160)
97 #define SPM_WAKEUP_MISC (SPM_BASE + 0x164)
98 #define BUS_PROTECT_RDY (SPM_BASE + 0x168)
99 #define BUS_PROTECT2_RDY (SPM_BASE + 0x16C)
100 #define SUBSYS_IDLE_STA (SPM_BASE + 0x170)
101 #define CPU_IDLE_STA (SPM_BASE + 0x174)
102 #define PCM_FSM_STA (SPM_BASE + 0x178)
103 #define SRC_REQ_STA (SPM_BASE + 0x17C)
104 #define PWR_STATUS (SPM_BASE + 0x180)
105 #define PWR_STATUS_2ND (SPM_BASE + 0x184)
106 #define CPU_PWR_STATUS (SPM_BASE + 0x188)
107 #define CPU_PWR_STATUS_2ND (SPM_BASE + 0x18C)
108 #define MISC_STA (SPM_BASE + 0x190)
109 #define SPM_SRC_RDY_STA (SPM_BASE + 0x194)
110 #define DRAMC_DBG_LATCH (SPM_BASE + 0x19C)
111 #define SPM_TWAM_LAST_STA0 (SPM_BASE + 0x1A0)
112 #define SPM_TWAM_LAST_STA1 (SPM_BASE + 0x1A4)
113 #define SPM_TWAM_LAST_STA2 (SPM_BASE + 0x1A8)
114 #define SPM_TWAM_LAST_STA3 (SPM_BASE + 0x1AC)
115 #define SPM_TWAM_CURR_STA0 (SPM_BASE + 0x1B0)
116 #define SPM_TWAM_CURR_STA1 (SPM_BASE + 0x1B4)
117 #define SPM_TWAM_CURR_STA2 (SPM_BASE + 0x1B8)
118 #define SPM_TWAM_CURR_STA3 (SPM_BASE + 0x1BC)
119 #define SPM_TWAM_TIMER_OUT (SPM_BASE + 0x1C0)
120 #define SPM_DVFS_STA (SPM_BASE + 0x1C8)
121 #define BUS_PROTECT3_RDY (SPM_BASE + 0x1CC)
122 #define SRC_DDREN_STA (SPM_BASE + 0x1E0)
123 #define MCU_PWR_CON (SPM_BASE + 0x200)
124 #define MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
125 #define MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
126 #define MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
127 #define MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
128 #define MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
129 #define MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218)
130 #define MP1_CPU0_PWR_CON (SPM_BASE + 0x21C)
131 #define MP1_CPU1_PWR_CON (SPM_BASE + 0x220)
132 #define MP1_CPU2_PWR_CON (SPM_BASE + 0x224)
133 #define MP1_CPU3_PWR_CON (SPM_BASE + 0x228)
134 #define MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240)
135 #define MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244)
136 #define MP0_CPU0_L1_PDN (SPM_BASE + 0x248)
137 #define MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)
138 #define MP0_CPU2_L1_PDN (SPM_BASE + 0x250)
139 #define MP0_CPU3_L1_PDN (SPM_BASE + 0x254)
140 #define MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258)
141 #define MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C)
142 #define MP1_CPU0_L1_PDN (SPM_BASE + 0x260)
143 #define MP1_CPU1_L1_PDN (SPM_BASE + 0x264)
144 #define MP1_CPU2_L1_PDN (SPM_BASE + 0x268)
145 #define MP1_CPU3_L1_PDN (SPM_BASE + 0x26C)
146 #define CPU_EXT_BUCK_ISO (SPM_BASE + 0x290)
147 #define DUMMY1_PWR_CON (SPM_BASE + 0x2B0)
148 #define BYPASS_SPMC (SPM_BASE + 0x2B4)
149 #define SPMC_DORMANT_ENABLE (SPM_BASE + 0x2B8)
150 #define ARMPLL_CLK_CON (SPM_BASE + 0x2BC)
151 #define SPMC_IN_RET (SPM_BASE + 0x2C0)
152 #define VDE_PWR_CON (SPM_BASE + 0x300)
153 #define VEN_PWR_CON (SPM_BASE + 0x304)
154 #define ISP_PWR_CON (SPM_BASE + 0x308)
155 #define DIS_PWR_CON (SPM_BASE + 0x30C)
156 #define MFG_CORE1_PWR_CON (SPM_BASE + 0x310)
157 #define AUDIO_PWR_CON (SPM_BASE + 0x314)
158 #define IFR_PWR_CON (SPM_BASE + 0x318)
159 #define DPY_PWR_CON (SPM_BASE + 0x31C)
160 #define MD1_PWR_CON (SPM_BASE + 0x320)
161 #define VPU_TOP_PWR_CON (SPM_BASE + 0x324)
162 #define CONN_PWR_CON (SPM_BASE + 0x32C)
163 #define VPU_CORE2_PWR_CON (SPM_BASE + 0x330)
164 #define MFG_ASYNC_PWR_CON (SPM_BASE + 0x334)
165 #define MFG_PWR_CON (SPM_BASE + 0x338)
166 #define VPU_CORE0_PWR_CON (SPM_BASE + 0x33C)
167 #define VPU_CORE1_PWR_CON (SPM_BASE + 0x340)
168 #define CAM_PWR_CON (SPM_BASE + 0x344)
169 #define MFG_2D_PWR_CON (SPM_BASE + 0x348)
170 #define MFG_CORE0_PWR_CON (SPM_BASE + 0x34C)
171 #define SYSRAM_CON (SPM_BASE + 0x350)
172 #define SYSROM_CON (SPM_BASE + 0x354)
173 #define SSPM_SRAM_CON (SPM_BASE + 0x358)
174 #define SCP_SRAM_CON (SPM_BASE + 0x35C)
175 #define UFS_SRAM_CON (SPM_BASE + 0x36C)
176 #define DUMMY_SRAM_CON (SPM_BASE + 0x380)
177 #define MD_EXT_BUCK_ISO_CON (SPM_BASE + 0x390)
178 #define MD_SRAM_ISO_CON (SPM_BASE + 0x394)
179 #define MD_EXTRA_PWR_CON (SPM_BASE + 0x398)
180 #define EXT_BUCK_CON (SPM_BASE + 0x3A0)
181 #define MBIST_EFUSE_REPAIR_ACK_STA (SPM_BASE + 0x3D0)
182 #define SPM_DVFS_CON (SPM_BASE + 0x400)
183 #define SPM_MDBSI_CON (SPM_BASE + 0x404)
184 #define SPM_MAS_PAUSE_MASK_B (SPM_BASE + 0x408)
185 #define SPM_MAS_PAUSE2_MASK_B (SPM_BASE + 0x40C)
186 #define SPM_BSI_GEN (SPM_BASE + 0x410)
187 #define SPM_BSI_EN_SR (SPM_BASE + 0x414)
188 #define SPM_BSI_CLK_SR (SPM_BASE + 0x418)
189 #define SPM_BSI_D0_SR (SPM_BASE + 0x41C)
190 #define SPM_BSI_D1_SR (SPM_BASE + 0x420)
191 #define SPM_BSI_D2_SR (SPM_BASE + 0x424)
192 #define SPM_AP_SEMA (SPM_BASE + 0x428)
193 #define SPM_SPM_SEMA (SPM_BASE + 0x42C)
194 #define AP_MDSRC_REQ (SPM_BASE + 0x430)
195 #define SPM2MD_DVFS_CON (SPM_BASE + 0x438)
196 #define MD2SPM_DVFS_CON (SPM_BASE + 0x43C)
197 #define DRAMC_DPY_CLK_SW_CON_RSV (SPM_BASE + 0x440)
198 #define DPY_LP_CON (SPM_BASE + 0x444)
199 #define CPU_DVFS_REQ (SPM_BASE + 0x448)
200 #define SPM_PLL_CON (SPM_BASE + 0x44C)
201 #define SPM_EMI_BW_MODE (SPM_BASE + 0x450)
202 #define AP2MD_PEER_WAKEUP (SPM_BASE + 0x454)
203 #define ULPOSC_CON (SPM_BASE + 0x458)
204 #define SPM2MM_CON (SPM_BASE + 0x45C)
205 #define DRAMC_DPY_CLK_SW_CON_SEL (SPM_BASE + 0x460)
206 #define DRAMC_DPY_CLK_SW_CON (SPM_BASE + 0x464)
207 #define SPM_S1_MODE_CH (SPM_BASE + 0x468)
208 #define EMI_SELF_REFRESH_CH_STA (SPM_BASE + 0x46C)
209 #define DRAMC_DPY_CLK_SW_CON_SEL2 (SPM_BASE + 0x470)
210 #define DRAMC_DPY_CLK_SW_CON2 (SPM_BASE + 0x474)
211 #define DRAMC_DMYRD_CON (SPM_BASE + 0x478)
212 #define SPM_DRS_CON (SPM_BASE + 0x47C)
213 #define SPM_SEMA_M0 (SPM_BASE + 0x480)
214 #define SPM_SEMA_M1 (SPM_BASE + 0x484)
215 #define SPM_SEMA_M2 (SPM_BASE + 0x488)
216 #define SPM_SEMA_M3 (SPM_BASE + 0x48C)
217 #define SPM_SEMA_M4 (SPM_BASE + 0x490)
218 #define SPM_SEMA_M5 (SPM_BASE + 0x494)
219 #define SPM_SEMA_M6 (SPM_BASE + 0x498)
220 #define SPM_SEMA_M7 (SPM_BASE + 0x49C)
221 #define SPM_MAS_PAUSE_MM_MASK_B (SPM_BASE + 0x4A0)
222 #define SPM_MAS_PAUSE_MCU_MASK_B (SPM_BASE + 0x4A4)
223 #define SRAM_DREQ_ACK (SPM_BASE + 0x4AC)
224 #define SRAM_DREQ_CON (SPM_BASE + 0x4B0)
225 #define SRAM_DREQ_CON_SET (SPM_BASE + 0x4B4)
226 #define SRAM_DREQ_CON_CLR (SPM_BASE + 0x4B8)
227 #define SPM2EMI_ENTER_ULPM (SPM_BASE + 0x4BC)
228 #define SPM_SSPM_IRQ (SPM_BASE + 0x4C0)
229 #define SPM2PMCU_INT (SPM_BASE + 0x4C4)
230 #define SPM2PMCU_INT_SET (SPM_BASE + 0x4C8)
231 #define SPM2PMCU_INT_CLR (SPM_BASE + 0x4CC)
232 #define SPM2PMCU_MAILBOX_0 (SPM_BASE + 0x4D0)
233 #define SPM2PMCU_MAILBOX_1 (SPM_BASE + 0x4D4)
234 #define SPM2PMCU_MAILBOX_2 (SPM_BASE + 0x4D8)
235 #define SPM2PMCU_MAILBOX_3 (SPM_BASE + 0x4DC)
236 #define PMCU2SPM_INT (SPM_BASE + 0x4E0)
237 #define PMCU2SPM_INT_SET (SPM_BASE + 0x4E4)
238 #define PMCU2SPM_INT_CLR (SPM_BASE + 0x4E8)
239 #define PMCU2SPM_MAILBOX_0 (SPM_BASE + 0x4EC)
240 #define PMCU2SPM_MAILBOX_1 (SPM_BASE + 0x4F0)
241 #define PMCU2SPM_MAILBOX_2 (SPM_BASE + 0x4F4)
242 #define PMCU2SPM_MAILBOX_3 (SPM_BASE + 0x4F8)
243 #define PMCU2SPM_CFG (SPM_BASE + 0x4FC)
244 #define MP0_CPU0_IRQ_MASK (SPM_BASE + 0x500)
245 #define MP0_CPU1_IRQ_MASK (SPM_BASE + 0x504)
246 #define MP0_CPU2_IRQ_MASK (SPM_BASE + 0x508)
247 #define MP0_CPU3_IRQ_MASK (SPM_BASE + 0x50C)
248 #define MP1_CPU0_IRQ_MASK (SPM_BASE + 0x510)
249 #define MP1_CPU1_IRQ_MASK (SPM_BASE + 0x514)
250 #define MP1_CPU2_IRQ_MASK (SPM_BASE + 0x518)
251 #define MP1_CPU3_IRQ_MASK (SPM_BASE + 0x51C)
252 #define MP0_CPU0_WFI_EN (SPM_BASE + 0x530)
253 #define MP0_CPU1_WFI_EN (SPM_BASE + 0x534)
254 #define MP0_CPU2_WFI_EN (SPM_BASE + 0x538)
255 #define MP0_CPU3_WFI_EN (SPM_BASE + 0x53C)
256 #define MP1_CPU0_WFI_EN (SPM_BASE + 0x540)
257 #define MP1_CPU1_WFI_EN (SPM_BASE + 0x544)
258 #define MP1_CPU2_WFI_EN (SPM_BASE + 0x548)
259 #define MP1_CPU3_WFI_EN (SPM_BASE + 0x54C)
260 #define MP0_L2CFLUSH (SPM_BASE + 0x554)
261 #define MP1_L2CFLUSH (SPM_BASE + 0x558)
262 #define CPU_PTPOD2_CON (SPM_BASE + 0x560)
263 #define ROOT_CPUTOP_ADDR (SPM_BASE + 0x570)
264 #define ROOT_CORE_ADDR (SPM_BASE + 0x574)
265 #define CPU_SPARE_CON (SPM_BASE + 0x580)
266 #define CPU_SPARE_CON_SET (SPM_BASE + 0x584)
267 #define CPU_SPARE_CON_CLR (SPM_BASE + 0x588)
268 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x5D0)
269 #define SPM2SW_MAILBOX_1 (SPM_BASE + 0x5D4)
270 #define SPM2SW_MAILBOX_2 (SPM_BASE + 0x5D8)
271 #define SPM2SW_MAILBOX_3 (SPM_BASE + 0x5DC)
272 #define SW2SPM_INT (SPM_BASE + 0x5E0)
273 #define SW2SPM_INT_SET (SPM_BASE + 0x5E4)
274 #define SW2SPM_INT_CLR (SPM_BASE + 0x5E8)
275 #define SW2SPM_MAILBOX_0 (SPM_BASE + 0x5EC)
276 #define SW2SPM_MAILBOX_1 (SPM_BASE + 0x5F0)
277 #define SW2SPM_MAILBOX_2 (SPM_BASE + 0x5F4)
278 #define SW2SPM_MAILBOX_3 (SPM_BASE + 0x5F8)
279 #define SW2SPM_CFG (SPM_BASE + 0x5FC)
280 #define SPM_SW_FLAG (SPM_BASE + 0x600)
281 #define SPM_SW_DEBUG (SPM_BASE + 0x604)
282 #define SPM_SW_RSV_0 (SPM_BASE + 0x608)
283 #define SPM_SW_RSV_1 (SPM_BASE + 0x60C)
284 #define SPM_SW_RSV_2 (SPM_BASE + 0x610)
285 #define SPM_SW_RSV_3 (SPM_BASE + 0x614)
286 #define SPM_SW_RSV_4 (SPM_BASE + 0x618)
287 #define SPM_SW_RSV_5 (SPM_BASE + 0x61C)
288 #define SPM_RSV_CON (SPM_BASE + 0x620)
289 #define SPM_RSV_STA (SPM_BASE + 0x624)
290 #define SPM_RSV_CON1 (SPM_BASE + 0x628)
291 #define SPM_RSV_STA1 (SPM_BASE + 0x62C)
292 #define SPM_PASR_DPD_0 (SPM_BASE + 0x630)
293 #define SPM_PASR_DPD_1 (SPM_BASE + 0x634)
294 #define SPM_PASR_DPD_2 (SPM_BASE + 0x638)
295 #define SPM_PASR_DPD_3 (SPM_BASE + 0x63C)
296 #define SPM_SPARE_CON (SPM_BASE + 0x640)
297 #define SPM_SPARE_CON_SET (SPM_BASE + 0x644)
298 #define SPM_SPARE_CON_CLR (SPM_BASE + 0x648)
299 #define SPM_SW_RSV_6 (SPM_BASE + 0x64C)
300 #define SPM_SW_RSV_7 (SPM_BASE + 0x650)
301 #define SPM_SW_RSV_8 (SPM_BASE + 0x654)
302 #define SPM_SW_RSV_9 (SPM_BASE + 0x658)
303 #define SPM_SW_RSV_10 (SPM_BASE + 0x65C)
304 #define SPM_SW_RSV_18 (SPM_BASE + 0x67C)
305 #define SPM_SW_RSV_19 (SPM_BASE + 0x680)
306 #define DVFSRC_EVENT_MASK_CON (SPM_BASE + 0x690)
307 #define DVFSRC_EVENT_FORCE_ON (SPM_BASE + 0x694)
308 #define DVFSRC_EVENT_SEL (SPM_BASE + 0x698)
309 #define SPM_DVFS_EVENT_STA (SPM_BASE + 0x69C)
310 #define SPM_DVFS_EVENT_STA1 (SPM_BASE + 0x6A0)
311 #define SPM_DVFS_LEVEL (SPM_BASE + 0x6A4)
312 #define DVFS_ABORT_STA (SPM_BASE + 0x6A8)
313 #define DVFS_ABORT_OTHERS_MASK (SPM_BASE + 0x6AC)
314 #define SPM_DFS_LEVEL (SPM_BASE + 0x6B0)
315 #define SPM_DVS_LEVEL (SPM_BASE + 0x6B4)
316 #define SPM_DVFS_MISC (SPM_BASE + 0x6B8)
317 #define SPARE_SRC_REQ_MASK (SPM_BASE + 0x6C0)
318 #define SCP_VCORE_LEVEL (SPM_BASE + 0x6C4)
319 #define SC_MM_CK_SEL_CON (SPM_BASE + 0x6C8)
320 #define SPARE_ACK_STA (SPM_BASE + 0x6F0)
321 #define SPARE_ACK_MASK (SPM_BASE + 0x6F4)
322 #define SPM_DVFS_CON1 (SPM_BASE + 0x700)
323 #define SPM_DVFS_CON1_STA (SPM_BASE + 0x704)
324 #define SPM_DVFS_CMD0 (SPM_BASE + 0x710)
325 #define SPM_DVFS_CMD1 (SPM_BASE + 0x714)
326 #define SPM_DVFS_CMD2 (SPM_BASE + 0x718)
327 #define SPM_DVFS_CMD3 (SPM_BASE + 0x71C)
328 #define SPM_DVFS_CMD4 (SPM_BASE + 0x720)
329 #define SPM_DVFS_CMD5 (SPM_BASE + 0x724)
330 #define SPM_DVFS_CMD6 (SPM_BASE + 0x728)
331 #define SPM_DVFS_CMD7 (SPM_BASE + 0x72C)
332 #define SPM_DVFS_CMD8 (SPM_BASE + 0x730)
333 #define SPM_DVFS_CMD9 (SPM_BASE + 0x734)
334 #define SPM_DVFS_CMD10 (SPM_BASE + 0x738)
335 #define SPM_DVFS_CMD11 (SPM_BASE + 0x73C)
336 #define SPM_DVFS_CMD12 (SPM_BASE + 0x740)
337 #define SPM_DVFS_CMD13 (SPM_BASE + 0x744)
338 #define SPM_DVFS_CMD14 (SPM_BASE + 0x748)
339 #define SPM_DVFS_CMD15 (SPM_BASE + 0x74C)
340 #define WDT_LATCH_SPARE0_FIX (SPM_BASE + 0x780)
341 #define WDT_LATCH_SPARE1_FIX (SPM_BASE + 0x784)
342 #define WDT_LATCH_SPARE2_FIX (SPM_BASE + 0x788)
343 #define WDT_LATCH_SPARE3_FIX (SPM_BASE + 0x78C)
344 #define SPARE_ACK_IN_FIX (SPM_BASE + 0x790)
345 #define DCHA_LATCH_RSV0_FIX (SPM_BASE + 0x794)
346 #define DCHB_LATCH_RSV0_FIX (SPM_BASE + 0x798)
347 #define PCM_WDT_LATCH_0 (SPM_BASE + 0x800)
348 #define PCM_WDT_LATCH_1 (SPM_BASE + 0x804)
349 #define PCM_WDT_LATCH_2 (SPM_BASE + 0x808)
350 #define PCM_WDT_LATCH_3 (SPM_BASE + 0x80C)
351 #define PCM_WDT_LATCH_4 (SPM_BASE + 0x810)
352 #define PCM_WDT_LATCH_5 (SPM_BASE + 0x814)
353 #define PCM_WDT_LATCH_6 (SPM_BASE + 0x818)
354 #define PCM_WDT_LATCH_7 (SPM_BASE + 0x81C)
355 #define PCM_WDT_LATCH_8 (SPM_BASE + 0x820)
356 #define PCM_WDT_LATCH_9 (SPM_BASE + 0x824)
357 #define WDT_LATCH_SPARE0 (SPM_BASE + 0x828)
358 #define WDT_LATCH_SPARE1 (SPM_BASE + 0x82C)
359 #define WDT_LATCH_SPARE2 (SPM_BASE + 0x830)
360 #define WDT_LATCH_SPARE3 (SPM_BASE + 0x834)
361 #define PCM_WDT_LATCH_10 (SPM_BASE + 0x838)
362 #define PCM_WDT_LATCH_11 (SPM_BASE + 0x83C)
363 #define DCHA_GATING_LATCH_0 (SPM_BASE + 0x840)
364 #define DCHA_GATING_LATCH_1 (SPM_BASE + 0x844)
365 #define DCHA_GATING_LATCH_2 (SPM_BASE + 0x848)
366 #define DCHA_GATING_LATCH_3 (SPM_BASE + 0x84C)
367 #define DCHA_GATING_LATCH_4 (SPM_BASE + 0x850)
368 #define DCHA_GATING_LATCH_5 (SPM_BASE + 0x854)
369 #define DCHA_GATING_LATCH_6 (SPM_BASE + 0x858)
370 #define DCHA_GATING_LATCH_7 (SPM_BASE + 0x85C)
371 #define DCHB_GATING_LATCH_0 (SPM_BASE + 0x860)
372 #define DCHB_GATING_LATCH_1 (SPM_BASE + 0x864)
373 #define DCHB_GATING_LATCH_2 (SPM_BASE + 0x868)
374 #define DCHB_GATING_LATCH_3 (SPM_BASE + 0x86C)
375 #define DCHB_GATING_LATCH_4 (SPM_BASE + 0x870)
376 #define DCHB_GATING_LATCH_5 (SPM_BASE + 0x874)
377 #define DCHB_GATING_LATCH_6 (SPM_BASE + 0x878)
378 #define DCHB_GATING_LATCH_7 (SPM_BASE + 0x87C)
379 #define DCHA_LATCH_RSV0 (SPM_BASE + 0x880)
380 #define DCHB_LATCH_RSV0 (SPM_BASE + 0x884)
381 #define PCM_WDT_LATCH_12 (SPM_BASE + 0x888)
382 #define PCM_WDT_LATCH_13 (SPM_BASE + 0x88C)
383 #define SPM_PC_TRACE_CON (SPM_BASE + 0x8C0)
384 #define SPM_PC_TRACE_G0 (SPM_BASE + 0x8C4)
385 #define SPM_PC_TRACE_G1 (SPM_BASE + 0x8C8)
386 #define SPM_PC_TRACE_G2 (SPM_BASE + 0x8CC)
387 #define SPM_PC_TRACE_G3 (SPM_BASE + 0x8D0)
388 #define SPM_PC_TRACE_G4 (SPM_BASE + 0x8D4)
389 #define SPM_PC_TRACE_G5 (SPM_BASE + 0x8D8)
390 #define SPM_PC_TRACE_G6 (SPM_BASE + 0x8DC)
391 #define SPM_PC_TRACE_G7 (SPM_BASE + 0x8E0)
392 #define SPM_ACK_CHK_CON (SPM_BASE + 0x900)
393 #define SPM_ACK_CHK_PC (SPM_BASE + 0x904)
394 #define SPM_ACK_CHK_SEL (SPM_BASE + 0x908)
395 #define SPM_ACK_CHK_TIMER (SPM_BASE + 0x90C)
396 #define SPM_ACK_CHK_STA (SPM_BASE + 0x910)
397 #define SPM_ACK_CHK_LATCH (SPM_BASE + 0x914)
398 #define SPM_ACK_CHK_CON2 (SPM_BASE + 0x920)
399 #define SPM_ACK_CHK_PC2 (SPM_BASE + 0x924)
400 #define SPM_ACK_CHK_SEL2 (SPM_BASE + 0x928)
401 #define SPM_ACK_CHK_TIMER2 (SPM_BASE + 0x92C)
402 #define SPM_ACK_CHK_STA2 (SPM_BASE + 0x930)
403 #define SPM_ACK_CHK_LATCH2 (SPM_BASE + 0x934)
404 #define SPM_ACK_CHK_CON3 (SPM_BASE + 0x940)
405 #define SPM_ACK_CHK_PC3 (SPM_BASE + 0x944)
406 #define SPM_ACK_CHK_SEL3 (SPM_BASE + 0x948)
407 #define SPM_ACK_CHK_TIMER3 (SPM_BASE + 0x94C)
408 #define SPM_ACK_CHK_STA3 (SPM_BASE + 0x950)
409 #define SPM_ACK_CHK_LATCH3 (SPM_BASE + 0x954)
410 #define SPM_ACK_CHK_CON4 (SPM_BASE + 0x960)
411 #define SPM_ACK_CHK_PC4 (SPM_BASE + 0x964)
412 #define SPM_ACK_CHK_SEL4 (SPM_BASE + 0x968)
413 #define SPM_ACK_CHK_TIMER4 (SPM_BASE + 0x96C)
414 #define SPM_ACK_CHK_STA4 (SPM_BASE + 0x970)
415 #define SPM_ACK_CHK_LATCH4 (SPM_BASE + 0x974)