Lines Matching refs:SPM_BASE
23 #define SPM_POWERON_CONFIG_EN (SPM_BASE + 0x000)
29 #define SPM_PWR_STATUS (SPM_BASE + 0x180)
30 #define SPM_PWR_STATUS_2ND (SPM_BASE + 0x184)
32 #define SPM_BYPASS_SPMC (SPM_BASE + 0x2b4)
33 #define SPM_SPMC_DORMANT_ENABLE (SPM_BASE + 0x2b8)
35 #define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204)
36 #define SPM_MP0_CPU0_PWR_CON (SPM_BASE + 0x208)
37 #define SPM_MP0_CPU1_PWR_CON (SPM_BASE + 0x20C)
38 #define SPM_MP0_CPU2_PWR_CON (SPM_BASE + 0x210)
39 #define SPM_MP0_CPU3_PWR_CON (SPM_BASE + 0x214)
40 #define SPM_MP1_CPUTOP_PWR_CON (SPM_BASE + 0x218)
41 #define SPM_MP1_CPU0_PWR_CON (SPM_BASE + 0x21C)
42 #define SPM_MP1_CPU1_PWR_CON (SPM_BASE + 0x220)
43 #define SPM_MP1_CPU2_PWR_CON (SPM_BASE + 0x224)
44 #define SPM_MP1_CPU3_PWR_CON (SPM_BASE + 0x228)
45 #define SPM_MP0_CPUTOP_L2_PDN (SPM_BASE + 0x240)
46 #define SPM_MP0_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x244)
47 #define SPM_MP0_CPU0_L1_PDN (SPM_BASE + 0x248)
48 #define SPM_MP0_CPU1_L1_PDN (SPM_BASE + 0x24C)
49 #define SPM_MP0_CPU2_L1_PDN (SPM_BASE + 0x250)
50 #define SPM_MP0_CPU3_L1_PDN (SPM_BASE + 0x254)
51 #define SPM_MP1_CPUTOP_L2_PDN (SPM_BASE + 0x258)
52 #define SPM_MP1_CPUTOP_L2_SLEEP_B (SPM_BASE + 0x25C)
53 #define SPM_MP1_CPU0_L1_PDN (SPM_BASE + 0x260)
54 #define SPM_MP1_CPU1_L1_PDN (SPM_BASE + 0x264)
55 #define SPM_MP1_CPU2_L1_PDN (SPM_BASE + 0x268)
56 #define SPM_MP1_CPU3_L1_PDN (SPM_BASE + 0x26C)
58 #define SPM_CPU_EXT_BUCK_ISO (SPM_BASE + 0x290)