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Searched refs:PLAT_ARM_GICD_BASE (Results 1 – 25 of 32) sorted by relevance

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/trusted-firmware-a-latest/plat/arm/board/rdn2/
Drdn2_plat.c36 .rt_owner_base = PLAT_ARM_GICD_BASE,
40 PLAT_ARM_GICD_BASE >> 16,
42 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
45 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
48 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
52 {PLAT_ARM_GICD_BASE, 32, 511},
54 {PLAT_ARM_GICD_BASE, 512, 991},
57 {PLAT_ARM_GICD_BASE, 4096, 4575},
60 {PLAT_ARM_GICD_BASE, 4576, 5055},
/trusted-firmware-a-latest/plat/arm/board/rdv1mc/
Drdv1mc_plat.c32 .rt_owner_base = PLAT_ARM_GICD_BASE,
36 PLAT_ARM_GICD_BASE >> 16,
37 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
39 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
42 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
46 {PLAT_ARM_GICD_BASE, 32, 255},
/trusted-firmware-a-latest/plat/arm/board/rdn1edge/
Drdn1edge_plat.c22 .rt_owner_base = PLAT_ARM_GICD_BASE,
26 PLAT_ARM_GICD_BASE >> 16,
27 (PLAT_ARM_GICD_BASE + CSS_SGI_REMOTE_CHIP_MEM_OFFSET(1)) >> 16
30 {PLAT_ARM_GICD_BASE, 32, 255},
/trusted-firmware-a-latest/plat/arm/board/n1sdp/
Dn1sdp_bl31_setup.c47 .rt_owner_base = PLAT_ARM_GICD_BASE,
51 PLAT_ARM_GICD_BASE >> 16,
52 PLAT_ARM_GICD_BASE >> 16
55 {PLAT_ARM_GICD_BASE, 32, 511},
56 {PLAT_ARM_GICD_BASE, 512, 991}
/trusted-firmware-a-latest/services/spd/trusty/
Dgeneric-arm64-smcall.c15 #ifndef PLAT_ARM_GICD_BASE
17 #define PLAT_ARM_GICD_BASE GICD_BASE macro
23 #error PLAT_ARM_GICD_BASE or GICD_BASE must be defined
68 return PLAT_ARM_GICD_BASE; in trusty_get_reg_base()
/trusted-firmware-a-latest/include/plat/arm/css/common/aarch64/
Dcss_macros.S20 mov_imm x16, PLAT_ARM_GICD_BASE
/trusted-firmware-a-latest/plat/arm/board/rde1edge/include/
Dplatform_def.h44 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a-latest/plat/arm/board/sgi575/include/
Dplatform_def.h45 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a-latest/plat/arm/board/rdn1edge/include/
Dplatform_def.h50 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a-latest/plat/hisilicon/hikey/include/
Dplatform_def.h48 #define PLAT_ARM_GICD_BASE 0xF6801000 macro
Dplat_macros.S36 mov_imm x16, PLAT_ARM_GICD_BASE
/trusted-firmware-a-latest/plat/arm/common/
Darm_gicv2.c35 .gicd_base = PLAT_ARM_GICD_BASE,
Darm_gicv3.c83 .gicd_base = PLAT_ARM_GICD_BASE,
/trusted-firmware-a-latest/plat/arm/board/rdv1/include/
Dplatform_def.h64 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a-latest/plat/arm/board/rdv1mc/include/
Dplatform_def.h59 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a-latest/plat/arm/board/rdn2/include/
Dplatform_def.h87 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a-latest/plat/mediatek/mt8173/include/
Dplatform_def.h118 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE macro
/trusted-firmware-a-latest/plat/arm/board/fvp/
Dfvp_gicv3.c124 fvp_gic_data.gicd_base = PLAT_ARM_GICD_BASE; in plat_arm_gic_driver_init()
/trusted-firmware-a-latest/plat/hisilicon/hikey/
Dhikey_bl31_setup.c49 .gicd_base = PLAT_ARM_GICD_BASE,
/trusted-firmware-a-latest/plat/xilinx/zynqmp/include/
Dplatform_def.h125 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE macro
/trusted-firmware-a-latest/plat/arm/board/tc/include/
Dplatform_def.h265 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro
/trusted-firmware-a-latest/plat/arm/board/fvp_r/include/
Dplatform_def.h250 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE macro
/trusted-firmware-a-latest/plat/arm/board/corstone700/common/include/
Dplatform_def.h119 #define PLAT_ARM_GICD_BASE 0x1C010000 macro
/trusted-firmware-a-latest/include/plat/nuvoton/npcm845x/
Dplatform_def.h176 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE macro
/trusted-firmware-a-latest/plat/arm/board/morello/include/
Dplatform_def.h239 #define PLAT_ARM_GICD_BASE UL(0x30000000) macro

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