1 /* 2 * Copyright (c) 2014-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2018-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef PLATFORM_DEF_H 10 #define PLATFORM_DEF_H 11 12 #include <arch.h> 13 #include <common/interrupt_props.h> 14 #include <drivers/arm/gic_common.h> 15 #include <lib/utils_def.h> 16 17 #include "zynqmp_def.h" 18 19 /******************************************************************************* 20 * Generic platform constants 21 ******************************************************************************/ 22 23 /* Size of cacheable stacks */ 24 #ifndef PLATFORM_STACK_SIZE 25 #define PLATFORM_STACK_SIZE 0x440 26 #endif 27 28 #define PLATFORM_CORE_COUNT U(4) 29 #define PLAT_MAX_PWR_LVL U(1) 30 #define PLAT_MAX_RET_STATE U(1) 31 #define PLAT_MAX_OFF_STATE U(2) 32 33 /******************************************************************************* 34 * BL31 specific defines. 35 ******************************************************************************/ 36 /* 37 * Put BL31 at the top of the Trusted SRAM (just below the shared memory, if 38 * present). BL31_BASE is calculated using the current BL31 debug size plus a 39 * little space for growth. 40 */ 41 #ifndef ZYNQMP_ATF_MEM_BASE 42 #if !DEBUG && defined(SPD_none) && !SDEI_SUPPORT 43 # define BL31_BASE U(0xfffea000) 44 # define BL31_LIMIT U(0x100000000) 45 #else 46 # define BL31_BASE U(0x1000) 47 # define BL31_LIMIT U(0x80000) 48 #endif 49 #else 50 # define BL31_BASE U(ZYNQMP_ATF_MEM_BASE) 51 # define BL31_LIMIT (UL(ZYNQMP_ATF_MEM_BASE) + U(ZYNQMP_ATF_MEM_SIZE)) 52 # ifdef ZYNQMP_ATF_MEM_PROGBITS_SIZE 53 # define BL31_PROGBITS_LIMIT (UL(ZYNQMP_ATF_MEM_BASE) + U(ZYNQMP_ATF_MEM_PROGBITS_SIZE)) 54 # endif 55 #endif 56 57 /******************************************************************************* 58 * BL32 specific defines. 59 ******************************************************************************/ 60 #ifndef ZYNQMP_BL32_MEM_BASE 61 # define BL32_BASE U(0x60000000) 62 # define BL32_LIMIT U(0x80000000) 63 #else 64 # define BL32_BASE U(ZYNQMP_BL32_MEM_BASE) 65 # define BL32_LIMIT (UL(ZYNQMP_BL32_MEM_BASE) + U(ZYNQMP_BL32_MEM_SIZE)) 66 #endif 67 68 /******************************************************************************* 69 * BL33 specific defines. 70 ******************************************************************************/ 71 #ifndef PRELOADED_BL33_BASE 72 # define PLAT_ARM_NS_IMAGE_BASE U(0x8000000) 73 #else 74 # define PLAT_ARM_NS_IMAGE_BASE U(PRELOADED_BL33_BASE) 75 #endif 76 77 /******************************************************************************* 78 * TSP specific defines. 79 ******************************************************************************/ 80 #define TSP_SEC_MEM_BASE BL32_BASE 81 #define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE) 82 83 /* ID of the secure physical generic timer interrupt used by the TSP */ 84 #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER 85 86 /******************************************************************************* 87 * Platform specific page table and MMU setup constants 88 ******************************************************************************/ 89 #define XILINX_OF_BOARD_DTB_MAX_SIZE U(0x200000) 90 #define PLAT_DDR_LOWMEM_MAX U(0x80000000) 91 #define PLAT_OCM_BASE U(0xFFFC0000) 92 #define PLAT_OCM_LIMIT U(0xFFFFFFFF) 93 94 #define IS_TFA_IN_OCM(x) ((x >= PLAT_OCM_BASE) && (x < PLAT_OCM_LIMIT)) 95 96 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32) 97 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32) 98 99 #ifndef MAX_MMAP_REGIONS 100 #if (defined(XILINX_OF_BOARD_DTB_ADDR) && !IS_TFA_IN_OCM(BL31_BASE)) 101 #define MAX_MMAP_REGIONS 8 102 #else 103 #define MAX_MMAP_REGIONS 7 104 #endif 105 #endif 106 107 #ifndef MAX_XLAT_TABLES 108 #if !IS_TFA_IN_OCM(BL31_BASE) 109 #define MAX_XLAT_TABLES 8 110 #else 111 #define MAX_XLAT_TABLES 5 112 #endif 113 #endif 114 115 #define CACHE_WRITEBACK_SHIFT 6 116 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 117 118 #define ZYNQMP_SDEI_SGI_PRIVATE U(8) 119 120 /* Platform macros to support exception handling framework */ 121 #define PLAT_PRI_BITS U(3) 122 #define PLAT_SDEI_CRITICAL_PRI 0x10 123 #define PLAT_SDEI_NORMAL_PRI 0x20 124 125 #define PLAT_ARM_GICD_BASE BASE_GICD_BASE 126 #define PLAT_ARM_GICC_BASE BASE_GICC_BASE 127 /* 128 * Define properties of Group 1 Secure and Group 0 interrupts as per GICv3 129 * terminology. On a GICv2 system or mode, the lists will be merged and treated 130 * as Group 0 interrupts. 131 */ 132 #if !ZYNQMP_WDT_RESTART 133 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 134 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 135 GIC_INTR_CFG_LEVEL), \ 136 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 137 GIC_INTR_CFG_EDGE), \ 138 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 139 GIC_INTR_CFG_EDGE), \ 140 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 141 GIC_INTR_CFG_EDGE), \ 142 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 143 GIC_INTR_CFG_EDGE), \ 144 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 145 GIC_INTR_CFG_EDGE), \ 146 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 147 GIC_INTR_CFG_EDGE), \ 148 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 149 GIC_INTR_CFG_EDGE) 150 #else 151 #define PLAT_ARM_G1S_IRQ_PROPS(grp) \ 152 INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ 153 GIC_INTR_CFG_LEVEL), \ 154 INTR_PROP_DESC(IRQ_TTC3_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 155 GIC_INTR_CFG_EDGE), \ 156 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ 157 GIC_INTR_CFG_EDGE), \ 158 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ 159 GIC_INTR_CFG_EDGE), \ 160 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \ 161 GIC_INTR_CFG_EDGE), \ 162 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \ 163 GIC_INTR_CFG_EDGE), \ 164 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \ 165 GIC_INTR_CFG_EDGE), \ 166 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \ 167 GIC_INTR_CFG_EDGE), \ 168 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \ 169 GIC_INTR_CFG_EDGE) 170 #endif 171 172 #define PLAT_ARM_G0_IRQ_PROPS(grp) \ 173 INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, grp, \ 174 GIC_INTR_CFG_EDGE) 175 176 #endif /* PLATFORM_DEF_H */ 177
