Home
last modified time | relevance | path

Searched refs:MPIDR_AFFLVL0 (Results 1 – 25 of 51) sorted by relevance

123

/trusted-firmware-a-latest/plat/hisilicon/poplar/
Dplat_pm.c76 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in poplar_pwr_domain_on_finish()
120 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in poplar_validate_power_state()
122 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in poplar_validate_power_state()
147 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in poplar_get_sys_suspend_power_state()
/trusted-firmware-a-latest/plat/hisilicon/hikey/
Dhikey_pm.c24 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
167 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in hikey_get_sys_suspend_power_state()
232 if (pwr_lvl != MPIDR_AFFLVL0) in hikey_validate_power_state()
235 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey_validate_power_state()
238 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in hikey_validate_power_state()
/trusted-firmware-a-latest/plat/imx/common/
Dimx8_psci.c43 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in imx_validate_power_state()
58 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in imx_get_sys_suspend_power_state()
/trusted-firmware-a-latest/plat/renesas/common/
Dplat_pm.c37 #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0])
259 if (pwr_lvl != MPIDR_AFFLVL0) in rcar_validate_power_state()
262 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in rcar_validate_power_state()
264 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in rcar_validate_power_state()
283 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
290 for (i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in rcar_get_sys_suspend_power_state()
/trusted-firmware-a-latest/plat/hisilicon/hikey960/
Dhikey960_pm.c27 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
156 if (pwr_lvl != MPIDR_AFFLVL0) in hikey960_validate_power_state()
159 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in hikey960_validate_power_state()
162 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in hikey960_validate_power_state()
293 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in hikey960_get_sys_suspend_power_state()
/trusted-firmware-a-latest/plat/qemu/qemu_sbsa/
Dsbsa_pm.c62 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
65 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
183 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in qemu_pwr_domain_on_finish()
/trusted-firmware-a-latest/plat/rockchip/common/
Dplat_pm.c22 ((state)->pwr_domain_state[MPIDR_AFFLVL0])
150 if (pwr_lvl != MPIDR_AFFLVL0) in rockchip_validate_power_state()
153 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in rockchip_validate_power_state()
156 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in rockchip_validate_power_state()
176 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in rockchip_get_sys_suspend_power_state()
/trusted-firmware-a-latest/plat/qemu/common/
Dqemu_pm.c55 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
58 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
186 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in qemu_pwr_domain_on_finish()
/trusted-firmware-a-latest/plat/brcm/board/stingray/src/
Dbrcm_pm_ops.c29 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
362 if (pwr_lvl != MPIDR_AFFLVL0) in brcm_validate_power_state()
365 req_state->pwr_domain_state[MPIDR_AFFLVL0] = in brcm_validate_power_state()
368 for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++) in brcm_validate_power_state()
Dpm.c63 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in brcm_pwr_domain_on_finish()
/trusted-firmware-a-latest/plat/nuvoton/npcm845x/
Dnpcm845x_psci.c57 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
65 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
193 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in npcm845x_pwr_domain_on_finish()
215 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in npcm845x_pwr_domain_suspend_finish()
/trusted-firmware-a-latest/plat/rpi/common/
Drpi3_pm.c53 MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
56 MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
159 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in rpi3_pwr_domain_on_finish()
/trusted-firmware-a-latest/plat/xilinx/versal_net/
Dplat_psci_pm.c208 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_net_validate_power_state()
210 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_net_validate_power_state()
231 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) in versal_net_get_sys_suspend_power_state()
/trusted-firmware-a-latest/plat/amlogic/axg/
Daxg_pm.c102 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_on_finish()
117 assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] == in axg_pwr_domain_off()
/trusted-firmware-a-latest/plat/imx/imx8m/include/
Dimx8m_psci.h10 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
/trusted-firmware-a-latest/plat/imx/imx8qm/include/
Dplatform_def.h26 #define IMX_PWR_LVL0 MPIDR_AFFLVL0
/trusted-firmware-a-latest/plat/xilinx/versal/
Dplat_psci.c207 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in versal_validate_power_state()
209 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in versal_validate_power_state()
/trusted-firmware-a-latest/plat/xilinx/zynqmp/
Dplat_psci.c186 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_RET_STATE; in zynqmp_validate_power_state()
188 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PLAT_MAX_OFF_STATE; in zynqmp_validate_power_state()
/trusted-firmware-a-latest/plat/qti/sc7180/inc/
Dplatform_def.h31 #define QTI_PWR_LVL0 MPIDR_AFFLVL0
/trusted-firmware-a-latest/plat/qti/sc7280/inc/
Dplatform_def.h31 #define QTI_PWR_LVL0 MPIDR_AFFLVL0
/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t210/
Dplat_psci_handlers.c55 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id & 0xff; in tegra_soc_validate_power_state()
64 req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; in tegra_soc_validate_power_state()
81 for (uint32_t i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++) in tegra_soc_validate_power_state()
201 unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; in tegra_soc_pwr_domain_suspend()
/trusted-firmware-a-latest/plat/ti/k3/common/
Dk3_psci.c20 #define CORE_PWR_STATE(state) ((state)->pwr_domain_state[MPIDR_AFFLVL0])
264 for (i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++) { in k3_get_sys_suspend_power_state()
/trusted-firmware-a-latest/include/plat/marvell/armada/a3k/common/
Dmarvell_def.h35 #define MARVELL_PWR_LVL0 MPIDR_AFFLVL0
/trusted-firmware-a-latest/plat/nvidia/tegra/soc/t186/
Dplat_psci_handlers.c81 req_state->pwr_domain_state[MPIDR_AFFLVL0] = state_id; in tegra_soc_validate_power_state()
113 stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] & in tegra_soc_pwr_domain_suspend()
373 uint8_t stateid_afflvl0 = target_state->pwr_domain_state[MPIDR_AFFLVL0]; in tegra_soc_pwr_domain_on_finish()
/trusted-firmware-a-latest/include/plat/marvell/armada/a8k/common/
Dmarvell_def.h32 #define MARVELL_PWR_LVL0 MPIDR_AFFLVL0

123