| /trusted-firmware-a-3.4.0/drivers/nxp/ddr/phy-gen2/ |
| D | phy.c | 70 static inline uint16_t *phy_io_addr(void *phy, uint32_t addr) in phy_io_addr() argument
72 return phy + (map_phy_addr_space(addr) << 2); in phy_io_addr()
75 static inline void phy_io_write16(uint16_t *phy, uint32_t addr, uint16_t data) in phy_io_write16() argument
77 mmio_write_16((uintptr_t)phy_io_addr(phy, addr), data); in phy_io_write16()
83 static inline uint16_t phy_io_read16(uint16_t *phy, uint32_t addr) in phy_io_read16() argument
85 uint16_t reg = mmio_read_16((uintptr_t) phy_io_addr(phy, addr)); in phy_io_read16()
99 static void read_phy_reg(uint16_t *phy, uint32_t addr, in read_phy_reg() argument
105 buf[i] = phy_io_read16(phy, (addr + i)); in read_phy_reg()
148 uint16_t *phy; in get_cdd_val() local
157 phy = phy_ptr[i]; in get_cdd_val()
[all …]
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| /trusted-firmware-a-3.4.0/plat/brcm/board/stingray/driver/ |
| D | usb_phy.c | 278 usb_phy_t *phy = phy_port->p; in u3h_u2drd_phy_reset() local
282 mmio_clrbits_32(phy->usb3hreg + USB3H_U2PHY_CTRL, in u3h_u2drd_phy_reset()
284 mmio_setbits_32(phy->usb3hreg + USB3H_U2PHY_CTRL, in u3h_u2drd_phy_reset()
288 mmio_clrbits_32(phy->drdu2reg + DRDU2_PHY_CTRL, in u3h_u2drd_phy_reset()
290 mmio_setbits_32(phy->drdu2reg + DRDU2_PHY_CTRL, in u3h_u2drd_phy_reset()
298 usb_phy_t *phy = phy_port->p; in u3drd_phy_reset() local
301 mmio_clrbits_32(phy->drdu3reg + DRDU3_U2PHY_CTRL, in u3drd_phy_reset()
303 mmio_setbits_32(phy->drdu3reg + DRDU3_U2PHY_CTRL, in u3drd_phy_reset()
310 usb_phy_t *phy = phy_port->p; in u3h_u2drd_phy_power_on() local
315 mmio_clrbits_32(phy->usb3hreg + USB3H_PHY_PWR_CTRL, in u3h_u2drd_phy_power_on()
[all …]
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| /trusted-firmware-a-3.4.0/plat/rockchip/rk3368/drivers/ddr/ |
| D | ddr_rk3368.c | 169 struct DDRPHY_SAVE_REG_TAG phy; member
315 p_ddr_reg->phy.PHY_REG0 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG0); in ddr_reg_save()
316 p_ddr_reg->phy.PHY_REG1 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG1); in ddr_reg_save()
317 p_ddr_reg->phy.PHY_REGB = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGB); in ddr_reg_save()
318 p_ddr_reg->phy.PHY_REGC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGC); in ddr_reg_save()
319 p_ddr_reg->phy.PHY_REG11 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG11); in ddr_reg_save()
320 p_ddr_reg->phy.PHY_REG13 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG13); in ddr_reg_save()
321 p_ddr_reg->phy.PHY_REG14 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG14); in ddr_reg_save()
322 p_ddr_reg->phy.PHY_REG16 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG16); in ddr_reg_save()
323 p_ddr_reg->phy.PHY_REG20 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG20); in ddr_reg_save()
[all …]
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| /trusted-firmware-a-3.4.0/fdts/ |
| D | stm32mp15xx-dhcom-pdk2.dtsi | 28 phy-names = "usb2-phy";
39 phy-supply = <&vdd_usb>;
43 phy-supply = <&vdd_usb>;
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| D | stm32mp15-ddr.dtsi | 86 st,phy-reg = <
100 st,phy-timing = <
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| D | corstone700_fpga.dts | 17 phy-mode = "mii";
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| D | corstone700_fvp.dts | 30 phy-mode = "mii";
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| D | stm32mp15xx-dkx.dtsi | 332 phy-names = "usb2-phy";
342 phy-supply = <&vdd_usb>;
346 phy-supply = <&vdd_usb>;
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| D | stm32mp13-ddr.dtsi | 80 st,phy-reg = <
92 st,phy-timing = <
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| D | stm32mp131.dtsi | 413 usbphyc_port0: usb-phy@0 {
414 #phy-cells = <0>;
418 usbphyc_port1: usb-phy@1 {
419 #phy-cells = <1>;
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| /trusted-firmware-a-3.4.0/drivers/st/ddr/ |
| D | stm32mp1_ddr.c | 214 static void stm32mp1_ddrphy_idone_wait(struct stm32mp_ddrphy *phy) in stm32mp1_ddrphy_idone_wait() argument
221 pgsr = mmio_read_32((uintptr_t)&phy->pgsr); in stm32mp1_ddrphy_idone_wait()
224 (uintptr_t)&phy->pgsr, pgsr); in stm32mp1_ddrphy_idone_wait()
256 (uintptr_t)&phy->pgsr, pgsr); in stm32mp1_ddrphy_idone_wait()
259 static void stm32mp1_ddrphy_init(struct stm32mp_ddrphy *phy, uint32_t pir) in stm32mp1_ddrphy_init() argument
263 mmio_write_32((uintptr_t)&phy->pir, pir_init); in stm32mp1_ddrphy_init()
265 (uintptr_t)&phy->pir, pir_init, in stm32mp1_ddrphy_init()
266 mmio_read_32((uintptr_t)&phy->pir)); in stm32mp1_ddrphy_init()
272 stm32mp1_ddrphy_idone_wait(phy); in stm32mp1_ddrphy_init()
382 uint32_t mr1 = mmio_read_32((uintptr_t)&priv->phy->mr1); in stm32mp1_ddr3_dll_off()
[all …]
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| D | stm32mp1_ram.c | 143 priv->phy = (struct stm32mp_ddrphy *)stm32mp_ddrphyc_base(); in stm32mp1_ddr_probe()
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| D | stm32mp_ddr.c | 21 return (uintptr_t)priv->phy; in get_base_addr()
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| /trusted-firmware-a-3.4.0/drivers/nxp/ddr/nxp-ddr/ |
| D | ddr.mk | 9 PLAT_DDR_PHY_DIR := phy-gen2
29 PLAT_DDR_PHY_DIR := phy-gen1
78 $(PLAT_DRIVERS_PATH)/ddr/$(PLAT_DDR_PHY_DIR)/phy.c
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| D | utility.c | 147 priv->phy[0] = priv->phy[0]; in disable_unused_ddrc()
148 priv->phy[1] = NULL; in disable_unused_ddrc()
154 priv->phy[1] = NULL; in disable_unused_ddrc()
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| /trusted-firmware-a-3.4.0/docs/plat/marvell/armada/ |
| D | porting.rst | 101 Comphy Porting (phy-porting-layer.h or phy-default-porting-layer.h)
124 ``drivers/marvell/comphy/phy-default-porting-layer.h`` which contains the
126 phy-porting-layer.h file under: ``plat/marvell/armada/<soc
127 family>/<platform>/board/phy-porting-layer.h``. If the phy-porting-layer.h
128 exists, the phy-default-porting-layer.h is not going to be included.
138 …``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h`` "plat/marvell/armada/<soc family>/<pla…
148 ``plat/marvell/armada/a8k/a80x0/board/phy-porting-layer.h``
152 phy-porting-layer.h), the default values are used
153 (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is
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| /trusted-firmware-a-3.4.0/include/drivers/st/ |
| D | stm32mp_ddr.h | 49 struct stm32mp_ddrphy *phy; member
|
| /trusted-firmware-a-3.4.0/plat/nxp/soc-lx2160a/lx2160ardb/ |
| D | ddr_init.c | 188 info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; in init_ddr()
189 info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; in init_ddr()
|
| /trusted-firmware-a-3.4.0/include/drivers/nxp/ddr/ |
| D | ddr.h | 98 uint16_t *phy[MAX_DDRC_NUM]; member
|
| /trusted-firmware-a-3.4.0/plat/nxp/soc-lx2160a/ |
| D | ddr_fip.mk | 7 DDR_PHY_BIN_PATH ?= ./ddr-phy-binary/lx2160a
|
| /trusted-firmware-a-3.4.0/plat/nxp/soc-lx2160a/lx2160aqds/ |
| D | ddr_init.c | 323 info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; in init_ddr()
324 info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; in init_ddr()
|
| /trusted-firmware-a-3.4.0/plat/nxp/soc-lx2160a/lx2162aqds/ |
| D | ddr_init.c | 323 info.phy[0] = (void *)NXP_DDR_PHY1_ADDR; in init_ddr()
324 info.phy[1] = (void *)NXP_DDR_PHY2_ADDR; in init_ddr()
|
| /trusted-firmware-a-3.4.0/plat/nxp/soc-ls1043a/ |
| D | soc.def | 40 # ddr phy - set to NXP or SNPS
|
| /trusted-firmware-a-3.4.0/plat/nxp/soc-ls1046a/ |
| D | soc.def | 40 # ddr phy - set to NXP or SNPS
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| /trusted-firmware-a-3.4.0/plat/rockchip/rk3399/drivers/dram/ |
| D | suspend.c | 126 uint32_t phy) in rkclk_ddr_reset() argument
130 phy &= 0x1; in rkclk_ddr_reset()
133 CRU_SFTRST_DDR_PHY(channel, phy)); in rkclk_ddr_reset()
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