1#
2# Copyright 2021-2022 NXP
3#
4# SPDX-License-Identifier: BSD-3-Clause
5#
6
7ifeq ($(PLAT_DDR_PHY), PHY_GEN2)
8$(eval $(call add_define, PHY_GEN2))
9PLAT_DDR_PHY_DIR		:= phy-gen2
10ifeq (${APPLY_MAX_CDD},yes)
11$(eval $(call add_define,NXP_APPLY_MAX_CDD))
12endif
13
14ifeq (${ERRATA_DDR_A011396}, 1)
15$(eval $(call add_define,ERRATA_DDR_A011396))
16endif
17
18ifeq (${ERRATA_DDR_A050450}, 1)
19$(eval $(call add_define,ERRATA_DDR_A050450))
20endif
21
22ifeq (${ERRATA_DDR_A050958}, 1)
23$(eval $(call add_define,ERRATA_DDR_A050958))
24endif
25
26endif
27
28ifeq ($(PLAT_DDR_PHY), PHY_GEN1)
29PLAT_DDR_PHY_DIR		:= phy-gen1
30
31ifeq (${ERRATA_DDR_A008511},1)
32$(eval $(call add_define,ERRATA_DDR_A008511))
33endif
34
35ifeq (${ERRATA_DDR_A009803},1)
36$(eval $(call add_define,ERRATA_DDR_A009803))
37endif
38
39ifeq (${ERRATA_DDR_A009942},1)
40$(eval $(call add_define,ERRATA_DDR_A009942))
41endif
42
43ifeq (${ERRATA_DDR_A010165},1)
44$(eval $(call add_define,ERRATA_DDR_A010165))
45endif
46
47endif
48
49ifeq ($(DDR_BIST), yes)
50$(eval $(call add_define, BIST_EN))
51endif
52
53ifeq ($(DDR_DEBUG), yes)
54$(eval $(call add_define, DDR_DEBUG))
55endif
56
57ifeq ($(DDR_PHY_DEBUG), yes)
58$(eval $(call add_define, DDR_PHY_DEBUG))
59endif
60
61ifeq ($(DEBUG_PHY_IO), yes)
62$(eval $(call add_define, DEBUG_PHY_IO))
63endif
64
65ifeq ($(DEBUG_WARM_RESET), yes)
66$(eval $(call add_define, DEBUG_WARM_RESET))
67endif
68
69ifeq ($(DEBUG_DDR_INPUT_CONFIG), yes)
70$(eval $(call add_define, DEBUG_DDR_INPUT_CONFIG))
71endif
72
73DDR_CNTLR_SOURCES	:= $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/ddr.c \
74			   $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/ddrc.c \
75			   $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/dimm.c \
76			   $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/regs.c \
77			   $(PLAT_DRIVERS_PATH)/ddr/nxp-ddr/utility.c \
78			   $(PLAT_DRIVERS_PATH)/ddr/$(PLAT_DDR_PHY_DIR)/phy.c
79
80PLAT_INCLUDES		+= -I$(PLAT_DRIVERS_INCLUDE_PATH)/ddr
81