1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
4 * Author: Alexandre Torgue <alexandre.torgue@st.com> for STMicroelectronics.
5 */
6
7#include <dt-bindings/clock/stm32mp1-clksrc.h>
8#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
9
10/ {
11	memory@c0000000 {
12		device_type = "memory";
13		reg = <0xc0000000 0x20000000>;
14	};
15
16	vin: vin {
17		compatible = "regulator-fixed";
18		regulator-name = "vin";
19		regulator-min-microvolt = <5000000>;
20		regulator-max-microvolt = <5000000>;
21		regulator-always-on;
22	};
23};
24
25&bsec {
26	board_id: board_id@ec {
27		reg = <0xec 0x4>;
28		st,non-secure-otp;
29	};
30};
31
32&clk_hse {
33	st,digbypass;
34};
35
36&cpu0 {
37	cpu-supply = <&vddcore>;
38};
39
40&cpu1 {
41	cpu-supply = <&vddcore>;
42};
43
44&hash1 {
45	status = "okay";
46};
47
48&i2c4 {
49	pinctrl-names = "default";
50	pinctrl-0 = <&i2c4_pins_a>;
51	i2c-scl-rising-time-ns = <185>;
52	i2c-scl-falling-time-ns = <20>;
53	clock-frequency = <400000>;
54	status = "okay";
55
56	pmic: stpmic@33 {
57		compatible = "st,stpmic1";
58		reg = <0x33>;
59		interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>;
60		interrupt-controller;
61		#interrupt-cells = <2>;
62		status = "okay";
63
64		regulators {
65			compatible = "st,stpmic1-regulators";
66			buck1-supply = <&vin>;
67			buck2-supply = <&vin>;
68			buck3-supply = <&vin>;
69			buck4-supply = <&vin>;
70			ldo1-supply = <&v3v3>;
71			ldo2-supply = <&vin>;
72			ldo3-supply = <&vdd_ddr>;
73			ldo4-supply = <&vin>;
74			ldo5-supply = <&vin>;
75			ldo6-supply = <&v3v3>;
76			vref_ddr-supply = <&vin>;
77			boost-supply = <&vin>;
78			pwr_sw1-supply = <&bst_out>;
79			pwr_sw2-supply = <&bst_out>;
80
81			vddcore: buck1 {
82				regulator-name = "vddcore";
83				regulator-min-microvolt = <1200000>;
84				regulator-max-microvolt = <1350000>;
85				regulator-always-on;
86				regulator-initial-mode = <0>;
87				regulator-over-current-protection;
88			};
89
90			vdd_ddr: buck2 {
91				regulator-name = "vdd_ddr";
92				regulator-min-microvolt = <1350000>;
93				regulator-max-microvolt = <1350000>;
94				regulator-always-on;
95				regulator-initial-mode = <0>;
96				regulator-over-current-protection;
97			};
98
99			vdd: buck3 {
100				regulator-name = "vdd";
101				regulator-min-microvolt = <3300000>;
102				regulator-max-microvolt = <3300000>;
103				regulator-always-on;
104				st,mask-reset;
105				regulator-initial-mode = <0>;
106				regulator-over-current-protection;
107			};
108
109			v3v3: buck4 {
110				regulator-name = "v3v3";
111				regulator-min-microvolt = <3300000>;
112				regulator-max-microvolt = <3300000>;
113				regulator-always-on;
114				regulator-over-current-protection;
115				regulator-initial-mode = <0>;
116			};
117
118			v1v8_audio: ldo1 {
119				regulator-name = "v1v8_audio";
120				regulator-min-microvolt = <1800000>;
121				regulator-max-microvolt = <1800000>;
122				regulator-always-on;
123			};
124
125			v3v3_hdmi: ldo2 {
126				regulator-name = "v3v3_hdmi";
127				regulator-min-microvolt = <3300000>;
128				regulator-max-microvolt = <3300000>;
129				regulator-always-on;
130			};
131
132			vtt_ddr: ldo3 {
133				regulator-name = "vtt_ddr";
134				regulator-always-on;
135				regulator-over-current-protection;
136				st,regulator-sink-source;
137			};
138
139			vdd_usb: ldo4 {
140				regulator-name = "vdd_usb";
141				regulator-min-microvolt = <3300000>;
142				regulator-max-microvolt = <3300000>;
143			};
144
145			vdda: ldo5 {
146				regulator-name = "vdda";
147				regulator-min-microvolt = <2900000>;
148				regulator-max-microvolt = <2900000>;
149				regulator-boot-on;
150			};
151
152			v1v2_hdmi: ldo6 {
153				regulator-name = "v1v2_hdmi";
154				regulator-min-microvolt = <1200000>;
155				regulator-max-microvolt = <1200000>;
156				regulator-always-on;
157			};
158
159			vref_ddr: vref_ddr {
160				regulator-name = "vref_ddr";
161				regulator-always-on;
162			};
163
164			bst_out: boost {
165				regulator-name = "bst_out";
166			};
167
168			vbus_otg: pwr_sw1 {
169				regulator-name = "vbus_otg";
170			};
171
172			vbus_sw: pwr_sw2 {
173				regulator-name = "vbus_sw";
174				regulator-active-discharge = <1>;
175			};
176		};
177	};
178};
179
180&iwdg2 {
181	timeout-sec = <32>;
182	status = "okay";
183	secure-status = "okay";
184};
185
186&pwr_regulators {
187	vdd-supply = <&vdd>;
188	vdd_3v3_usbfs-supply = <&vdd_usb>;
189};
190
191&rcc {
192	secure-status = "disabled";
193	st,clksrc = <
194		CLK_MPU_PLL1P
195		CLK_AXI_PLL2P
196		CLK_MCU_PLL3P
197		CLK_PLL12_HSE
198		CLK_PLL3_HSE
199		CLK_PLL4_HSE
200		CLK_RTC_LSE
201		CLK_MCO1_DISABLED
202		CLK_MCO2_DISABLED
203	>;
204
205	st,clkdiv = <
206		1 /*MPU*/
207		0 /*AXI*/
208		0 /*MCU*/
209		1 /*APB1*/
210		1 /*APB2*/
211		1 /*APB3*/
212		1 /*APB4*/
213		2 /*APB5*/
214		23 /*RTC*/
215		0 /*MCO1*/
216		0 /*MCO2*/
217	>;
218
219	st,pkcs = <
220		CLK_CKPER_HSE
221		CLK_FMC_ACLK
222		CLK_QSPI_ACLK
223		CLK_ETH_PLL4P
224		CLK_SDMMC12_PLL4P
225		CLK_DSI_DSIPLL
226		CLK_STGEN_HSE
227		CLK_USBPHY_HSE
228		CLK_SPI2S1_PLL3Q
229		CLK_SPI2S23_PLL3Q
230		CLK_SPI45_HSI
231		CLK_SPI6_HSI
232		CLK_I2C46_HSI
233		CLK_SDMMC3_PLL4P
234		CLK_USBO_USBPHY
235		CLK_ADC_CKPER
236		CLK_CEC_LSE
237		CLK_I2C12_HSI
238		CLK_I2C35_HSI
239		CLK_UART1_HSI
240		CLK_UART24_HSI
241		CLK_UART35_HSI
242		CLK_UART6_HSI
243		CLK_UART78_HSI
244		CLK_SPDIF_PLL4P
245		CLK_FDCAN_PLL4R
246		CLK_SAI1_PLL3Q
247		CLK_SAI2_PLL3Q
248		CLK_SAI3_PLL3Q
249		CLK_SAI4_PLL3Q
250		CLK_RNG1_LSI
251		CLK_RNG2_LSI
252		CLK_LPTIM1_PCLK1
253		CLK_LPTIM23_PCLK3
254		CLK_LPTIM45_LSE
255	>;
256
257	/* VCO = 1300.0 MHz => P = 650 (CPU) */
258	pll1: st,pll@0 {
259		compatible = "st,stm32mp1-pll";
260		reg = <0>;
261		cfg = < 2 80 0 0 0 PQR(1,0,0) >;
262		frac = < 0x800 >;
263	};
264
265	/* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
266	pll2: st,pll@1 {
267		compatible = "st,stm32mp1-pll";
268		reg = <1>;
269		cfg = <2 65 1 0 0 PQR(1,1,1)>;
270		frac = <0x1400>;
271	};
272
273	/* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
274	pll3: st,pll@2 {
275		compatible = "st,stm32mp1-pll";
276		reg = <2>;
277		cfg = <1 33 1 16 36 PQR(1,1,1)>;
278		frac = <0x1a04>;
279	};
280
281	/* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
282	pll4: st,pll@3 {
283		compatible = "st,stm32mp1-pll";
284		reg = <3>;
285		cfg = <3 98 5 7 7 PQR(1,1,1)>;
286	};
287};
288
289&rng1 {
290	status = "okay";
291};
292
293&rtc {
294	status = "okay";
295};
296
297&sdmmc1 {
298	pinctrl-names = "default";
299	pinctrl-0 = <&sdmmc1_b4_pins_a>;
300	disable-wp;
301	st,neg-edge;
302	bus-width = <4>;
303	vmmc-supply = <&v3v3>;
304	status = "okay";
305};
306
307&timers15 {
308	secure-status = "okay";
309};
310
311&uart4 {
312	pinctrl-names = "default";
313	pinctrl-0 = <&uart4_pins_a>;
314	status = "okay";
315};
316
317&uart7 {
318	pinctrl-names = "default";
319	pinctrl-0 = <&uart7_pins_c>;
320	status = "disabled";
321};
322
323&usart3 {
324	pinctrl-names = "default";
325	pinctrl-0 = <&usart3_pins_c>;
326	uart-has-rtscts;
327	status = "disabled";
328};
329
330&usbotg_hs {
331	phys = <&usbphyc_port1 0>;
332	phy-names = "usb2-phy";
333	usb-role-switch;
334	status = "okay";
335};
336
337&usbphyc {
338	status = "okay";
339};
340
341&usbphyc_port0 {
342	phy-supply = <&vdd_usb>;
343};
344
345&usbphyc_port1 {
346	phy-supply = <&vdd_usb>;
347};
348