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Searched refs:RTS (Results 1 – 25 of 67) sorted by relevance

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/Zephyr-latest/drivers/pinctrl/
DKconfig.realtek_rts59127 bool "Pin controller driver for REALTEK RTS MCUs"
11 Enable pin controller driver for REALTEK RTS MCUs
/Zephyr-latest/drivers/serial/
DKconfig.intel_lw21 bool "Auto set RTS signal during poll out"
24 Assert RTS before polling out a character,
25 and deassert RTS after the character is polled out.
DKconfig.mec523 such as CTS and RTS.
DKconfig.xec23 such as CTS and RTS.
DKconfig.altera24 …The receiver will deassert RTS as soon as a byte is received and reassert after the byte is fetche…
DKconfig.ns1655022 such as CTS and RTS.
/Zephyr-latest/samples/net/sockets/echo_client/boards/
Dmimxrt1020_evk.overlay13 * nRF21540 (P6) P0.07 CTS -> IMXRT1020-EVK (J19) D8 (GPIO B1 07) (RTS)
15 * nRF21540 (P6) P0.05 RTS -> IMXRT1020-EVK (J17) D7 (GPIO B1 06) (CTS)
45 * As SPINEL UART's implementation required CTS/RTS flow control -
/Zephyr-latest/boards/shields/arduino_uno_click/boards/
Dnrf9160dk_nrf9160_arduino_uno_click_common.dtsi30 * The default pin group for the nRF9160 DK includes RTS/CTS HW flow
33 * on the same pins, but just removes RTS/CTS from the pin groups.
/Zephyr-latest/boards/antmicro/myra_sip_baseboard/support/
Dopenocd_myra_sip_baseboard.cfg5 ft232r tck_num RTS
/Zephyr-latest/boards/nuvoton/numaker_m2l31ki/
Dnumaker_m2l31ki-pinctrl.dtsi17 /* TX/RX/RTS/CTS/RST --> D1/D0/A2/A3/D2 --> PB3/PB2/PB8/PB9/PC9 */
/Zephyr-latest/tests/drivers/uart/uart_elementary/
DREADME.txt6 For single uart configuration - UART0 TX connected to RX and CTS to RTS
/Zephyr-latest/boards/nuvoton/numaker_pfm_m467/
Dnumaker_pfm_m467-pinctrl.dtsi17 /* TX/RX/RTS/CTS/RST --> D1/D0/A2/A3/D2 --> PB3/PB2/PB8/PB9/PC9 */
/Zephyr-latest/tests/drivers/uart/uart_mix_fifo_poll/
DREADME.txt15 Test requires that two pairs of pins are shortened: TX with RX and CTS with RTS.
/Zephyr-latest/samples/boards/espressif/light_sleep/
DREADME.rst69 check DTR/RTS configuration in the serial monitor. This is not necessary for
70 IDF monitor, but for other tools it might be necessary to set DTR and RTS line
/Zephyr-latest/boards/cypress/cy8ckit_062_ble/
Dcy8ckit_062_ble_common.dtsi46 <8 0 &gpio_prt5 2 0>, /* D2-RTS-5 */
/Zephyr-latest/boards/infineon/cy8ckit_062s4/
Dcy8ckit_062s4.dts45 <8 0 &gpio_prt5 0 0>, /* D2-RTS-5 */
/Zephyr-latest/boards/witte/linum/doc/
Dindex.rst29 - 2 On-board RS232 Transceiver with RTS/CTS
92 RTS PD4
101 RTS PD12
/Zephyr-latest/boards/gardena/sgrm/doc/
Dindex.rst39 | PB0.2 | RTS (O) | |
/Zephyr-latest/boards/waveshare/nrf51_ble400/doc/
Dindex.rst146 * RTS = P0.12
154 * RTS = P0.10
/Zephyr-latest/boards/silabs/dev_kits/sim3u1xx_dk/doc/
Dindex.rst55 | PB1.14 | RTS (O) | |
/Zephyr-latest/soc/espressif/common/
DKconfig.esptool186 Automatic resetting depends on the RTS & DTR signals being
207 Automatic resetting depends on the RTS & DTR signals being
/Zephyr-latest/boards/shields/sparkfun_carrier_asset_tracker/doc/
Dindex.rst40 | micromod_1_uart alias | UART 1 (with CTS and RTS pins) |
/Zephyr-latest/boards/particle/boron/doc/
Dindex.rst87 * UARTE0 enabled RX/TX on labeled header (UART1); add RTS/CTS with overlay
/Zephyr-latest/boards/particle/argon/doc/
Dindex.rst91 * UARTE0 enabled RX/TX on labeled header (UART1); add RTS/CTS with overlay
/Zephyr-latest/boards/particle/xenon/doc/
Dindex.rst92 * UARTE0 enabled RX/TX on labeled header (UART1); add RTS/CTS with overlay

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