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Searched refs:reg (Results 1 – 25 of 70) sorted by relevance

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/loramac-node-latest/src/boards/mcu/saml21/hri/
Dhri_evsys_l21.h72 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; in hri_evsys_set_INTEN_OVR0_bit()
77 return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR0) >> EVSYS_INTENSET_OVR0_Pos; in hri_evsys_get_INTEN_OVR0_bit()
83 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; in hri_evsys_write_INTEN_OVR0_bit()
85 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR0; in hri_evsys_write_INTEN_OVR0_bit()
91 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR0; in hri_evsys_clear_INTEN_OVR0_bit()
96 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; in hri_evsys_set_INTEN_OVR1_bit()
101 return (((Evsys *)hw)->INTENSET.reg & EVSYS_INTENSET_OVR1) >> EVSYS_INTENSET_OVR1_Pos; in hri_evsys_get_INTEN_OVR1_bit()
107 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; in hri_evsys_write_INTEN_OVR1_bit()
109 ((Evsys *)hw)->INTENSET.reg = EVSYS_INTENSET_OVR1; in hri_evsys_write_INTEN_OVR1_bit()
115 ((Evsys *)hw)->INTENCLR.reg = EVSYS_INTENSET_OVR1; in hri_evsys_clear_INTEN_OVR1_bit()
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Dhri_pac_l21.h79 ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; in hri_pac_set_INTEN_ERR_bit()
84 return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; in hri_pac_get_INTEN_ERR_bit()
90 ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; in hri_pac_write_INTEN_ERR_bit()
92 ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; in hri_pac_write_INTEN_ERR_bit()
98 ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; in hri_pac_clear_INTEN_ERR_bit()
103 ((Pac *)hw)->INTENSET.reg = mask; in hri_pac_set_INTEN_reg()
109 tmp = ((Pac *)hw)->INTENSET.reg; in hri_pac_get_INTEN_reg()
116 return ((Pac *)hw)->INTENSET.reg; in hri_pac_read_INTEN_reg()
121 ((Pac *)hw)->INTENSET.reg = data; in hri_pac_write_INTEN_reg()
122 ((Pac *)hw)->INTENCLR.reg = ~data; in hri_pac_write_INTEN_reg()
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Dhri_oscctrl_l21.h80 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_set_INTEN_XOSCRDY_bit()
85 return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY) >> OSCCTRL_INTENSET_XOSCRDY_Pos; in hri_oscctrl_get_INTEN_XOSCRDY_bit()
91 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_write_INTEN_XOSCRDY_bit()
93 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_write_INTEN_XOSCRDY_bit()
99 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY; in hri_oscctrl_clear_INTEN_XOSCRDY_bit()
104 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; in hri_oscctrl_set_INTEN_OSC16MRDY_bit()
109 …return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_OSC16MRDY) >> OSCCTRL_INTENSET_OSC16MRDY_… in hri_oscctrl_get_INTEN_OSC16MRDY_bit()
115 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; in hri_oscctrl_write_INTEN_OSC16MRDY_bit()
117 ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_OSC16MRDY; in hri_oscctrl_write_INTEN_OSC16MRDY_bit()
123 ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_OSC16MRDY; in hri_oscctrl_clear_INTEN_OSC16MRDY_bit()
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Dhri_supc_l21.h75 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_set_INTEN_BOD33RDY_bit()
80 return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; in hri_supc_get_INTEN_BOD33RDY_bit()
86 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_write_INTEN_BOD33RDY_bit()
88 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_write_INTEN_BOD33RDY_bit()
94 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; in hri_supc_clear_INTEN_BOD33RDY_bit()
99 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; in hri_supc_set_INTEN_BOD33DET_bit()
104 return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; in hri_supc_get_INTEN_BOD33DET_bit()
110 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; in hri_supc_write_INTEN_BOD33DET_bit()
112 ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; in hri_supc_write_INTEN_BOD33DET_bit()
118 ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; in hri_supc_clear_INTEN_BOD33DET_bit()
[all …]
Dhri_dmac_l21.h92 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; in hri_dmac_set_CHINTEN_TERR_bit()
97 return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; in hri_dmac_get_CHINTEN_TERR_bit()
103 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; in hri_dmac_write_CHINTEN_TERR_bit()
105 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; in hri_dmac_write_CHINTEN_TERR_bit()
111 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; in hri_dmac_clear_CHINTEN_TERR_bit()
116 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; in hri_dmac_set_CHINTEN_TCMPL_bit()
121 return (((Dmac *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; in hri_dmac_get_CHINTEN_TCMPL_bit()
127 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; in hri_dmac_write_CHINTEN_TCMPL_bit()
129 ((Dmac *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; in hri_dmac_write_CHINTEN_TCMPL_bit()
135 ((Dmac *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; in hri_dmac_clear_CHINTEN_TCMPL_bit()
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Dhri_mclk_l21.h77 ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; in hri_mclk_set_INTEN_CKRDY_bit()
82 return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; in hri_mclk_get_INTEN_CKRDY_bit()
88 ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; in hri_mclk_write_INTEN_CKRDY_bit()
90 ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; in hri_mclk_write_INTEN_CKRDY_bit()
96 ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; in hri_mclk_clear_INTEN_CKRDY_bit()
101 ((Mclk *)hw)->INTENSET.reg = mask; in hri_mclk_set_INTEN_reg()
107 tmp = ((Mclk *)hw)->INTENSET.reg; in hri_mclk_get_INTEN_reg()
114 return ((Mclk *)hw)->INTENSET.reg; in hri_mclk_read_INTEN_reg()
119 ((Mclk *)hw)->INTENSET.reg = data; in hri_mclk_write_INTEN_reg()
120 ((Mclk *)hw)->INTENCLR.reg = ~data; in hri_mclk_write_INTEN_reg()
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Dhri_tcc_l21.h83 static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) in hri_tcc_wait_for_sync() argument
85 while (((Tcc *)hw)->SYNCBUSY.reg & reg) { in hri_tcc_wait_for_sync()
89 static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) in hri_tcc_is_syncing() argument
91 return ((Tcc *)hw)->SYNCBUSY.reg & reg; in hri_tcc_is_syncing()
97 ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH4_COUNT(mask); in hri_tcc_set_COUNT_DITH4_COUNT_bf()
104 tmp = ((Tcc *)hw)->COUNT.reg; in hri_tcc_get_COUNT_DITH4_COUNT_bf()
113 tmp = ((Tcc *)hw)->COUNT.reg; in hri_tcc_write_COUNT_DITH4_COUNT_bf()
116 ((Tcc *)hw)->COUNT.reg = tmp; in hri_tcc_write_COUNT_DITH4_COUNT_bf()
123 ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH4_COUNT(mask); in hri_tcc_clear_COUNT_DITH4_COUNT_bf()
130 ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH4_COUNT(mask); in hri_tcc_toggle_COUNT_DITH4_COUNT_bf()
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Dhri_tal_l21.h87 ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_BRK; in hri_tal_set_INTEN_BRK_bit()
92 return (((Tal *)hw)->INTENSET.reg & TAL_INTENSET_BRK) >> TAL_INTENSET_BRK_Pos; in hri_tal_get_INTEN_BRK_bit()
98 ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_BRK; in hri_tal_write_INTEN_BRK_bit()
100 ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_BRK; in hri_tal_write_INTEN_BRK_bit()
106 ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_BRK; in hri_tal_clear_INTEN_BRK_bit()
111 ((Tal *)hw)->INTENSET.reg = mask; in hri_tal_set_INTEN_reg()
117 tmp = ((Tal *)hw)->INTENSET.reg; in hri_tal_get_INTEN_reg()
124 return ((Tal *)hw)->INTENSET.reg; in hri_tal_read_INTEN_reg()
129 ((Tal *)hw)->INTENSET.reg = data; in hri_tal_write_INTEN_reg()
130 ((Tal *)hw)->INTENCLR.reg = ~data; in hri_tal_write_INTEN_reg()
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Dhri_adc_l21.h84 static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) in hri_adc_wait_for_sync() argument
86 while (((Adc *)hw)->SYNCBUSY.reg & reg) { in hri_adc_wait_for_sync()
90 static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) in hri_adc_is_syncing() argument
92 return ((Adc *)hw)->SYNCBUSY.reg & reg; in hri_adc_is_syncing()
97 ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; in hri_adc_set_INTEN_RESRDY_bit()
102 return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; in hri_adc_get_INTEN_RESRDY_bit()
108 ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; in hri_adc_write_INTEN_RESRDY_bit()
110 ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; in hri_adc_write_INTEN_RESRDY_bit()
116 ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; in hri_adc_clear_INTEN_RESRDY_bit()
121 ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; in hri_adc_set_INTEN_OVERRUN_bit()
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Dhri_sercom_l21.h101 …c inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) in hri_sercomi2cm_wait_for_sync() argument
103 while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { in hri_sercomi2cm_wait_for_sync()
107 …atic inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) in hri_sercomi2cm_is_syncing() argument
109 return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; in hri_sercomi2cm_is_syncing()
112 …c inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) in hri_sercomi2cs_wait_for_sync() argument
114 while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { in hri_sercomi2cs_wait_for_sync()
118 …atic inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) in hri_sercomi2cs_is_syncing() argument
120 return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; in hri_sercomi2cs_is_syncing()
123 …tic inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) in hri_sercomspi_wait_for_sync() argument
125 while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { in hri_sercomspi_wait_for_sync()
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Dhri_dac_l21.h74 static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) in hri_dac_wait_for_sync() argument
76 while (((Dac *)hw)->SYNCBUSY.reg & reg) { in hri_dac_wait_for_sync()
80 static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) in hri_dac_is_syncing() argument
82 return ((Dac *)hw)->SYNCBUSY.reg & reg; in hri_dac_is_syncing()
87 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; in hri_dac_set_INTEN_UNDERRUN0_bit()
92 return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; in hri_dac_get_INTEN_UNDERRUN0_bit()
98 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; in hri_dac_write_INTEN_UNDERRUN0_bit()
100 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; in hri_dac_write_INTEN_UNDERRUN0_bit()
106 ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; in hri_dac_clear_INTEN_UNDERRUN0_bit()
111 ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; in hri_dac_set_INTEN_UNDERRUN1_bit()
[all …]
Dhri_osc32kctrl_l21.h72 ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit()
77 …return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_… in hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit()
83 ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit()
85 ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit()
91 ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; in hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit()
96 ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; in hri_osc32kctrl_set_INTEN_OSC32KRDY_bit()
101 …return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_OSC32KRDY) >> OSC32KCTRL_INTENSET_O… in hri_osc32kctrl_get_INTEN_OSC32KRDY_bit()
107 ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; in hri_osc32kctrl_write_INTEN_OSC32KRDY_bit()
109 ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_OSC32KRDY; in hri_osc32kctrl_write_INTEN_OSC32KRDY_bit()
115 ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_OSC32KRDY; in hri_osc32kctrl_clear_INTEN_OSC32KRDY_bit()
[all …]
Dhri_usb_l21.h124 …tic inline void hri_usbdevice_wait_for_sync(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) in hri_usbdevice_wait_for_sync() argument
126 while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { in hri_usbdevice_wait_for_sync()
130 static inline bool hri_usbdevice_is_syncing(const void *const hw, hri_usbdevice_syncbusy_reg_t reg) in hri_usbdevice_is_syncing() argument
132 return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; in hri_usbdevice_is_syncing()
135 static inline void hri_usbhost_wait_for_sync(const void *const hw, hri_usbhost_syncbusy_reg_t reg) in hri_usbhost_wait_for_sync() argument
137 while (((Usb *)hw)->HOST.SYNCBUSY.reg & reg) { in hri_usbhost_wait_for_sync()
141 static inline bool hri_usbhost_is_syncing(const void *const hw, hri_usbhost_syncbusy_reg_t reg) in hri_usbhost_is_syncing() argument
143 return ((Usb *)hw)->HOST.SYNCBUSY.reg & reg; in hri_usbhost_is_syncing()
148 ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; in hri_usbpipe_set_PSTATUS_DTGL_bit()
153 return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) in hri_usbpipe_get_PSTATUS_DTGL_bit()
[all …]
Dhri_rtc_l21.h97 static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) in hri_rtcmode0_wait_for_sync() argument
99 while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { in hri_rtcmode0_wait_for_sync()
103 static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) in hri_rtcmode0_is_syncing() argument
105 return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; in hri_rtcmode0_is_syncing()
108 static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) in hri_rtcmode1_wait_for_sync() argument
110 while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { in hri_rtcmode1_wait_for_sync()
114 static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) in hri_rtcmode1_is_syncing() argument
116 return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; in hri_rtcmode1_is_syncing()
119 static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) in hri_rtcmode2_wait_for_sync() argument
121 while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { in hri_rtcmode2_wait_for_sync()
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Dhri_aes_l21.h78 ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; in hri_aes_set_INTEN_ENCCMP_bit()
83 return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; in hri_aes_get_INTEN_ENCCMP_bit()
89 ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; in hri_aes_write_INTEN_ENCCMP_bit()
91 ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; in hri_aes_write_INTEN_ENCCMP_bit()
97 ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; in hri_aes_clear_INTEN_ENCCMP_bit()
102 ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; in hri_aes_set_INTEN_GFMCMP_bit()
107 return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; in hri_aes_get_INTEN_GFMCMP_bit()
113 ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; in hri_aes_write_INTEN_GFMCMP_bit()
115 ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; in hri_aes_write_INTEN_GFMCMP_bit()
121 ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; in hri_aes_clear_INTEN_GFMCMP_bit()
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Dhri_nvic_l21.h78 ((Nvic *)hw)->NVICISER.reg |= NVIC_NVICISER_SETENA(mask); in hri_nvic_set_NVICISER_SETENA_bf()
86 tmp = ((Nvic *)hw)->NVICISER.reg; in hri_nvic_get_NVICISER_SETENA_bf()
95 tmp = ((Nvic *)hw)->NVICISER.reg; in hri_nvic_write_NVICISER_SETENA_bf()
98 ((Nvic *)hw)->NVICISER.reg = tmp; in hri_nvic_write_NVICISER_SETENA_bf()
105 ((Nvic *)hw)->NVICISER.reg &= ~NVIC_NVICISER_SETENA(mask); in hri_nvic_clear_NVICISER_SETENA_bf()
112 ((Nvic *)hw)->NVICISER.reg ^= NVIC_NVICISER_SETENA(mask); in hri_nvic_toggle_NVICISER_SETENA_bf()
119 tmp = ((Nvic *)hw)->NVICISER.reg; in hri_nvic_read_NVICISER_SETENA_bf()
127 ((Nvic *)hw)->NVICISER.reg |= mask; in hri_nvic_set_NVICISER_reg()
134 tmp = ((Nvic *)hw)->NVICISER.reg; in hri_nvic_get_NVICISER_reg()
142 ((Nvic *)hw)->NVICISER.reg = data; in hri_nvic_write_NVICISER_reg()
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Dhri_dsu_l21.h90 ((Dsu *)hw)->CTRL.reg = data; in hri_dsu_write_CTRL_reg()
97 ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); in hri_dsu_set_ADDR_AMOD_bf()
104 tmp = ((Dsu *)hw)->ADDR.reg; in hri_dsu_get_ADDR_AMOD_bf()
113 tmp = ((Dsu *)hw)->ADDR.reg; in hri_dsu_write_ADDR_AMOD_bf()
116 ((Dsu *)hw)->ADDR.reg = tmp; in hri_dsu_write_ADDR_AMOD_bf()
123 ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); in hri_dsu_clear_ADDR_AMOD_bf()
130 ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); in hri_dsu_toggle_ADDR_AMOD_bf()
137 tmp = ((Dsu *)hw)->ADDR.reg; in hri_dsu_read_ADDR_AMOD_bf()
145 ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); in hri_dsu_set_ADDR_ADDR_bf()
152 tmp = ((Dsu *)hw)->ADDR.reg; in hri_dsu_get_ADDR_ADDR_bf()
[all …]
Dhri_systemcontrol_l21.h74 ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_REVISION(mask); in hri_systemcontrol_set_CPUID_REVISION_bf()
82 tmp = ((Systemcontrol *)hw)->CPUID.reg; in hri_systemcontrol_get_CPUID_REVISION_bf()
91 tmp = ((Systemcontrol *)hw)->CPUID.reg; in hri_systemcontrol_write_CPUID_REVISION_bf()
94 ((Systemcontrol *)hw)->CPUID.reg = tmp; in hri_systemcontrol_write_CPUID_REVISION_bf()
101 ((Systemcontrol *)hw)->CPUID.reg &= ~SystemControl_CPUID_REVISION(mask); in hri_systemcontrol_clear_CPUID_REVISION_bf()
108 ((Systemcontrol *)hw)->CPUID.reg ^= SystemControl_CPUID_REVISION(mask); in hri_systemcontrol_toggle_CPUID_REVISION_bf()
115 tmp = ((Systemcontrol *)hw)->CPUID.reg; in hri_systemcontrol_read_CPUID_REVISION_bf()
123 ((Systemcontrol *)hw)->CPUID.reg |= SystemControl_CPUID_PARTNO(mask); in hri_systemcontrol_set_CPUID_PARTNO_bf()
131 tmp = ((Systemcontrol *)hw)->CPUID.reg; in hri_systemcontrol_get_CPUID_PARTNO_bf()
140 tmp = ((Systemcontrol *)hw)->CPUID.reg; in hri_systemcontrol_write_CPUID_PARTNO_bf()
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Dhri_pm_l21.h72 ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; in hri_pm_set_INTEN_PLRDY_bit()
77 return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_PLRDY) >> PM_INTENSET_PLRDY_Pos; in hri_pm_get_INTEN_PLRDY_bit()
83 ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; in hri_pm_write_INTEN_PLRDY_bit()
85 ((Pm *)hw)->INTENSET.reg = PM_INTENSET_PLRDY; in hri_pm_write_INTEN_PLRDY_bit()
91 ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_PLRDY; in hri_pm_clear_INTEN_PLRDY_bit()
96 ((Pm *)hw)->INTENSET.reg = mask; in hri_pm_set_INTEN_reg()
102 tmp = ((Pm *)hw)->INTENSET.reg; in hri_pm_get_INTEN_reg()
109 return ((Pm *)hw)->INTENSET.reg; in hri_pm_read_INTEN_reg()
114 ((Pm *)hw)->INTENSET.reg = data; in hri_pm_write_INTEN_reg()
115 ((Pm *)hw)->INTENCLR.reg = ~data; in hri_pm_write_INTEN_reg()
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Dhri_nvmctrl_l21.h73 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_set_INTEN_READY_bit()
78 return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; in hri_nvmctrl_get_INTEN_READY_bit()
84 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_write_INTEN_READY_bit()
86 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_write_INTEN_READY_bit()
92 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_clear_INTEN_READY_bit()
97 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_set_INTEN_ERROR_bit()
102 return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; in hri_nvmctrl_get_INTEN_ERROR_bit()
108 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_write_INTEN_ERROR_bit()
110 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_write_INTEN_ERROR_bit()
116 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_clear_INTEN_ERROR_bit()
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Dhri_tc_l21.h84 static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) in hri_tc_wait_for_sync() argument
86 while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { in hri_tc_wait_for_sync()
90 static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) in hri_tc_is_syncing() argument
92 return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; in hri_tc_is_syncing()
98 ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); in hri_tccount16_set_COUNT_COUNT_bf()
105 tmp = ((Tc *)hw)->COUNT16.COUNT.reg; in hri_tccount16_get_COUNT_COUNT_bf()
114 tmp = ((Tc *)hw)->COUNT16.COUNT.reg; in hri_tccount16_write_COUNT_COUNT_bf()
117 ((Tc *)hw)->COUNT16.COUNT.reg = tmp; in hri_tccount16_write_COUNT_COUNT_bf()
124 ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); in hri_tccount16_clear_COUNT_COUNT_bf()
131 ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); in hri_tccount16_toggle_COUNT_COUNT_bf()
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Dhri_ac_l21.h75 static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) in hri_ac_wait_for_sync() argument
77 while (((Ac *)hw)->SYNCBUSY.reg & reg) { in hri_ac_wait_for_sync()
81 static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) in hri_ac_is_syncing() argument
83 return ((Ac *)hw)->SYNCBUSY.reg & reg; in hri_ac_is_syncing()
88 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; in hri_ac_set_INTEN_COMP0_bit()
93 return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; in hri_ac_get_INTEN_COMP0_bit()
99 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; in hri_ac_write_INTEN_COMP0_bit()
101 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; in hri_ac_write_INTEN_COMP0_bit()
107 ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; in hri_ac_clear_INTEN_COMP0_bit()
112 ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; in hri_ac_set_INTEN_COMP1_bit()
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Dhri_eic_l21.h72 static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) in hri_eic_wait_for_sync() argument
74 while (((Eic *)hw)->SYNCBUSY.reg & reg) { in hri_eic_wait_for_sync()
78 static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) in hri_eic_is_syncing() argument
80 return ((Eic *)hw)->SYNCBUSY.reg & reg; in hri_eic_is_syncing()
85 ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); in hri_eic_set_INTEN_EXTINT_bf()
91 tmp = ((Eic *)hw)->INTENSET.reg; in hri_eic_get_INTEN_EXTINT_bf()
99 tmp = ((Eic *)hw)->INTENSET.reg; in hri_eic_read_INTEN_EXTINT_bf()
106 ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); in hri_eic_write_INTEN_EXTINT_bf()
107 ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); in hri_eic_write_INTEN_EXTINT_bf()
112 ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); in hri_eic_clear_INTEN_EXTINT_bf()
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Dhri_wdt_l21.h70 static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) in hri_wdt_wait_for_sync() argument
72 while (((Wdt *)hw)->SYNCBUSY.reg & reg) { in hri_wdt_wait_for_sync()
76 static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) in hri_wdt_is_syncing() argument
78 return ((Wdt *)hw)->SYNCBUSY.reg & reg; in hri_wdt_is_syncing()
83 ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; in hri_wdt_set_INTEN_EW_bit()
88 return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; in hri_wdt_get_INTEN_EW_bit()
94 ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; in hri_wdt_write_INTEN_EW_bit()
96 ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; in hri_wdt_write_INTEN_EW_bit()
102 ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; in hri_wdt_clear_INTEN_EW_bit()
107 ((Wdt *)hw)->INTENSET.reg = mask; in hri_wdt_set_INTEN_reg()
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Dhri_systick_l21.h70 ((Systick *)hw)->CSR.reg |= SysTick_CSR_ENABLE; in hri_systick_set_CSR_ENABLE_bit()
77 tmp = ((Systick *)hw)->CSR.reg; in hri_systick_get_CSR_ENABLE_bit()
86 tmp = ((Systick *)hw)->CSR.reg; in hri_systick_write_CSR_ENABLE_bit()
89 ((Systick *)hw)->CSR.reg = tmp; in hri_systick_write_CSR_ENABLE_bit()
96 ((Systick *)hw)->CSR.reg &= ~SysTick_CSR_ENABLE; in hri_systick_clear_CSR_ENABLE_bit()
103 ((Systick *)hw)->CSR.reg ^= SysTick_CSR_ENABLE; in hri_systick_toggle_CSR_ENABLE_bit()
110 ((Systick *)hw)->CSR.reg |= SysTick_CSR_TICKINT; in hri_systick_set_CSR_TICKINT_bit()
117 tmp = ((Systick *)hw)->CSR.reg; in hri_systick_get_CSR_TICKINT_bit()
126 tmp = ((Systick *)hw)->CSR.reg; in hri_systick_write_CSR_TICKINT_bit()
129 ((Systick *)hw)->CSR.reg = tmp; in hri_systick_write_CSR_TICKINT_bit()
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