1 /**
2 * \file
3 *
4 * \brief SAM TCC
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_TCC_COMPONENT_
44 #ifndef _HRI_TCC_L21_H_INCLUDED_
45 #define _HRI_TCC_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_TCC_CRITICAL_SECTIONS)
55 #define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define TCC_CRITICAL_SECTION_ENTER()
59 #define TCC_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint16_t hri_tcc_patt_reg_t;
63 typedef uint16_t hri_tcc_pattbuf_reg_t;
64 typedef uint32_t hri_tcc_cc_reg_t;
65 typedef uint32_t hri_tcc_ccbuf_reg_t;
66 typedef uint32_t hri_tcc_count_reg_t;
67 typedef uint32_t hri_tcc_ctrla_reg_t;
68 typedef uint32_t hri_tcc_drvctrl_reg_t;
69 typedef uint32_t hri_tcc_evctrl_reg_t;
70 typedef uint32_t hri_tcc_fctrla_reg_t;
71 typedef uint32_t hri_tcc_fctrlb_reg_t;
72 typedef uint32_t hri_tcc_intenset_reg_t;
73 typedef uint32_t hri_tcc_intflag_reg_t;
74 typedef uint32_t hri_tcc_per_reg_t;
75 typedef uint32_t hri_tcc_perbuf_reg_t;
76 typedef uint32_t hri_tcc_status_reg_t;
77 typedef uint32_t hri_tcc_syncbusy_reg_t;
78 typedef uint32_t hri_tcc_wave_reg_t;
79 typedef uint32_t hri_tcc_wexctrl_reg_t;
80 typedef uint8_t hri_tcc_ctrlbset_reg_t;
81 typedef uint8_t hri_tcc_dbgctrl_reg_t;
82
hri_tcc_wait_for_sync(const void * const hw,hri_tcc_syncbusy_reg_t reg)83 static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg)
84 {
85 while (((Tcc *)hw)->SYNCBUSY.reg & reg) {
86 };
87 }
88
hri_tcc_is_syncing(const void * const hw,hri_tcc_syncbusy_reg_t reg)89 static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg)
90 {
91 return ((Tcc *)hw)->SYNCBUSY.reg & reg;
92 }
93
hri_tcc_set_COUNT_DITH4_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)94 static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
95 {
96 TCC_CRITICAL_SECTION_ENTER();
97 ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH4_COUNT(mask);
98 TCC_CRITICAL_SECTION_LEAVE();
99 }
100
hri_tcc_get_COUNT_DITH4_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)101 static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
102 {
103 uint32_t tmp;
104 tmp = ((Tcc *)hw)->COUNT.reg;
105 tmp = (tmp & TCC_COUNT_DITH4_COUNT(mask)) >> TCC_COUNT_DITH4_COUNT_Pos;
106 return tmp;
107 }
108
hri_tcc_write_COUNT_DITH4_COUNT_bf(const void * const hw,hri_tcc_count_reg_t data)109 static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
110 {
111 uint32_t tmp;
112 TCC_CRITICAL_SECTION_ENTER();
113 tmp = ((Tcc *)hw)->COUNT.reg;
114 tmp &= ~TCC_COUNT_DITH4_COUNT_Msk;
115 tmp |= TCC_COUNT_DITH4_COUNT(data);
116 ((Tcc *)hw)->COUNT.reg = tmp;
117 TCC_CRITICAL_SECTION_LEAVE();
118 }
119
hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)120 static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
121 {
122 TCC_CRITICAL_SECTION_ENTER();
123 ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH4_COUNT(mask);
124 TCC_CRITICAL_SECTION_LEAVE();
125 }
126
hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)127 static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
128 {
129 TCC_CRITICAL_SECTION_ENTER();
130 ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH4_COUNT(mask);
131 TCC_CRITICAL_SECTION_LEAVE();
132 }
133
hri_tcc_read_COUNT_DITH4_COUNT_bf(const void * const hw)134 static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw)
135 {
136 uint32_t tmp;
137 tmp = ((Tcc *)hw)->COUNT.reg;
138 tmp = (tmp & TCC_COUNT_DITH4_COUNT_Msk) >> TCC_COUNT_DITH4_COUNT_Pos;
139 return tmp;
140 }
141
hri_tcc_set_COUNT_DITH5_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)142 static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
143 {
144 TCC_CRITICAL_SECTION_ENTER();
145 ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH5_COUNT(mask);
146 TCC_CRITICAL_SECTION_LEAVE();
147 }
148
hri_tcc_get_COUNT_DITH5_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)149 static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
150 {
151 uint32_t tmp;
152 tmp = ((Tcc *)hw)->COUNT.reg;
153 tmp = (tmp & TCC_COUNT_DITH5_COUNT(mask)) >> TCC_COUNT_DITH5_COUNT_Pos;
154 return tmp;
155 }
156
hri_tcc_write_COUNT_DITH5_COUNT_bf(const void * const hw,hri_tcc_count_reg_t data)157 static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
158 {
159 uint32_t tmp;
160 TCC_CRITICAL_SECTION_ENTER();
161 tmp = ((Tcc *)hw)->COUNT.reg;
162 tmp &= ~TCC_COUNT_DITH5_COUNT_Msk;
163 tmp |= TCC_COUNT_DITH5_COUNT(data);
164 ((Tcc *)hw)->COUNT.reg = tmp;
165 TCC_CRITICAL_SECTION_LEAVE();
166 }
167
hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)168 static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
169 {
170 TCC_CRITICAL_SECTION_ENTER();
171 ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH5_COUNT(mask);
172 TCC_CRITICAL_SECTION_LEAVE();
173 }
174
hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)175 static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
176 {
177 TCC_CRITICAL_SECTION_ENTER();
178 ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH5_COUNT(mask);
179 TCC_CRITICAL_SECTION_LEAVE();
180 }
181
hri_tcc_read_COUNT_DITH5_COUNT_bf(const void * const hw)182 static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw)
183 {
184 uint32_t tmp;
185 tmp = ((Tcc *)hw)->COUNT.reg;
186 tmp = (tmp & TCC_COUNT_DITH5_COUNT_Msk) >> TCC_COUNT_DITH5_COUNT_Pos;
187 return tmp;
188 }
189
hri_tcc_set_COUNT_DITH6_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)190 static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
191 {
192 TCC_CRITICAL_SECTION_ENTER();
193 ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_DITH6_COUNT(mask);
194 TCC_CRITICAL_SECTION_LEAVE();
195 }
196
hri_tcc_get_COUNT_DITH6_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)197 static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
198 {
199 uint32_t tmp;
200 tmp = ((Tcc *)hw)->COUNT.reg;
201 tmp = (tmp & TCC_COUNT_DITH6_COUNT(mask)) >> TCC_COUNT_DITH6_COUNT_Pos;
202 return tmp;
203 }
204
hri_tcc_write_COUNT_DITH6_COUNT_bf(const void * const hw,hri_tcc_count_reg_t data)205 static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
206 {
207 uint32_t tmp;
208 TCC_CRITICAL_SECTION_ENTER();
209 tmp = ((Tcc *)hw)->COUNT.reg;
210 tmp &= ~TCC_COUNT_DITH6_COUNT_Msk;
211 tmp |= TCC_COUNT_DITH6_COUNT(data);
212 ((Tcc *)hw)->COUNT.reg = tmp;
213 TCC_CRITICAL_SECTION_LEAVE();
214 }
215
hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)216 static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
217 {
218 TCC_CRITICAL_SECTION_ENTER();
219 ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_DITH6_COUNT(mask);
220 TCC_CRITICAL_SECTION_LEAVE();
221 }
222
hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)223 static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
224 {
225 TCC_CRITICAL_SECTION_ENTER();
226 ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_DITH6_COUNT(mask);
227 TCC_CRITICAL_SECTION_LEAVE();
228 }
229
hri_tcc_read_COUNT_DITH6_COUNT_bf(const void * const hw)230 static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw)
231 {
232 uint32_t tmp;
233 tmp = ((Tcc *)hw)->COUNT.reg;
234 tmp = (tmp & TCC_COUNT_DITH6_COUNT_Msk) >> TCC_COUNT_DITH6_COUNT_Pos;
235 return tmp;
236 }
237
hri_tcc_set_COUNT_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)238 static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
239 {
240 TCC_CRITICAL_SECTION_ENTER();
241 ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask);
242 TCC_CRITICAL_SECTION_LEAVE();
243 }
244
hri_tcc_get_COUNT_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)245 static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
246 {
247 uint32_t tmp;
248 tmp = ((Tcc *)hw)->COUNT.reg;
249 tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos;
250 return tmp;
251 }
252
hri_tcc_write_COUNT_COUNT_bf(const void * const hw,hri_tcc_count_reg_t data)253 static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data)
254 {
255 uint32_t tmp;
256 TCC_CRITICAL_SECTION_ENTER();
257 tmp = ((Tcc *)hw)->COUNT.reg;
258 tmp &= ~TCC_COUNT_COUNT_Msk;
259 tmp |= TCC_COUNT_COUNT(data);
260 ((Tcc *)hw)->COUNT.reg = tmp;
261 TCC_CRITICAL_SECTION_LEAVE();
262 }
263
hri_tcc_clear_COUNT_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)264 static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
265 {
266 TCC_CRITICAL_SECTION_ENTER();
267 ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask);
268 TCC_CRITICAL_SECTION_LEAVE();
269 }
270
hri_tcc_toggle_COUNT_COUNT_bf(const void * const hw,hri_tcc_count_reg_t mask)271 static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask)
272 {
273 TCC_CRITICAL_SECTION_ENTER();
274 ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask);
275 TCC_CRITICAL_SECTION_LEAVE();
276 }
277
hri_tcc_read_COUNT_COUNT_bf(const void * const hw)278 static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw)
279 {
280 uint32_t tmp;
281 tmp = ((Tcc *)hw)->COUNT.reg;
282 tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos;
283 return tmp;
284 }
285
hri_tcc_set_COUNT_DITH4_reg(const void * const hw,hri_tcc_count_reg_t mask)286 static inline void hri_tcc_set_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask)
287 {
288 TCC_CRITICAL_SECTION_ENTER();
289 ((Tcc *)hw)->COUNT.reg |= mask;
290 TCC_CRITICAL_SECTION_LEAVE();
291 }
292
hri_tcc_get_COUNT_DITH4_reg(const void * const hw,hri_tcc_count_reg_t mask)293 static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask)
294 {
295 uint32_t tmp;
296 tmp = ((Tcc *)hw)->COUNT.reg;
297 tmp &= mask;
298 return tmp;
299 }
300
hri_tcc_write_COUNT_DITH4_reg(const void * const hw,hri_tcc_count_reg_t data)301 static inline void hri_tcc_write_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t data)
302 {
303 TCC_CRITICAL_SECTION_ENTER();
304 ((Tcc *)hw)->COUNT.reg = data;
305 TCC_CRITICAL_SECTION_LEAVE();
306 }
307
hri_tcc_clear_COUNT_DITH4_reg(const void * const hw,hri_tcc_count_reg_t mask)308 static inline void hri_tcc_clear_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask)
309 {
310 TCC_CRITICAL_SECTION_ENTER();
311 ((Tcc *)hw)->COUNT.reg &= ~mask;
312 TCC_CRITICAL_SECTION_LEAVE();
313 }
314
hri_tcc_toggle_COUNT_DITH4_reg(const void * const hw,hri_tcc_count_reg_t mask)315 static inline void hri_tcc_toggle_COUNT_DITH4_reg(const void *const hw, hri_tcc_count_reg_t mask)
316 {
317 TCC_CRITICAL_SECTION_ENTER();
318 ((Tcc *)hw)->COUNT.reg ^= mask;
319 TCC_CRITICAL_SECTION_LEAVE();
320 }
321
hri_tcc_read_COUNT_DITH4_reg(const void * const hw)322 static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_reg(const void *const hw)
323 {
324 return ((Tcc *)hw)->COUNT.reg;
325 }
326
hri_tcc_set_COUNT_DITH5_reg(const void * const hw,hri_tcc_count_reg_t mask)327 static inline void hri_tcc_set_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask)
328 {
329 TCC_CRITICAL_SECTION_ENTER();
330 ((Tcc *)hw)->COUNT.reg |= mask;
331 TCC_CRITICAL_SECTION_LEAVE();
332 }
333
hri_tcc_get_COUNT_DITH5_reg(const void * const hw,hri_tcc_count_reg_t mask)334 static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask)
335 {
336 uint32_t tmp;
337 tmp = ((Tcc *)hw)->COUNT.reg;
338 tmp &= mask;
339 return tmp;
340 }
341
hri_tcc_write_COUNT_DITH5_reg(const void * const hw,hri_tcc_count_reg_t data)342 static inline void hri_tcc_write_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t data)
343 {
344 TCC_CRITICAL_SECTION_ENTER();
345 ((Tcc *)hw)->COUNT.reg = data;
346 TCC_CRITICAL_SECTION_LEAVE();
347 }
348
hri_tcc_clear_COUNT_DITH5_reg(const void * const hw,hri_tcc_count_reg_t mask)349 static inline void hri_tcc_clear_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask)
350 {
351 TCC_CRITICAL_SECTION_ENTER();
352 ((Tcc *)hw)->COUNT.reg &= ~mask;
353 TCC_CRITICAL_SECTION_LEAVE();
354 }
355
hri_tcc_toggle_COUNT_DITH5_reg(const void * const hw,hri_tcc_count_reg_t mask)356 static inline void hri_tcc_toggle_COUNT_DITH5_reg(const void *const hw, hri_tcc_count_reg_t mask)
357 {
358 TCC_CRITICAL_SECTION_ENTER();
359 ((Tcc *)hw)->COUNT.reg ^= mask;
360 TCC_CRITICAL_SECTION_LEAVE();
361 }
362
hri_tcc_read_COUNT_DITH5_reg(const void * const hw)363 static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_reg(const void *const hw)
364 {
365 return ((Tcc *)hw)->COUNT.reg;
366 }
367
hri_tcc_set_COUNT_DITH6_reg(const void * const hw,hri_tcc_count_reg_t mask)368 static inline void hri_tcc_set_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask)
369 {
370 TCC_CRITICAL_SECTION_ENTER();
371 ((Tcc *)hw)->COUNT.reg |= mask;
372 TCC_CRITICAL_SECTION_LEAVE();
373 }
374
hri_tcc_get_COUNT_DITH6_reg(const void * const hw,hri_tcc_count_reg_t mask)375 static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask)
376 {
377 uint32_t tmp;
378 tmp = ((Tcc *)hw)->COUNT.reg;
379 tmp &= mask;
380 return tmp;
381 }
382
hri_tcc_write_COUNT_DITH6_reg(const void * const hw,hri_tcc_count_reg_t data)383 static inline void hri_tcc_write_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t data)
384 {
385 TCC_CRITICAL_SECTION_ENTER();
386 ((Tcc *)hw)->COUNT.reg = data;
387 TCC_CRITICAL_SECTION_LEAVE();
388 }
389
hri_tcc_clear_COUNT_DITH6_reg(const void * const hw,hri_tcc_count_reg_t mask)390 static inline void hri_tcc_clear_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask)
391 {
392 TCC_CRITICAL_SECTION_ENTER();
393 ((Tcc *)hw)->COUNT.reg &= ~mask;
394 TCC_CRITICAL_SECTION_LEAVE();
395 }
396
hri_tcc_toggle_COUNT_DITH6_reg(const void * const hw,hri_tcc_count_reg_t mask)397 static inline void hri_tcc_toggle_COUNT_DITH6_reg(const void *const hw, hri_tcc_count_reg_t mask)
398 {
399 TCC_CRITICAL_SECTION_ENTER();
400 ((Tcc *)hw)->COUNT.reg ^= mask;
401 TCC_CRITICAL_SECTION_LEAVE();
402 }
403
hri_tcc_read_COUNT_DITH6_reg(const void * const hw)404 static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_reg(const void *const hw)
405 {
406 return ((Tcc *)hw)->COUNT.reg;
407 }
408
hri_tcc_set_COUNT_reg(const void * const hw,hri_tcc_count_reg_t mask)409 static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
410 {
411 TCC_CRITICAL_SECTION_ENTER();
412 ((Tcc *)hw)->COUNT.reg |= mask;
413 TCC_CRITICAL_SECTION_LEAVE();
414 }
415
hri_tcc_get_COUNT_reg(const void * const hw,hri_tcc_count_reg_t mask)416 static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
417 {
418 uint32_t tmp;
419 tmp = ((Tcc *)hw)->COUNT.reg;
420 tmp &= mask;
421 return tmp;
422 }
423
hri_tcc_write_COUNT_reg(const void * const hw,hri_tcc_count_reg_t data)424 static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data)
425 {
426 TCC_CRITICAL_SECTION_ENTER();
427 ((Tcc *)hw)->COUNT.reg = data;
428 TCC_CRITICAL_SECTION_LEAVE();
429 }
430
hri_tcc_clear_COUNT_reg(const void * const hw,hri_tcc_count_reg_t mask)431 static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
432 {
433 TCC_CRITICAL_SECTION_ENTER();
434 ((Tcc *)hw)->COUNT.reg &= ~mask;
435 TCC_CRITICAL_SECTION_LEAVE();
436 }
437
hri_tcc_toggle_COUNT_reg(const void * const hw,hri_tcc_count_reg_t mask)438 static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask)
439 {
440 TCC_CRITICAL_SECTION_ENTER();
441 ((Tcc *)hw)->COUNT.reg ^= mask;
442 TCC_CRITICAL_SECTION_LEAVE();
443 }
444
hri_tcc_read_COUNT_reg(const void * const hw)445 static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw)
446 {
447 return ((Tcc *)hw)->COUNT.reg;
448 }
449
hri_tcc_set_PER_DITH4_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)450 static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
451 {
452 TCC_CRITICAL_SECTION_ENTER();
453 ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask);
454 TCC_CRITICAL_SECTION_LEAVE();
455 }
456
hri_tcc_get_PER_DITH4_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)457 static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
458 {
459 uint32_t tmp;
460 tmp = ((Tcc *)hw)->PER.reg;
461 tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos;
462 return tmp;
463 }
464
hri_tcc_write_PER_DITH4_DITHER_bf(const void * const hw,hri_tcc_per_reg_t data)465 static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
466 {
467 uint32_t tmp;
468 TCC_CRITICAL_SECTION_ENTER();
469 tmp = ((Tcc *)hw)->PER.reg;
470 tmp &= ~TCC_PER_DITH4_DITHER_Msk;
471 tmp |= TCC_PER_DITH4_DITHER(data);
472 ((Tcc *)hw)->PER.reg = tmp;
473 TCC_CRITICAL_SECTION_LEAVE();
474 }
475
hri_tcc_clear_PER_DITH4_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)476 static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
477 {
478 TCC_CRITICAL_SECTION_ENTER();
479 ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask);
480 TCC_CRITICAL_SECTION_LEAVE();
481 }
482
hri_tcc_toggle_PER_DITH4_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)483 static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
484 {
485 TCC_CRITICAL_SECTION_ENTER();
486 ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask);
487 TCC_CRITICAL_SECTION_LEAVE();
488 }
489
hri_tcc_read_PER_DITH4_DITHER_bf(const void * const hw)490 static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw)
491 {
492 uint32_t tmp;
493 tmp = ((Tcc *)hw)->PER.reg;
494 tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos;
495 return tmp;
496 }
497
hri_tcc_set_PER_DITH4_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)498 static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
499 {
500 TCC_CRITICAL_SECTION_ENTER();
501 ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_PER(mask);
502 TCC_CRITICAL_SECTION_LEAVE();
503 }
504
hri_tcc_get_PER_DITH4_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)505 static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
506 {
507 uint32_t tmp;
508 tmp = ((Tcc *)hw)->PER.reg;
509 tmp = (tmp & TCC_PER_DITH4_PER(mask)) >> TCC_PER_DITH4_PER_Pos;
510 return tmp;
511 }
512
hri_tcc_write_PER_DITH4_PER_bf(const void * const hw,hri_tcc_per_reg_t data)513 static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
514 {
515 uint32_t tmp;
516 TCC_CRITICAL_SECTION_ENTER();
517 tmp = ((Tcc *)hw)->PER.reg;
518 tmp &= ~TCC_PER_DITH4_PER_Msk;
519 tmp |= TCC_PER_DITH4_PER(data);
520 ((Tcc *)hw)->PER.reg = tmp;
521 TCC_CRITICAL_SECTION_LEAVE();
522 }
523
hri_tcc_clear_PER_DITH4_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)524 static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
525 {
526 TCC_CRITICAL_SECTION_ENTER();
527 ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_PER(mask);
528 TCC_CRITICAL_SECTION_LEAVE();
529 }
530
hri_tcc_toggle_PER_DITH4_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)531 static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
532 {
533 TCC_CRITICAL_SECTION_ENTER();
534 ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_PER(mask);
535 TCC_CRITICAL_SECTION_LEAVE();
536 }
537
hri_tcc_read_PER_DITH4_PER_bf(const void * const hw)538 static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw)
539 {
540 uint32_t tmp;
541 tmp = ((Tcc *)hw)->PER.reg;
542 tmp = (tmp & TCC_PER_DITH4_PER_Msk) >> TCC_PER_DITH4_PER_Pos;
543 return tmp;
544 }
545
hri_tcc_set_PER_DITH5_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)546 static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
547 {
548 TCC_CRITICAL_SECTION_ENTER();
549 ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask);
550 TCC_CRITICAL_SECTION_LEAVE();
551 }
552
hri_tcc_get_PER_DITH5_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)553 static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
554 {
555 uint32_t tmp;
556 tmp = ((Tcc *)hw)->PER.reg;
557 tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos;
558 return tmp;
559 }
560
hri_tcc_write_PER_DITH5_DITHER_bf(const void * const hw,hri_tcc_per_reg_t data)561 static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
562 {
563 uint32_t tmp;
564 TCC_CRITICAL_SECTION_ENTER();
565 tmp = ((Tcc *)hw)->PER.reg;
566 tmp &= ~TCC_PER_DITH5_DITHER_Msk;
567 tmp |= TCC_PER_DITH5_DITHER(data);
568 ((Tcc *)hw)->PER.reg = tmp;
569 TCC_CRITICAL_SECTION_LEAVE();
570 }
571
hri_tcc_clear_PER_DITH5_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)572 static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
573 {
574 TCC_CRITICAL_SECTION_ENTER();
575 ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask);
576 TCC_CRITICAL_SECTION_LEAVE();
577 }
578
hri_tcc_toggle_PER_DITH5_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)579 static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
580 {
581 TCC_CRITICAL_SECTION_ENTER();
582 ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask);
583 TCC_CRITICAL_SECTION_LEAVE();
584 }
585
hri_tcc_read_PER_DITH5_DITHER_bf(const void * const hw)586 static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw)
587 {
588 uint32_t tmp;
589 tmp = ((Tcc *)hw)->PER.reg;
590 tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos;
591 return tmp;
592 }
593
hri_tcc_set_PER_DITH5_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)594 static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
595 {
596 TCC_CRITICAL_SECTION_ENTER();
597 ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_PER(mask);
598 TCC_CRITICAL_SECTION_LEAVE();
599 }
600
hri_tcc_get_PER_DITH5_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)601 static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
602 {
603 uint32_t tmp;
604 tmp = ((Tcc *)hw)->PER.reg;
605 tmp = (tmp & TCC_PER_DITH5_PER(mask)) >> TCC_PER_DITH5_PER_Pos;
606 return tmp;
607 }
608
hri_tcc_write_PER_DITH5_PER_bf(const void * const hw,hri_tcc_per_reg_t data)609 static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
610 {
611 uint32_t tmp;
612 TCC_CRITICAL_SECTION_ENTER();
613 tmp = ((Tcc *)hw)->PER.reg;
614 tmp &= ~TCC_PER_DITH5_PER_Msk;
615 tmp |= TCC_PER_DITH5_PER(data);
616 ((Tcc *)hw)->PER.reg = tmp;
617 TCC_CRITICAL_SECTION_LEAVE();
618 }
619
hri_tcc_clear_PER_DITH5_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)620 static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
621 {
622 TCC_CRITICAL_SECTION_ENTER();
623 ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_PER(mask);
624 TCC_CRITICAL_SECTION_LEAVE();
625 }
626
hri_tcc_toggle_PER_DITH5_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)627 static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
628 {
629 TCC_CRITICAL_SECTION_ENTER();
630 ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_PER(mask);
631 TCC_CRITICAL_SECTION_LEAVE();
632 }
633
hri_tcc_read_PER_DITH5_PER_bf(const void * const hw)634 static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw)
635 {
636 uint32_t tmp;
637 tmp = ((Tcc *)hw)->PER.reg;
638 tmp = (tmp & TCC_PER_DITH5_PER_Msk) >> TCC_PER_DITH5_PER_Pos;
639 return tmp;
640 }
641
hri_tcc_set_PER_DITH6_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)642 static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
643 {
644 TCC_CRITICAL_SECTION_ENTER();
645 ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask);
646 TCC_CRITICAL_SECTION_LEAVE();
647 }
648
hri_tcc_get_PER_DITH6_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)649 static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
650 {
651 uint32_t tmp;
652 tmp = ((Tcc *)hw)->PER.reg;
653 tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos;
654 return tmp;
655 }
656
hri_tcc_write_PER_DITH6_DITHER_bf(const void * const hw,hri_tcc_per_reg_t data)657 static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data)
658 {
659 uint32_t tmp;
660 TCC_CRITICAL_SECTION_ENTER();
661 tmp = ((Tcc *)hw)->PER.reg;
662 tmp &= ~TCC_PER_DITH6_DITHER_Msk;
663 tmp |= TCC_PER_DITH6_DITHER(data);
664 ((Tcc *)hw)->PER.reg = tmp;
665 TCC_CRITICAL_SECTION_LEAVE();
666 }
667
hri_tcc_clear_PER_DITH6_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)668 static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
669 {
670 TCC_CRITICAL_SECTION_ENTER();
671 ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask);
672 TCC_CRITICAL_SECTION_LEAVE();
673 }
674
hri_tcc_toggle_PER_DITH6_DITHER_bf(const void * const hw,hri_tcc_per_reg_t mask)675 static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask)
676 {
677 TCC_CRITICAL_SECTION_ENTER();
678 ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask);
679 TCC_CRITICAL_SECTION_LEAVE();
680 }
681
hri_tcc_read_PER_DITH6_DITHER_bf(const void * const hw)682 static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw)
683 {
684 uint32_t tmp;
685 tmp = ((Tcc *)hw)->PER.reg;
686 tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos;
687 return tmp;
688 }
689
hri_tcc_set_PER_DITH6_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)690 static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
691 {
692 TCC_CRITICAL_SECTION_ENTER();
693 ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_PER(mask);
694 TCC_CRITICAL_SECTION_LEAVE();
695 }
696
hri_tcc_get_PER_DITH6_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)697 static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
698 {
699 uint32_t tmp;
700 tmp = ((Tcc *)hw)->PER.reg;
701 tmp = (tmp & TCC_PER_DITH6_PER(mask)) >> TCC_PER_DITH6_PER_Pos;
702 return tmp;
703 }
704
hri_tcc_write_PER_DITH6_PER_bf(const void * const hw,hri_tcc_per_reg_t data)705 static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
706 {
707 uint32_t tmp;
708 TCC_CRITICAL_SECTION_ENTER();
709 tmp = ((Tcc *)hw)->PER.reg;
710 tmp &= ~TCC_PER_DITH6_PER_Msk;
711 tmp |= TCC_PER_DITH6_PER(data);
712 ((Tcc *)hw)->PER.reg = tmp;
713 TCC_CRITICAL_SECTION_LEAVE();
714 }
715
hri_tcc_clear_PER_DITH6_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)716 static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
717 {
718 TCC_CRITICAL_SECTION_ENTER();
719 ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_PER(mask);
720 TCC_CRITICAL_SECTION_LEAVE();
721 }
722
hri_tcc_toggle_PER_DITH6_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)723 static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
724 {
725 TCC_CRITICAL_SECTION_ENTER();
726 ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_PER(mask);
727 TCC_CRITICAL_SECTION_LEAVE();
728 }
729
hri_tcc_read_PER_DITH6_PER_bf(const void * const hw)730 static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw)
731 {
732 uint32_t tmp;
733 tmp = ((Tcc *)hw)->PER.reg;
734 tmp = (tmp & TCC_PER_DITH6_PER_Msk) >> TCC_PER_DITH6_PER_Pos;
735 return tmp;
736 }
737
hri_tcc_set_PER_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)738 static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
739 {
740 TCC_CRITICAL_SECTION_ENTER();
741 ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask);
742 TCC_CRITICAL_SECTION_LEAVE();
743 }
744
hri_tcc_get_PER_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)745 static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
746 {
747 uint32_t tmp;
748 tmp = ((Tcc *)hw)->PER.reg;
749 tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos;
750 return tmp;
751 }
752
hri_tcc_write_PER_PER_bf(const void * const hw,hri_tcc_per_reg_t data)753 static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data)
754 {
755 uint32_t tmp;
756 TCC_CRITICAL_SECTION_ENTER();
757 tmp = ((Tcc *)hw)->PER.reg;
758 tmp &= ~TCC_PER_PER_Msk;
759 tmp |= TCC_PER_PER(data);
760 ((Tcc *)hw)->PER.reg = tmp;
761 TCC_CRITICAL_SECTION_LEAVE();
762 }
763
hri_tcc_clear_PER_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)764 static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
765 {
766 TCC_CRITICAL_SECTION_ENTER();
767 ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask);
768 TCC_CRITICAL_SECTION_LEAVE();
769 }
770
hri_tcc_toggle_PER_PER_bf(const void * const hw,hri_tcc_per_reg_t mask)771 static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask)
772 {
773 TCC_CRITICAL_SECTION_ENTER();
774 ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask);
775 TCC_CRITICAL_SECTION_LEAVE();
776 }
777
hri_tcc_read_PER_PER_bf(const void * const hw)778 static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw)
779 {
780 uint32_t tmp;
781 tmp = ((Tcc *)hw)->PER.reg;
782 tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos;
783 return tmp;
784 }
785
hri_tcc_set_PER_DITH4_reg(const void * const hw,hri_tcc_per_reg_t mask)786 static inline void hri_tcc_set_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask)
787 {
788 TCC_CRITICAL_SECTION_ENTER();
789 ((Tcc *)hw)->PER.reg |= mask;
790 TCC_CRITICAL_SECTION_LEAVE();
791 }
792
hri_tcc_get_PER_DITH4_reg(const void * const hw,hri_tcc_per_reg_t mask)793 static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask)
794 {
795 uint32_t tmp;
796 tmp = ((Tcc *)hw)->PER.reg;
797 tmp &= mask;
798 return tmp;
799 }
800
hri_tcc_write_PER_DITH4_reg(const void * const hw,hri_tcc_per_reg_t data)801 static inline void hri_tcc_write_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t data)
802 {
803 TCC_CRITICAL_SECTION_ENTER();
804 ((Tcc *)hw)->PER.reg = data;
805 TCC_CRITICAL_SECTION_LEAVE();
806 }
807
hri_tcc_clear_PER_DITH4_reg(const void * const hw,hri_tcc_per_reg_t mask)808 static inline void hri_tcc_clear_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask)
809 {
810 TCC_CRITICAL_SECTION_ENTER();
811 ((Tcc *)hw)->PER.reg &= ~mask;
812 TCC_CRITICAL_SECTION_LEAVE();
813 }
814
hri_tcc_toggle_PER_DITH4_reg(const void * const hw,hri_tcc_per_reg_t mask)815 static inline void hri_tcc_toggle_PER_DITH4_reg(const void *const hw, hri_tcc_per_reg_t mask)
816 {
817 TCC_CRITICAL_SECTION_ENTER();
818 ((Tcc *)hw)->PER.reg ^= mask;
819 TCC_CRITICAL_SECTION_LEAVE();
820 }
821
hri_tcc_read_PER_DITH4_reg(const void * const hw)822 static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_reg(const void *const hw)
823 {
824 return ((Tcc *)hw)->PER.reg;
825 }
826
hri_tcc_set_PER_DITH5_reg(const void * const hw,hri_tcc_per_reg_t mask)827 static inline void hri_tcc_set_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask)
828 {
829 TCC_CRITICAL_SECTION_ENTER();
830 ((Tcc *)hw)->PER.reg |= mask;
831 TCC_CRITICAL_SECTION_LEAVE();
832 }
833
hri_tcc_get_PER_DITH5_reg(const void * const hw,hri_tcc_per_reg_t mask)834 static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask)
835 {
836 uint32_t tmp;
837 tmp = ((Tcc *)hw)->PER.reg;
838 tmp &= mask;
839 return tmp;
840 }
841
hri_tcc_write_PER_DITH5_reg(const void * const hw,hri_tcc_per_reg_t data)842 static inline void hri_tcc_write_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t data)
843 {
844 TCC_CRITICAL_SECTION_ENTER();
845 ((Tcc *)hw)->PER.reg = data;
846 TCC_CRITICAL_SECTION_LEAVE();
847 }
848
hri_tcc_clear_PER_DITH5_reg(const void * const hw,hri_tcc_per_reg_t mask)849 static inline void hri_tcc_clear_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask)
850 {
851 TCC_CRITICAL_SECTION_ENTER();
852 ((Tcc *)hw)->PER.reg &= ~mask;
853 TCC_CRITICAL_SECTION_LEAVE();
854 }
855
hri_tcc_toggle_PER_DITH5_reg(const void * const hw,hri_tcc_per_reg_t mask)856 static inline void hri_tcc_toggle_PER_DITH5_reg(const void *const hw, hri_tcc_per_reg_t mask)
857 {
858 TCC_CRITICAL_SECTION_ENTER();
859 ((Tcc *)hw)->PER.reg ^= mask;
860 TCC_CRITICAL_SECTION_LEAVE();
861 }
862
hri_tcc_read_PER_DITH5_reg(const void * const hw)863 static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_reg(const void *const hw)
864 {
865 return ((Tcc *)hw)->PER.reg;
866 }
867
hri_tcc_set_PER_DITH6_reg(const void * const hw,hri_tcc_per_reg_t mask)868 static inline void hri_tcc_set_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask)
869 {
870 TCC_CRITICAL_SECTION_ENTER();
871 ((Tcc *)hw)->PER.reg |= mask;
872 TCC_CRITICAL_SECTION_LEAVE();
873 }
874
hri_tcc_get_PER_DITH6_reg(const void * const hw,hri_tcc_per_reg_t mask)875 static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask)
876 {
877 uint32_t tmp;
878 tmp = ((Tcc *)hw)->PER.reg;
879 tmp &= mask;
880 return tmp;
881 }
882
hri_tcc_write_PER_DITH6_reg(const void * const hw,hri_tcc_per_reg_t data)883 static inline void hri_tcc_write_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t data)
884 {
885 TCC_CRITICAL_SECTION_ENTER();
886 ((Tcc *)hw)->PER.reg = data;
887 TCC_CRITICAL_SECTION_LEAVE();
888 }
889
hri_tcc_clear_PER_DITH6_reg(const void * const hw,hri_tcc_per_reg_t mask)890 static inline void hri_tcc_clear_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask)
891 {
892 TCC_CRITICAL_SECTION_ENTER();
893 ((Tcc *)hw)->PER.reg &= ~mask;
894 TCC_CRITICAL_SECTION_LEAVE();
895 }
896
hri_tcc_toggle_PER_DITH6_reg(const void * const hw,hri_tcc_per_reg_t mask)897 static inline void hri_tcc_toggle_PER_DITH6_reg(const void *const hw, hri_tcc_per_reg_t mask)
898 {
899 TCC_CRITICAL_SECTION_ENTER();
900 ((Tcc *)hw)->PER.reg ^= mask;
901 TCC_CRITICAL_SECTION_LEAVE();
902 }
903
hri_tcc_read_PER_DITH6_reg(const void * const hw)904 static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_reg(const void *const hw)
905 {
906 return ((Tcc *)hw)->PER.reg;
907 }
908
hri_tcc_set_PER_reg(const void * const hw,hri_tcc_per_reg_t mask)909 static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
910 {
911 TCC_CRITICAL_SECTION_ENTER();
912 ((Tcc *)hw)->PER.reg |= mask;
913 TCC_CRITICAL_SECTION_LEAVE();
914 }
915
hri_tcc_get_PER_reg(const void * const hw,hri_tcc_per_reg_t mask)916 static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
917 {
918 uint32_t tmp;
919 tmp = ((Tcc *)hw)->PER.reg;
920 tmp &= mask;
921 return tmp;
922 }
923
hri_tcc_write_PER_reg(const void * const hw,hri_tcc_per_reg_t data)924 static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data)
925 {
926 TCC_CRITICAL_SECTION_ENTER();
927 ((Tcc *)hw)->PER.reg = data;
928 TCC_CRITICAL_SECTION_LEAVE();
929 }
930
hri_tcc_clear_PER_reg(const void * const hw,hri_tcc_per_reg_t mask)931 static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
932 {
933 TCC_CRITICAL_SECTION_ENTER();
934 ((Tcc *)hw)->PER.reg &= ~mask;
935 TCC_CRITICAL_SECTION_LEAVE();
936 }
937
hri_tcc_toggle_PER_reg(const void * const hw,hri_tcc_per_reg_t mask)938 static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask)
939 {
940 TCC_CRITICAL_SECTION_ENTER();
941 ((Tcc *)hw)->PER.reg ^= mask;
942 TCC_CRITICAL_SECTION_LEAVE();
943 }
944
hri_tcc_read_PER_reg(const void * const hw)945 static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw)
946 {
947 return ((Tcc *)hw)->PER.reg;
948 }
949
hri_tcc_set_CC_DITH4_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)950 static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
951 {
952 TCC_CRITICAL_SECTION_ENTER();
953 ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask);
954 TCC_CRITICAL_SECTION_LEAVE();
955 }
956
hri_tcc_get_CC_DITH4_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)957 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index,
958 hri_tcc_cc_reg_t mask)
959 {
960 uint32_t tmp;
961 tmp = ((Tcc *)hw)->CC[index].reg;
962 tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos;
963 return tmp;
964 }
965
hri_tcc_write_CC_DITH4_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)966 static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
967 {
968 uint32_t tmp;
969 TCC_CRITICAL_SECTION_ENTER();
970 tmp = ((Tcc *)hw)->CC[index].reg;
971 tmp &= ~TCC_CC_DITH4_DITHER_Msk;
972 tmp |= TCC_CC_DITH4_DITHER(data);
973 ((Tcc *)hw)->CC[index].reg = tmp;
974 TCC_CRITICAL_SECTION_LEAVE();
975 }
976
hri_tcc_clear_CC_DITH4_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)977 static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
978 {
979 TCC_CRITICAL_SECTION_ENTER();
980 ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask);
981 TCC_CRITICAL_SECTION_LEAVE();
982 }
983
hri_tcc_toggle_CC_DITH4_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)984 static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
985 {
986 TCC_CRITICAL_SECTION_ENTER();
987 ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask);
988 TCC_CRITICAL_SECTION_LEAVE();
989 }
990
hri_tcc_read_CC_DITH4_DITHER_bf(const void * const hw,uint8_t index)991 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index)
992 {
993 uint32_t tmp;
994 tmp = ((Tcc *)hw)->CC[index].reg;
995 tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos;
996 return tmp;
997 }
998
hri_tcc_set_CC_DITH4_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)999 static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1000 {
1001 TCC_CRITICAL_SECTION_ENTER();
1002 ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_CC(mask);
1003 TCC_CRITICAL_SECTION_LEAVE();
1004 }
1005
hri_tcc_get_CC_DITH4_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1006 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1007 {
1008 uint32_t tmp;
1009 tmp = ((Tcc *)hw)->CC[index].reg;
1010 tmp = (tmp & TCC_CC_DITH4_CC(mask)) >> TCC_CC_DITH4_CC_Pos;
1011 return tmp;
1012 }
1013
hri_tcc_write_CC_DITH4_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)1014 static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
1015 {
1016 uint32_t tmp;
1017 TCC_CRITICAL_SECTION_ENTER();
1018 tmp = ((Tcc *)hw)->CC[index].reg;
1019 tmp &= ~TCC_CC_DITH4_CC_Msk;
1020 tmp |= TCC_CC_DITH4_CC(data);
1021 ((Tcc *)hw)->CC[index].reg = tmp;
1022 TCC_CRITICAL_SECTION_LEAVE();
1023 }
1024
hri_tcc_clear_CC_DITH4_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1025 static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1026 {
1027 TCC_CRITICAL_SECTION_ENTER();
1028 ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_CC(mask);
1029 TCC_CRITICAL_SECTION_LEAVE();
1030 }
1031
hri_tcc_toggle_CC_DITH4_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1032 static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1033 {
1034 TCC_CRITICAL_SECTION_ENTER();
1035 ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_CC(mask);
1036 TCC_CRITICAL_SECTION_LEAVE();
1037 }
1038
hri_tcc_read_CC_DITH4_CC_bf(const void * const hw,uint8_t index)1039 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index)
1040 {
1041 uint32_t tmp;
1042 tmp = ((Tcc *)hw)->CC[index].reg;
1043 tmp = (tmp & TCC_CC_DITH4_CC_Msk) >> TCC_CC_DITH4_CC_Pos;
1044 return tmp;
1045 }
1046
hri_tcc_set_CC_DITH5_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1047 static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1048 {
1049 TCC_CRITICAL_SECTION_ENTER();
1050 ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask);
1051 TCC_CRITICAL_SECTION_LEAVE();
1052 }
1053
hri_tcc_get_CC_DITH5_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1054 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index,
1055 hri_tcc_cc_reg_t mask)
1056 {
1057 uint32_t tmp;
1058 tmp = ((Tcc *)hw)->CC[index].reg;
1059 tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos;
1060 return tmp;
1061 }
1062
hri_tcc_write_CC_DITH5_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)1063 static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
1064 {
1065 uint32_t tmp;
1066 TCC_CRITICAL_SECTION_ENTER();
1067 tmp = ((Tcc *)hw)->CC[index].reg;
1068 tmp &= ~TCC_CC_DITH5_DITHER_Msk;
1069 tmp |= TCC_CC_DITH5_DITHER(data);
1070 ((Tcc *)hw)->CC[index].reg = tmp;
1071 TCC_CRITICAL_SECTION_LEAVE();
1072 }
1073
hri_tcc_clear_CC_DITH5_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1074 static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1075 {
1076 TCC_CRITICAL_SECTION_ENTER();
1077 ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask);
1078 TCC_CRITICAL_SECTION_LEAVE();
1079 }
1080
hri_tcc_toggle_CC_DITH5_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1081 static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1082 {
1083 TCC_CRITICAL_SECTION_ENTER();
1084 ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask);
1085 TCC_CRITICAL_SECTION_LEAVE();
1086 }
1087
hri_tcc_read_CC_DITH5_DITHER_bf(const void * const hw,uint8_t index)1088 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index)
1089 {
1090 uint32_t tmp;
1091 tmp = ((Tcc *)hw)->CC[index].reg;
1092 tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos;
1093 return tmp;
1094 }
1095
hri_tcc_set_CC_DITH5_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1096 static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1097 {
1098 TCC_CRITICAL_SECTION_ENTER();
1099 ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_CC(mask);
1100 TCC_CRITICAL_SECTION_LEAVE();
1101 }
1102
hri_tcc_get_CC_DITH5_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1103 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1104 {
1105 uint32_t tmp;
1106 tmp = ((Tcc *)hw)->CC[index].reg;
1107 tmp = (tmp & TCC_CC_DITH5_CC(mask)) >> TCC_CC_DITH5_CC_Pos;
1108 return tmp;
1109 }
1110
hri_tcc_write_CC_DITH5_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)1111 static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
1112 {
1113 uint32_t tmp;
1114 TCC_CRITICAL_SECTION_ENTER();
1115 tmp = ((Tcc *)hw)->CC[index].reg;
1116 tmp &= ~TCC_CC_DITH5_CC_Msk;
1117 tmp |= TCC_CC_DITH5_CC(data);
1118 ((Tcc *)hw)->CC[index].reg = tmp;
1119 TCC_CRITICAL_SECTION_LEAVE();
1120 }
1121
hri_tcc_clear_CC_DITH5_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1122 static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1123 {
1124 TCC_CRITICAL_SECTION_ENTER();
1125 ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_CC(mask);
1126 TCC_CRITICAL_SECTION_LEAVE();
1127 }
1128
hri_tcc_toggle_CC_DITH5_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1129 static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1130 {
1131 TCC_CRITICAL_SECTION_ENTER();
1132 ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_CC(mask);
1133 TCC_CRITICAL_SECTION_LEAVE();
1134 }
1135
hri_tcc_read_CC_DITH5_CC_bf(const void * const hw,uint8_t index)1136 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index)
1137 {
1138 uint32_t tmp;
1139 tmp = ((Tcc *)hw)->CC[index].reg;
1140 tmp = (tmp & TCC_CC_DITH5_CC_Msk) >> TCC_CC_DITH5_CC_Pos;
1141 return tmp;
1142 }
1143
hri_tcc_set_CC_DITH6_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1144 static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1145 {
1146 TCC_CRITICAL_SECTION_ENTER();
1147 ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask);
1148 TCC_CRITICAL_SECTION_LEAVE();
1149 }
1150
hri_tcc_get_CC_DITH6_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1151 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index,
1152 hri_tcc_cc_reg_t mask)
1153 {
1154 uint32_t tmp;
1155 tmp = ((Tcc *)hw)->CC[index].reg;
1156 tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos;
1157 return tmp;
1158 }
1159
hri_tcc_write_CC_DITH6_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)1160 static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
1161 {
1162 uint32_t tmp;
1163 TCC_CRITICAL_SECTION_ENTER();
1164 tmp = ((Tcc *)hw)->CC[index].reg;
1165 tmp &= ~TCC_CC_DITH6_DITHER_Msk;
1166 tmp |= TCC_CC_DITH6_DITHER(data);
1167 ((Tcc *)hw)->CC[index].reg = tmp;
1168 TCC_CRITICAL_SECTION_LEAVE();
1169 }
1170
hri_tcc_clear_CC_DITH6_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1171 static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1172 {
1173 TCC_CRITICAL_SECTION_ENTER();
1174 ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask);
1175 TCC_CRITICAL_SECTION_LEAVE();
1176 }
1177
hri_tcc_toggle_CC_DITH6_DITHER_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1178 static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1179 {
1180 TCC_CRITICAL_SECTION_ENTER();
1181 ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask);
1182 TCC_CRITICAL_SECTION_LEAVE();
1183 }
1184
hri_tcc_read_CC_DITH6_DITHER_bf(const void * const hw,uint8_t index)1185 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index)
1186 {
1187 uint32_t tmp;
1188 tmp = ((Tcc *)hw)->CC[index].reg;
1189 tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos;
1190 return tmp;
1191 }
1192
hri_tcc_set_CC_DITH6_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1193 static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1194 {
1195 TCC_CRITICAL_SECTION_ENTER();
1196 ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_CC(mask);
1197 TCC_CRITICAL_SECTION_LEAVE();
1198 }
1199
hri_tcc_get_CC_DITH6_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1200 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1201 {
1202 uint32_t tmp;
1203 tmp = ((Tcc *)hw)->CC[index].reg;
1204 tmp = (tmp & TCC_CC_DITH6_CC(mask)) >> TCC_CC_DITH6_CC_Pos;
1205 return tmp;
1206 }
1207
hri_tcc_write_CC_DITH6_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)1208 static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
1209 {
1210 uint32_t tmp;
1211 TCC_CRITICAL_SECTION_ENTER();
1212 tmp = ((Tcc *)hw)->CC[index].reg;
1213 tmp &= ~TCC_CC_DITH6_CC_Msk;
1214 tmp |= TCC_CC_DITH6_CC(data);
1215 ((Tcc *)hw)->CC[index].reg = tmp;
1216 TCC_CRITICAL_SECTION_LEAVE();
1217 }
1218
hri_tcc_clear_CC_DITH6_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1219 static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1220 {
1221 TCC_CRITICAL_SECTION_ENTER();
1222 ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_CC(mask);
1223 TCC_CRITICAL_SECTION_LEAVE();
1224 }
1225
hri_tcc_toggle_CC_DITH6_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1226 static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1227 {
1228 TCC_CRITICAL_SECTION_ENTER();
1229 ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_CC(mask);
1230 TCC_CRITICAL_SECTION_LEAVE();
1231 }
1232
hri_tcc_read_CC_DITH6_CC_bf(const void * const hw,uint8_t index)1233 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index)
1234 {
1235 uint32_t tmp;
1236 tmp = ((Tcc *)hw)->CC[index].reg;
1237 tmp = (tmp & TCC_CC_DITH6_CC_Msk) >> TCC_CC_DITH6_CC_Pos;
1238 return tmp;
1239 }
1240
hri_tcc_set_CC_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1241 static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1242 {
1243 TCC_CRITICAL_SECTION_ENTER();
1244 ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask);
1245 TCC_CRITICAL_SECTION_LEAVE();
1246 }
1247
hri_tcc_get_CC_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1248 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1249 {
1250 uint32_t tmp;
1251 tmp = ((Tcc *)hw)->CC[index].reg;
1252 tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos;
1253 return tmp;
1254 }
1255
hri_tcc_write_CC_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)1256 static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
1257 {
1258 uint32_t tmp;
1259 TCC_CRITICAL_SECTION_ENTER();
1260 tmp = ((Tcc *)hw)->CC[index].reg;
1261 tmp &= ~TCC_CC_CC_Msk;
1262 tmp |= TCC_CC_CC(data);
1263 ((Tcc *)hw)->CC[index].reg = tmp;
1264 TCC_CRITICAL_SECTION_LEAVE();
1265 }
1266
hri_tcc_clear_CC_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1267 static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1268 {
1269 TCC_CRITICAL_SECTION_ENTER();
1270 ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask);
1271 TCC_CRITICAL_SECTION_LEAVE();
1272 }
1273
hri_tcc_toggle_CC_CC_bf(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1274 static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1275 {
1276 TCC_CRITICAL_SECTION_ENTER();
1277 ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask);
1278 TCC_CRITICAL_SECTION_LEAVE();
1279 }
1280
hri_tcc_read_CC_CC_bf(const void * const hw,uint8_t index)1281 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index)
1282 {
1283 uint32_t tmp;
1284 tmp = ((Tcc *)hw)->CC[index].reg;
1285 tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos;
1286 return tmp;
1287 }
1288
hri_tcc_set_CC_DITH4_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1289 static inline void hri_tcc_set_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1290 {
1291 TCC_CRITICAL_SECTION_ENTER();
1292 ((Tcc *)hw)->CC[index].reg |= mask;
1293 TCC_CRITICAL_SECTION_LEAVE();
1294 }
1295
hri_tcc_get_CC_DITH4_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1296 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1297 {
1298 uint32_t tmp;
1299 tmp = ((Tcc *)hw)->CC[index].reg;
1300 tmp &= mask;
1301 return tmp;
1302 }
1303
hri_tcc_write_CC_DITH4_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)1304 static inline void hri_tcc_write_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
1305 {
1306 TCC_CRITICAL_SECTION_ENTER();
1307 ((Tcc *)hw)->CC[index].reg = data;
1308 TCC_CRITICAL_SECTION_LEAVE();
1309 }
1310
hri_tcc_clear_CC_DITH4_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1311 static inline void hri_tcc_clear_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1312 {
1313 TCC_CRITICAL_SECTION_ENTER();
1314 ((Tcc *)hw)->CC[index].reg &= ~mask;
1315 TCC_CRITICAL_SECTION_LEAVE();
1316 }
1317
hri_tcc_toggle_CC_DITH4_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1318 static inline void hri_tcc_toggle_CC_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1319 {
1320 TCC_CRITICAL_SECTION_ENTER();
1321 ((Tcc *)hw)->CC[index].reg ^= mask;
1322 TCC_CRITICAL_SECTION_LEAVE();
1323 }
1324
hri_tcc_read_CC_DITH4_reg(const void * const hw,uint8_t index)1325 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_reg(const void *const hw, uint8_t index)
1326 {
1327 return ((Tcc *)hw)->CC[index].reg;
1328 }
1329
hri_tcc_set_CC_DITH5_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1330 static inline void hri_tcc_set_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1331 {
1332 TCC_CRITICAL_SECTION_ENTER();
1333 ((Tcc *)hw)->CC[index].reg |= mask;
1334 TCC_CRITICAL_SECTION_LEAVE();
1335 }
1336
hri_tcc_get_CC_DITH5_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1337 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1338 {
1339 uint32_t tmp;
1340 tmp = ((Tcc *)hw)->CC[index].reg;
1341 tmp &= mask;
1342 return tmp;
1343 }
1344
hri_tcc_write_CC_DITH5_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)1345 static inline void hri_tcc_write_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
1346 {
1347 TCC_CRITICAL_SECTION_ENTER();
1348 ((Tcc *)hw)->CC[index].reg = data;
1349 TCC_CRITICAL_SECTION_LEAVE();
1350 }
1351
hri_tcc_clear_CC_DITH5_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1352 static inline void hri_tcc_clear_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1353 {
1354 TCC_CRITICAL_SECTION_ENTER();
1355 ((Tcc *)hw)->CC[index].reg &= ~mask;
1356 TCC_CRITICAL_SECTION_LEAVE();
1357 }
1358
hri_tcc_toggle_CC_DITH5_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1359 static inline void hri_tcc_toggle_CC_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1360 {
1361 TCC_CRITICAL_SECTION_ENTER();
1362 ((Tcc *)hw)->CC[index].reg ^= mask;
1363 TCC_CRITICAL_SECTION_LEAVE();
1364 }
1365
hri_tcc_read_CC_DITH5_reg(const void * const hw,uint8_t index)1366 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_reg(const void *const hw, uint8_t index)
1367 {
1368 return ((Tcc *)hw)->CC[index].reg;
1369 }
1370
hri_tcc_set_CC_DITH6_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1371 static inline void hri_tcc_set_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1372 {
1373 TCC_CRITICAL_SECTION_ENTER();
1374 ((Tcc *)hw)->CC[index].reg |= mask;
1375 TCC_CRITICAL_SECTION_LEAVE();
1376 }
1377
hri_tcc_get_CC_DITH6_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1378 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1379 {
1380 uint32_t tmp;
1381 tmp = ((Tcc *)hw)->CC[index].reg;
1382 tmp &= mask;
1383 return tmp;
1384 }
1385
hri_tcc_write_CC_DITH6_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)1386 static inline void hri_tcc_write_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
1387 {
1388 TCC_CRITICAL_SECTION_ENTER();
1389 ((Tcc *)hw)->CC[index].reg = data;
1390 TCC_CRITICAL_SECTION_LEAVE();
1391 }
1392
hri_tcc_clear_CC_DITH6_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1393 static inline void hri_tcc_clear_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1394 {
1395 TCC_CRITICAL_SECTION_ENTER();
1396 ((Tcc *)hw)->CC[index].reg &= ~mask;
1397 TCC_CRITICAL_SECTION_LEAVE();
1398 }
1399
hri_tcc_toggle_CC_DITH6_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1400 static inline void hri_tcc_toggle_CC_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1401 {
1402 TCC_CRITICAL_SECTION_ENTER();
1403 ((Tcc *)hw)->CC[index].reg ^= mask;
1404 TCC_CRITICAL_SECTION_LEAVE();
1405 }
1406
hri_tcc_read_CC_DITH6_reg(const void * const hw,uint8_t index)1407 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_reg(const void *const hw, uint8_t index)
1408 {
1409 return ((Tcc *)hw)->CC[index].reg;
1410 }
1411
hri_tcc_set_CC_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1412 static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1413 {
1414 TCC_CRITICAL_SECTION_ENTER();
1415 ((Tcc *)hw)->CC[index].reg |= mask;
1416 TCC_CRITICAL_SECTION_LEAVE();
1417 }
1418
hri_tcc_get_CC_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1419 static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1420 {
1421 uint32_t tmp;
1422 tmp = ((Tcc *)hw)->CC[index].reg;
1423 tmp &= mask;
1424 return tmp;
1425 }
1426
hri_tcc_write_CC_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t data)1427 static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data)
1428 {
1429 TCC_CRITICAL_SECTION_ENTER();
1430 ((Tcc *)hw)->CC[index].reg = data;
1431 TCC_CRITICAL_SECTION_LEAVE();
1432 }
1433
hri_tcc_clear_CC_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1434 static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1435 {
1436 TCC_CRITICAL_SECTION_ENTER();
1437 ((Tcc *)hw)->CC[index].reg &= ~mask;
1438 TCC_CRITICAL_SECTION_LEAVE();
1439 }
1440
hri_tcc_toggle_CC_reg(const void * const hw,uint8_t index,hri_tcc_cc_reg_t mask)1441 static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask)
1442 {
1443 TCC_CRITICAL_SECTION_ENTER();
1444 ((Tcc *)hw)->CC[index].reg ^= mask;
1445 TCC_CRITICAL_SECTION_LEAVE();
1446 }
1447
hri_tcc_read_CC_reg(const void * const hw,uint8_t index)1448 static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index)
1449 {
1450 return ((Tcc *)hw)->CC[index].reg;
1451 }
1452
hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1453 static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1454 {
1455 TCC_CRITICAL_SECTION_ENTER();
1456 ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask);
1457 TCC_CRITICAL_SECTION_LEAVE();
1458 }
1459
hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1460 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw,
1461 hri_tcc_perbuf_reg_t mask)
1462 {
1463 uint32_t tmp;
1464 tmp = ((Tcc *)hw)->PERBUF.reg;
1465 tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
1466 return tmp;
1467 }
1468
hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t data)1469 static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
1470 {
1471 uint32_t tmp;
1472 TCC_CRITICAL_SECTION_ENTER();
1473 tmp = ((Tcc *)hw)->PERBUF.reg;
1474 tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk;
1475 tmp |= TCC_PERBUF_DITH4_DITHERBUF(data);
1476 ((Tcc *)hw)->PERBUF.reg = tmp;
1477 TCC_CRITICAL_SECTION_LEAVE();
1478 }
1479
hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1480 static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1481 {
1482 TCC_CRITICAL_SECTION_ENTER();
1483 ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask);
1484 TCC_CRITICAL_SECTION_LEAVE();
1485 }
1486
hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1487 static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1488 {
1489 TCC_CRITICAL_SECTION_ENTER();
1490 ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask);
1491 TCC_CRITICAL_SECTION_LEAVE();
1492 }
1493
hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void * const hw)1494 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw)
1495 {
1496 uint32_t tmp;
1497 tmp = ((Tcc *)hw)->PERBUF.reg;
1498 tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos;
1499 return tmp;
1500 }
1501
hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1502 static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1503 {
1504 TCC_CRITICAL_SECTION_ENTER();
1505 ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_PERBUF(mask);
1506 TCC_CRITICAL_SECTION_LEAVE();
1507 }
1508
hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1509 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1510 {
1511 uint32_t tmp;
1512 tmp = ((Tcc *)hw)->PERBUF.reg;
1513 tmp = (tmp & TCC_PERBUF_DITH4_PERBUF(mask)) >> TCC_PERBUF_DITH4_PERBUF_Pos;
1514 return tmp;
1515 }
1516
hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t data)1517 static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
1518 {
1519 uint32_t tmp;
1520 TCC_CRITICAL_SECTION_ENTER();
1521 tmp = ((Tcc *)hw)->PERBUF.reg;
1522 tmp &= ~TCC_PERBUF_DITH4_PERBUF_Msk;
1523 tmp |= TCC_PERBUF_DITH4_PERBUF(data);
1524 ((Tcc *)hw)->PERBUF.reg = tmp;
1525 TCC_CRITICAL_SECTION_LEAVE();
1526 }
1527
hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1528 static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1529 {
1530 TCC_CRITICAL_SECTION_ENTER();
1531 ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_PERBUF(mask);
1532 TCC_CRITICAL_SECTION_LEAVE();
1533 }
1534
hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1535 static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1536 {
1537 TCC_CRITICAL_SECTION_ENTER();
1538 ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_PERBUF(mask);
1539 TCC_CRITICAL_SECTION_LEAVE();
1540 }
1541
hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void * const hw)1542 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw)
1543 {
1544 uint32_t tmp;
1545 tmp = ((Tcc *)hw)->PERBUF.reg;
1546 tmp = (tmp & TCC_PERBUF_DITH4_PERBUF_Msk) >> TCC_PERBUF_DITH4_PERBUF_Pos;
1547 return tmp;
1548 }
1549
hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1550 static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1551 {
1552 TCC_CRITICAL_SECTION_ENTER();
1553 ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask);
1554 TCC_CRITICAL_SECTION_LEAVE();
1555 }
1556
hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1557 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw,
1558 hri_tcc_perbuf_reg_t mask)
1559 {
1560 uint32_t tmp;
1561 tmp = ((Tcc *)hw)->PERBUF.reg;
1562 tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
1563 return tmp;
1564 }
1565
hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t data)1566 static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
1567 {
1568 uint32_t tmp;
1569 TCC_CRITICAL_SECTION_ENTER();
1570 tmp = ((Tcc *)hw)->PERBUF.reg;
1571 tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk;
1572 tmp |= TCC_PERBUF_DITH5_DITHERBUF(data);
1573 ((Tcc *)hw)->PERBUF.reg = tmp;
1574 TCC_CRITICAL_SECTION_LEAVE();
1575 }
1576
hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1577 static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1578 {
1579 TCC_CRITICAL_SECTION_ENTER();
1580 ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask);
1581 TCC_CRITICAL_SECTION_LEAVE();
1582 }
1583
hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1584 static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1585 {
1586 TCC_CRITICAL_SECTION_ENTER();
1587 ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask);
1588 TCC_CRITICAL_SECTION_LEAVE();
1589 }
1590
hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void * const hw)1591 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw)
1592 {
1593 uint32_t tmp;
1594 tmp = ((Tcc *)hw)->PERBUF.reg;
1595 tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos;
1596 return tmp;
1597 }
1598
hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1599 static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1600 {
1601 TCC_CRITICAL_SECTION_ENTER();
1602 ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_PERBUF(mask);
1603 TCC_CRITICAL_SECTION_LEAVE();
1604 }
1605
hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1606 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1607 {
1608 uint32_t tmp;
1609 tmp = ((Tcc *)hw)->PERBUF.reg;
1610 tmp = (tmp & TCC_PERBUF_DITH5_PERBUF(mask)) >> TCC_PERBUF_DITH5_PERBUF_Pos;
1611 return tmp;
1612 }
1613
hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t data)1614 static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
1615 {
1616 uint32_t tmp;
1617 TCC_CRITICAL_SECTION_ENTER();
1618 tmp = ((Tcc *)hw)->PERBUF.reg;
1619 tmp &= ~TCC_PERBUF_DITH5_PERBUF_Msk;
1620 tmp |= TCC_PERBUF_DITH5_PERBUF(data);
1621 ((Tcc *)hw)->PERBUF.reg = tmp;
1622 TCC_CRITICAL_SECTION_LEAVE();
1623 }
1624
hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1625 static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1626 {
1627 TCC_CRITICAL_SECTION_ENTER();
1628 ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_PERBUF(mask);
1629 TCC_CRITICAL_SECTION_LEAVE();
1630 }
1631
hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1632 static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1633 {
1634 TCC_CRITICAL_SECTION_ENTER();
1635 ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_PERBUF(mask);
1636 TCC_CRITICAL_SECTION_LEAVE();
1637 }
1638
hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void * const hw)1639 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw)
1640 {
1641 uint32_t tmp;
1642 tmp = ((Tcc *)hw)->PERBUF.reg;
1643 tmp = (tmp & TCC_PERBUF_DITH5_PERBUF_Msk) >> TCC_PERBUF_DITH5_PERBUF_Pos;
1644 return tmp;
1645 }
1646
hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1647 static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1648 {
1649 TCC_CRITICAL_SECTION_ENTER();
1650 ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask);
1651 TCC_CRITICAL_SECTION_LEAVE();
1652 }
1653
hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1654 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw,
1655 hri_tcc_perbuf_reg_t mask)
1656 {
1657 uint32_t tmp;
1658 tmp = ((Tcc *)hw)->PERBUF.reg;
1659 tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
1660 return tmp;
1661 }
1662
hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t data)1663 static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
1664 {
1665 uint32_t tmp;
1666 TCC_CRITICAL_SECTION_ENTER();
1667 tmp = ((Tcc *)hw)->PERBUF.reg;
1668 tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk;
1669 tmp |= TCC_PERBUF_DITH6_DITHERBUF(data);
1670 ((Tcc *)hw)->PERBUF.reg = tmp;
1671 TCC_CRITICAL_SECTION_LEAVE();
1672 }
1673
hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1674 static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1675 {
1676 TCC_CRITICAL_SECTION_ENTER();
1677 ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask);
1678 TCC_CRITICAL_SECTION_LEAVE();
1679 }
1680
hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1681 static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1682 {
1683 TCC_CRITICAL_SECTION_ENTER();
1684 ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask);
1685 TCC_CRITICAL_SECTION_LEAVE();
1686 }
1687
hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void * const hw)1688 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw)
1689 {
1690 uint32_t tmp;
1691 tmp = ((Tcc *)hw)->PERBUF.reg;
1692 tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos;
1693 return tmp;
1694 }
1695
hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1696 static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1697 {
1698 TCC_CRITICAL_SECTION_ENTER();
1699 ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_PERBUF(mask);
1700 TCC_CRITICAL_SECTION_LEAVE();
1701 }
1702
hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1703 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1704 {
1705 uint32_t tmp;
1706 tmp = ((Tcc *)hw)->PERBUF.reg;
1707 tmp = (tmp & TCC_PERBUF_DITH6_PERBUF(mask)) >> TCC_PERBUF_DITH6_PERBUF_Pos;
1708 return tmp;
1709 }
1710
hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t data)1711 static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
1712 {
1713 uint32_t tmp;
1714 TCC_CRITICAL_SECTION_ENTER();
1715 tmp = ((Tcc *)hw)->PERBUF.reg;
1716 tmp &= ~TCC_PERBUF_DITH6_PERBUF_Msk;
1717 tmp |= TCC_PERBUF_DITH6_PERBUF(data);
1718 ((Tcc *)hw)->PERBUF.reg = tmp;
1719 TCC_CRITICAL_SECTION_LEAVE();
1720 }
1721
hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1722 static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1723 {
1724 TCC_CRITICAL_SECTION_ENTER();
1725 ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_PERBUF(mask);
1726 TCC_CRITICAL_SECTION_LEAVE();
1727 }
1728
hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1729 static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1730 {
1731 TCC_CRITICAL_SECTION_ENTER();
1732 ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_PERBUF(mask);
1733 TCC_CRITICAL_SECTION_LEAVE();
1734 }
1735
hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void * const hw)1736 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw)
1737 {
1738 uint32_t tmp;
1739 tmp = ((Tcc *)hw)->PERBUF.reg;
1740 tmp = (tmp & TCC_PERBUF_DITH6_PERBUF_Msk) >> TCC_PERBUF_DITH6_PERBUF_Pos;
1741 return tmp;
1742 }
1743
hri_tcc_set_PERBUF_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1744 static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1745 {
1746 TCC_CRITICAL_SECTION_ENTER();
1747 ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask);
1748 TCC_CRITICAL_SECTION_LEAVE();
1749 }
1750
hri_tcc_get_PERBUF_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1751 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1752 {
1753 uint32_t tmp;
1754 tmp = ((Tcc *)hw)->PERBUF.reg;
1755 tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos;
1756 return tmp;
1757 }
1758
hri_tcc_write_PERBUF_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t data)1759 static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data)
1760 {
1761 uint32_t tmp;
1762 TCC_CRITICAL_SECTION_ENTER();
1763 tmp = ((Tcc *)hw)->PERBUF.reg;
1764 tmp &= ~TCC_PERBUF_PERBUF_Msk;
1765 tmp |= TCC_PERBUF_PERBUF(data);
1766 ((Tcc *)hw)->PERBUF.reg = tmp;
1767 TCC_CRITICAL_SECTION_LEAVE();
1768 }
1769
hri_tcc_clear_PERBUF_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1770 static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1771 {
1772 TCC_CRITICAL_SECTION_ENTER();
1773 ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask);
1774 TCC_CRITICAL_SECTION_LEAVE();
1775 }
1776
hri_tcc_toggle_PERBUF_PERBUF_bf(const void * const hw,hri_tcc_perbuf_reg_t mask)1777 static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask)
1778 {
1779 TCC_CRITICAL_SECTION_ENTER();
1780 ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask);
1781 TCC_CRITICAL_SECTION_LEAVE();
1782 }
1783
hri_tcc_read_PERBUF_PERBUF_bf(const void * const hw)1784 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw)
1785 {
1786 uint32_t tmp;
1787 tmp = ((Tcc *)hw)->PERBUF.reg;
1788 tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos;
1789 return tmp;
1790 }
1791
hri_tcc_set_PERBUF_DITH4_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1792 static inline void hri_tcc_set_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1793 {
1794 TCC_CRITICAL_SECTION_ENTER();
1795 ((Tcc *)hw)->PERBUF.reg |= mask;
1796 TCC_CRITICAL_SECTION_LEAVE();
1797 }
1798
hri_tcc_get_PERBUF_DITH4_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1799 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1800 {
1801 uint32_t tmp;
1802 tmp = ((Tcc *)hw)->PERBUF.reg;
1803 tmp &= mask;
1804 return tmp;
1805 }
1806
hri_tcc_write_PERBUF_DITH4_reg(const void * const hw,hri_tcc_perbuf_reg_t data)1807 static inline void hri_tcc_write_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t data)
1808 {
1809 TCC_CRITICAL_SECTION_ENTER();
1810 ((Tcc *)hw)->PERBUF.reg = data;
1811 TCC_CRITICAL_SECTION_LEAVE();
1812 }
1813
hri_tcc_clear_PERBUF_DITH4_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1814 static inline void hri_tcc_clear_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1815 {
1816 TCC_CRITICAL_SECTION_ENTER();
1817 ((Tcc *)hw)->PERBUF.reg &= ~mask;
1818 TCC_CRITICAL_SECTION_LEAVE();
1819 }
1820
hri_tcc_toggle_PERBUF_DITH4_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1821 static inline void hri_tcc_toggle_PERBUF_DITH4_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1822 {
1823 TCC_CRITICAL_SECTION_ENTER();
1824 ((Tcc *)hw)->PERBUF.reg ^= mask;
1825 TCC_CRITICAL_SECTION_LEAVE();
1826 }
1827
hri_tcc_read_PERBUF_DITH4_reg(const void * const hw)1828 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_reg(const void *const hw)
1829 {
1830 return ((Tcc *)hw)->PERBUF.reg;
1831 }
1832
hri_tcc_set_PERBUF_DITH5_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1833 static inline void hri_tcc_set_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1834 {
1835 TCC_CRITICAL_SECTION_ENTER();
1836 ((Tcc *)hw)->PERBUF.reg |= mask;
1837 TCC_CRITICAL_SECTION_LEAVE();
1838 }
1839
hri_tcc_get_PERBUF_DITH5_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1840 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1841 {
1842 uint32_t tmp;
1843 tmp = ((Tcc *)hw)->PERBUF.reg;
1844 tmp &= mask;
1845 return tmp;
1846 }
1847
hri_tcc_write_PERBUF_DITH5_reg(const void * const hw,hri_tcc_perbuf_reg_t data)1848 static inline void hri_tcc_write_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t data)
1849 {
1850 TCC_CRITICAL_SECTION_ENTER();
1851 ((Tcc *)hw)->PERBUF.reg = data;
1852 TCC_CRITICAL_SECTION_LEAVE();
1853 }
1854
hri_tcc_clear_PERBUF_DITH5_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1855 static inline void hri_tcc_clear_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1856 {
1857 TCC_CRITICAL_SECTION_ENTER();
1858 ((Tcc *)hw)->PERBUF.reg &= ~mask;
1859 TCC_CRITICAL_SECTION_LEAVE();
1860 }
1861
hri_tcc_toggle_PERBUF_DITH5_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1862 static inline void hri_tcc_toggle_PERBUF_DITH5_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1863 {
1864 TCC_CRITICAL_SECTION_ENTER();
1865 ((Tcc *)hw)->PERBUF.reg ^= mask;
1866 TCC_CRITICAL_SECTION_LEAVE();
1867 }
1868
hri_tcc_read_PERBUF_DITH5_reg(const void * const hw)1869 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_reg(const void *const hw)
1870 {
1871 return ((Tcc *)hw)->PERBUF.reg;
1872 }
1873
hri_tcc_set_PERBUF_DITH6_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1874 static inline void hri_tcc_set_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1875 {
1876 TCC_CRITICAL_SECTION_ENTER();
1877 ((Tcc *)hw)->PERBUF.reg |= mask;
1878 TCC_CRITICAL_SECTION_LEAVE();
1879 }
1880
hri_tcc_get_PERBUF_DITH6_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1881 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1882 {
1883 uint32_t tmp;
1884 tmp = ((Tcc *)hw)->PERBUF.reg;
1885 tmp &= mask;
1886 return tmp;
1887 }
1888
hri_tcc_write_PERBUF_DITH6_reg(const void * const hw,hri_tcc_perbuf_reg_t data)1889 static inline void hri_tcc_write_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t data)
1890 {
1891 TCC_CRITICAL_SECTION_ENTER();
1892 ((Tcc *)hw)->PERBUF.reg = data;
1893 TCC_CRITICAL_SECTION_LEAVE();
1894 }
1895
hri_tcc_clear_PERBUF_DITH6_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1896 static inline void hri_tcc_clear_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1897 {
1898 TCC_CRITICAL_SECTION_ENTER();
1899 ((Tcc *)hw)->PERBUF.reg &= ~mask;
1900 TCC_CRITICAL_SECTION_LEAVE();
1901 }
1902
hri_tcc_toggle_PERBUF_DITH6_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1903 static inline void hri_tcc_toggle_PERBUF_DITH6_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1904 {
1905 TCC_CRITICAL_SECTION_ENTER();
1906 ((Tcc *)hw)->PERBUF.reg ^= mask;
1907 TCC_CRITICAL_SECTION_LEAVE();
1908 }
1909
hri_tcc_read_PERBUF_DITH6_reg(const void * const hw)1910 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_reg(const void *const hw)
1911 {
1912 return ((Tcc *)hw)->PERBUF.reg;
1913 }
1914
hri_tcc_set_PERBUF_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1915 static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1916 {
1917 TCC_CRITICAL_SECTION_ENTER();
1918 ((Tcc *)hw)->PERBUF.reg |= mask;
1919 TCC_CRITICAL_SECTION_LEAVE();
1920 }
1921
hri_tcc_get_PERBUF_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1922 static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1923 {
1924 uint32_t tmp;
1925 tmp = ((Tcc *)hw)->PERBUF.reg;
1926 tmp &= mask;
1927 return tmp;
1928 }
1929
hri_tcc_write_PERBUF_reg(const void * const hw,hri_tcc_perbuf_reg_t data)1930 static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data)
1931 {
1932 TCC_CRITICAL_SECTION_ENTER();
1933 ((Tcc *)hw)->PERBUF.reg = data;
1934 TCC_CRITICAL_SECTION_LEAVE();
1935 }
1936
hri_tcc_clear_PERBUF_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1937 static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1938 {
1939 TCC_CRITICAL_SECTION_ENTER();
1940 ((Tcc *)hw)->PERBUF.reg &= ~mask;
1941 TCC_CRITICAL_SECTION_LEAVE();
1942 }
1943
hri_tcc_toggle_PERBUF_reg(const void * const hw,hri_tcc_perbuf_reg_t mask)1944 static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask)
1945 {
1946 TCC_CRITICAL_SECTION_ENTER();
1947 ((Tcc *)hw)->PERBUF.reg ^= mask;
1948 TCC_CRITICAL_SECTION_LEAVE();
1949 }
1950
hri_tcc_read_PERBUF_reg(const void * const hw)1951 static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw)
1952 {
1953 return ((Tcc *)hw)->PERBUF.reg;
1954 }
1955
hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)1956 static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
1957 {
1958 TCC_CRITICAL_SECTION_ENTER();
1959 ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_CCBUF(mask);
1960 TCC_CRITICAL_SECTION_LEAVE();
1961 }
1962
hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)1963 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index,
1964 hri_tcc_ccbuf_reg_t mask)
1965 {
1966 uint32_t tmp;
1967 tmp = ((Tcc *)hw)->CCBUF[index].reg;
1968 tmp = (tmp & TCC_CCBUF_DITH4_CCBUF(mask)) >> TCC_CCBUF_DITH4_CCBUF_Pos;
1969 return tmp;
1970 }
1971
hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)1972 static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
1973 {
1974 uint32_t tmp;
1975 TCC_CRITICAL_SECTION_ENTER();
1976 tmp = ((Tcc *)hw)->CCBUF[index].reg;
1977 tmp &= ~TCC_CCBUF_DITH4_CCBUF_Msk;
1978 tmp |= TCC_CCBUF_DITH4_CCBUF(data);
1979 ((Tcc *)hw)->CCBUF[index].reg = tmp;
1980 TCC_CRITICAL_SECTION_LEAVE();
1981 }
1982
hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)1983 static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
1984 {
1985 TCC_CRITICAL_SECTION_ENTER();
1986 ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_CCBUF(mask);
1987 TCC_CRITICAL_SECTION_LEAVE();
1988 }
1989
hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)1990 static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
1991 {
1992 TCC_CRITICAL_SECTION_ENTER();
1993 ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_CCBUF(mask);
1994 TCC_CRITICAL_SECTION_LEAVE();
1995 }
1996
hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void * const hw,uint8_t index)1997 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index)
1998 {
1999 uint32_t tmp;
2000 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2001 tmp = (tmp & TCC_CCBUF_DITH4_CCBUF_Msk) >> TCC_CCBUF_DITH4_CCBUF_Pos;
2002 return tmp;
2003 }
2004
hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2005 static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2006 {
2007 TCC_CRITICAL_SECTION_ENTER();
2008 ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask);
2009 TCC_CRITICAL_SECTION_LEAVE();
2010 }
2011
hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2012 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
2013 hri_tcc_ccbuf_reg_t mask)
2014 {
2015 uint32_t tmp;
2016 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2017 tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
2018 return tmp;
2019 }
2020
hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)2021 static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
2022 {
2023 uint32_t tmp;
2024 TCC_CRITICAL_SECTION_ENTER();
2025 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2026 tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk;
2027 tmp |= TCC_CCBUF_DITH4_DITHERBUF(data);
2028 ((Tcc *)hw)->CCBUF[index].reg = tmp;
2029 TCC_CRITICAL_SECTION_LEAVE();
2030 }
2031
hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2032 static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2033 {
2034 TCC_CRITICAL_SECTION_ENTER();
2035 ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask);
2036 TCC_CRITICAL_SECTION_LEAVE();
2037 }
2038
hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2039 static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index,
2040 hri_tcc_ccbuf_reg_t mask)
2041 {
2042 TCC_CRITICAL_SECTION_ENTER();
2043 ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask);
2044 TCC_CRITICAL_SECTION_LEAVE();
2045 }
2046
hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void * const hw,uint8_t index)2047 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index)
2048 {
2049 uint32_t tmp;
2050 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2051 tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos;
2052 return tmp;
2053 }
2054
hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2055 static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2056 {
2057 TCC_CRITICAL_SECTION_ENTER();
2058 ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask);
2059 TCC_CRITICAL_SECTION_LEAVE();
2060 }
2061
hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2062 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
2063 hri_tcc_ccbuf_reg_t mask)
2064 {
2065 uint32_t tmp;
2066 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2067 tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
2068 return tmp;
2069 }
2070
hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)2071 static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
2072 {
2073 uint32_t tmp;
2074 TCC_CRITICAL_SECTION_ENTER();
2075 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2076 tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk;
2077 tmp |= TCC_CCBUF_DITH5_DITHERBUF(data);
2078 ((Tcc *)hw)->CCBUF[index].reg = tmp;
2079 TCC_CRITICAL_SECTION_LEAVE();
2080 }
2081
hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2082 static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2083 {
2084 TCC_CRITICAL_SECTION_ENTER();
2085 ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask);
2086 TCC_CRITICAL_SECTION_LEAVE();
2087 }
2088
hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2089 static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index,
2090 hri_tcc_ccbuf_reg_t mask)
2091 {
2092 TCC_CRITICAL_SECTION_ENTER();
2093 ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask);
2094 TCC_CRITICAL_SECTION_LEAVE();
2095 }
2096
hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void * const hw,uint8_t index)2097 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index)
2098 {
2099 uint32_t tmp;
2100 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2101 tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos;
2102 return tmp;
2103 }
2104
hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2105 static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2106 {
2107 TCC_CRITICAL_SECTION_ENTER();
2108 ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_CCBUF(mask);
2109 TCC_CRITICAL_SECTION_LEAVE();
2110 }
2111
hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2112 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index,
2113 hri_tcc_ccbuf_reg_t mask)
2114 {
2115 uint32_t tmp;
2116 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2117 tmp = (tmp & TCC_CCBUF_DITH5_CCBUF(mask)) >> TCC_CCBUF_DITH5_CCBUF_Pos;
2118 return tmp;
2119 }
2120
hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)2121 static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
2122 {
2123 uint32_t tmp;
2124 TCC_CRITICAL_SECTION_ENTER();
2125 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2126 tmp &= ~TCC_CCBUF_DITH5_CCBUF_Msk;
2127 tmp |= TCC_CCBUF_DITH5_CCBUF(data);
2128 ((Tcc *)hw)->CCBUF[index].reg = tmp;
2129 TCC_CRITICAL_SECTION_LEAVE();
2130 }
2131
hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2132 static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2133 {
2134 TCC_CRITICAL_SECTION_ENTER();
2135 ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_CCBUF(mask);
2136 TCC_CRITICAL_SECTION_LEAVE();
2137 }
2138
hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2139 static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2140 {
2141 TCC_CRITICAL_SECTION_ENTER();
2142 ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_CCBUF(mask);
2143 TCC_CRITICAL_SECTION_LEAVE();
2144 }
2145
hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void * const hw,uint8_t index)2146 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index)
2147 {
2148 uint32_t tmp;
2149 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2150 tmp = (tmp & TCC_CCBUF_DITH5_CCBUF_Msk) >> TCC_CCBUF_DITH5_CCBUF_Pos;
2151 return tmp;
2152 }
2153
hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2154 static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2155 {
2156 TCC_CRITICAL_SECTION_ENTER();
2157 ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask);
2158 TCC_CRITICAL_SECTION_LEAVE();
2159 }
2160
hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2161 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
2162 hri_tcc_ccbuf_reg_t mask)
2163 {
2164 uint32_t tmp;
2165 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2166 tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
2167 return tmp;
2168 }
2169
hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)2170 static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
2171 {
2172 uint32_t tmp;
2173 TCC_CRITICAL_SECTION_ENTER();
2174 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2175 tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk;
2176 tmp |= TCC_CCBUF_DITH6_DITHERBUF(data);
2177 ((Tcc *)hw)->CCBUF[index].reg = tmp;
2178 TCC_CRITICAL_SECTION_LEAVE();
2179 }
2180
hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2181 static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2182 {
2183 TCC_CRITICAL_SECTION_ENTER();
2184 ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask);
2185 TCC_CRITICAL_SECTION_LEAVE();
2186 }
2187
hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2188 static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index,
2189 hri_tcc_ccbuf_reg_t mask)
2190 {
2191 TCC_CRITICAL_SECTION_ENTER();
2192 ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask);
2193 TCC_CRITICAL_SECTION_LEAVE();
2194 }
2195
hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void * const hw,uint8_t index)2196 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index)
2197 {
2198 uint32_t tmp;
2199 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2200 tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos;
2201 return tmp;
2202 }
2203
hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2204 static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2205 {
2206 TCC_CRITICAL_SECTION_ENTER();
2207 ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_CCBUF(mask);
2208 TCC_CRITICAL_SECTION_LEAVE();
2209 }
2210
hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2211 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index,
2212 hri_tcc_ccbuf_reg_t mask)
2213 {
2214 uint32_t tmp;
2215 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2216 tmp = (tmp & TCC_CCBUF_DITH6_CCBUF(mask)) >> TCC_CCBUF_DITH6_CCBUF_Pos;
2217 return tmp;
2218 }
2219
hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)2220 static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
2221 {
2222 uint32_t tmp;
2223 TCC_CRITICAL_SECTION_ENTER();
2224 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2225 tmp &= ~TCC_CCBUF_DITH6_CCBUF_Msk;
2226 tmp |= TCC_CCBUF_DITH6_CCBUF(data);
2227 ((Tcc *)hw)->CCBUF[index].reg = tmp;
2228 TCC_CRITICAL_SECTION_LEAVE();
2229 }
2230
hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2231 static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2232 {
2233 TCC_CRITICAL_SECTION_ENTER();
2234 ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_CCBUF(mask);
2235 TCC_CRITICAL_SECTION_LEAVE();
2236 }
2237
hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2238 static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2239 {
2240 TCC_CRITICAL_SECTION_ENTER();
2241 ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_CCBUF(mask);
2242 TCC_CRITICAL_SECTION_LEAVE();
2243 }
2244
hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void * const hw,uint8_t index)2245 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index)
2246 {
2247 uint32_t tmp;
2248 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2249 tmp = (tmp & TCC_CCBUF_DITH6_CCBUF_Msk) >> TCC_CCBUF_DITH6_CCBUF_Pos;
2250 return tmp;
2251 }
2252
hri_tcc_set_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2253 static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2254 {
2255 TCC_CRITICAL_SECTION_ENTER();
2256 ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask);
2257 TCC_CRITICAL_SECTION_LEAVE();
2258 }
2259
hri_tcc_get_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2260 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index,
2261 hri_tcc_ccbuf_reg_t mask)
2262 {
2263 uint32_t tmp;
2264 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2265 tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos;
2266 return tmp;
2267 }
2268
hri_tcc_write_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)2269 static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
2270 {
2271 uint32_t tmp;
2272 TCC_CRITICAL_SECTION_ENTER();
2273 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2274 tmp &= ~TCC_CCBUF_CCBUF_Msk;
2275 tmp |= TCC_CCBUF_CCBUF(data);
2276 ((Tcc *)hw)->CCBUF[index].reg = tmp;
2277 TCC_CRITICAL_SECTION_LEAVE();
2278 }
2279
hri_tcc_clear_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2280 static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2281 {
2282 TCC_CRITICAL_SECTION_ENTER();
2283 ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask);
2284 TCC_CRITICAL_SECTION_LEAVE();
2285 }
2286
hri_tcc_toggle_CCBUF_CCBUF_bf(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2287 static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2288 {
2289 TCC_CRITICAL_SECTION_ENTER();
2290 ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask);
2291 TCC_CRITICAL_SECTION_LEAVE();
2292 }
2293
hri_tcc_read_CCBUF_CCBUF_bf(const void * const hw,uint8_t index)2294 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index)
2295 {
2296 uint32_t tmp;
2297 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2298 tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos;
2299 return tmp;
2300 }
2301
hri_tcc_set_CCBUF_DITH4_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2302 static inline void hri_tcc_set_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2303 {
2304 TCC_CRITICAL_SECTION_ENTER();
2305 ((Tcc *)hw)->CCBUF[index].reg |= mask;
2306 TCC_CRITICAL_SECTION_LEAVE();
2307 }
2308
hri_tcc_get_CCBUF_DITH4_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2309 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_reg(const void *const hw, uint8_t index,
2310 hri_tcc_ccbuf_reg_t mask)
2311 {
2312 uint32_t tmp;
2313 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2314 tmp &= mask;
2315 return tmp;
2316 }
2317
hri_tcc_write_CCBUF_DITH4_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)2318 static inline void hri_tcc_write_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
2319 {
2320 TCC_CRITICAL_SECTION_ENTER();
2321 ((Tcc *)hw)->CCBUF[index].reg = data;
2322 TCC_CRITICAL_SECTION_LEAVE();
2323 }
2324
hri_tcc_clear_CCBUF_DITH4_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2325 static inline void hri_tcc_clear_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2326 {
2327 TCC_CRITICAL_SECTION_ENTER();
2328 ((Tcc *)hw)->CCBUF[index].reg &= ~mask;
2329 TCC_CRITICAL_SECTION_LEAVE();
2330 }
2331
hri_tcc_toggle_CCBUF_DITH4_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2332 static inline void hri_tcc_toggle_CCBUF_DITH4_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2333 {
2334 TCC_CRITICAL_SECTION_ENTER();
2335 ((Tcc *)hw)->CCBUF[index].reg ^= mask;
2336 TCC_CRITICAL_SECTION_LEAVE();
2337 }
2338
hri_tcc_read_CCBUF_DITH4_reg(const void * const hw,uint8_t index)2339 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_reg(const void *const hw, uint8_t index)
2340 {
2341 return ((Tcc *)hw)->CCBUF[index].reg;
2342 }
2343
hri_tcc_set_CCBUF_DITH5_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2344 static inline void hri_tcc_set_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2345 {
2346 TCC_CRITICAL_SECTION_ENTER();
2347 ((Tcc *)hw)->CCBUF[index].reg |= mask;
2348 TCC_CRITICAL_SECTION_LEAVE();
2349 }
2350
hri_tcc_get_CCBUF_DITH5_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2351 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_reg(const void *const hw, uint8_t index,
2352 hri_tcc_ccbuf_reg_t mask)
2353 {
2354 uint32_t tmp;
2355 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2356 tmp &= mask;
2357 return tmp;
2358 }
2359
hri_tcc_write_CCBUF_DITH5_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)2360 static inline void hri_tcc_write_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
2361 {
2362 TCC_CRITICAL_SECTION_ENTER();
2363 ((Tcc *)hw)->CCBUF[index].reg = data;
2364 TCC_CRITICAL_SECTION_LEAVE();
2365 }
2366
hri_tcc_clear_CCBUF_DITH5_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2367 static inline void hri_tcc_clear_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2368 {
2369 TCC_CRITICAL_SECTION_ENTER();
2370 ((Tcc *)hw)->CCBUF[index].reg &= ~mask;
2371 TCC_CRITICAL_SECTION_LEAVE();
2372 }
2373
hri_tcc_toggle_CCBUF_DITH5_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2374 static inline void hri_tcc_toggle_CCBUF_DITH5_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2375 {
2376 TCC_CRITICAL_SECTION_ENTER();
2377 ((Tcc *)hw)->CCBUF[index].reg ^= mask;
2378 TCC_CRITICAL_SECTION_LEAVE();
2379 }
2380
hri_tcc_read_CCBUF_DITH5_reg(const void * const hw,uint8_t index)2381 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_reg(const void *const hw, uint8_t index)
2382 {
2383 return ((Tcc *)hw)->CCBUF[index].reg;
2384 }
2385
hri_tcc_set_CCBUF_DITH6_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2386 static inline void hri_tcc_set_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2387 {
2388 TCC_CRITICAL_SECTION_ENTER();
2389 ((Tcc *)hw)->CCBUF[index].reg |= mask;
2390 TCC_CRITICAL_SECTION_LEAVE();
2391 }
2392
hri_tcc_get_CCBUF_DITH6_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2393 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_reg(const void *const hw, uint8_t index,
2394 hri_tcc_ccbuf_reg_t mask)
2395 {
2396 uint32_t tmp;
2397 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2398 tmp &= mask;
2399 return tmp;
2400 }
2401
hri_tcc_write_CCBUF_DITH6_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)2402 static inline void hri_tcc_write_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
2403 {
2404 TCC_CRITICAL_SECTION_ENTER();
2405 ((Tcc *)hw)->CCBUF[index].reg = data;
2406 TCC_CRITICAL_SECTION_LEAVE();
2407 }
2408
hri_tcc_clear_CCBUF_DITH6_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2409 static inline void hri_tcc_clear_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2410 {
2411 TCC_CRITICAL_SECTION_ENTER();
2412 ((Tcc *)hw)->CCBUF[index].reg &= ~mask;
2413 TCC_CRITICAL_SECTION_LEAVE();
2414 }
2415
hri_tcc_toggle_CCBUF_DITH6_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2416 static inline void hri_tcc_toggle_CCBUF_DITH6_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2417 {
2418 TCC_CRITICAL_SECTION_ENTER();
2419 ((Tcc *)hw)->CCBUF[index].reg ^= mask;
2420 TCC_CRITICAL_SECTION_LEAVE();
2421 }
2422
hri_tcc_read_CCBUF_DITH6_reg(const void * const hw,uint8_t index)2423 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_reg(const void *const hw, uint8_t index)
2424 {
2425 return ((Tcc *)hw)->CCBUF[index].reg;
2426 }
2427
hri_tcc_set_CCBUF_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2428 static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2429 {
2430 TCC_CRITICAL_SECTION_ENTER();
2431 ((Tcc *)hw)->CCBUF[index].reg |= mask;
2432 TCC_CRITICAL_SECTION_LEAVE();
2433 }
2434
hri_tcc_get_CCBUF_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2435 static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2436 {
2437 uint32_t tmp;
2438 tmp = ((Tcc *)hw)->CCBUF[index].reg;
2439 tmp &= mask;
2440 return tmp;
2441 }
2442
hri_tcc_write_CCBUF_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t data)2443 static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data)
2444 {
2445 TCC_CRITICAL_SECTION_ENTER();
2446 ((Tcc *)hw)->CCBUF[index].reg = data;
2447 TCC_CRITICAL_SECTION_LEAVE();
2448 }
2449
hri_tcc_clear_CCBUF_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2450 static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2451 {
2452 TCC_CRITICAL_SECTION_ENTER();
2453 ((Tcc *)hw)->CCBUF[index].reg &= ~mask;
2454 TCC_CRITICAL_SECTION_LEAVE();
2455 }
2456
hri_tcc_toggle_CCBUF_reg(const void * const hw,uint8_t index,hri_tcc_ccbuf_reg_t mask)2457 static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask)
2458 {
2459 TCC_CRITICAL_SECTION_ENTER();
2460 ((Tcc *)hw)->CCBUF[index].reg ^= mask;
2461 TCC_CRITICAL_SECTION_LEAVE();
2462 }
2463
hri_tcc_read_CCBUF_reg(const void * const hw,uint8_t index)2464 static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index)
2465 {
2466 return ((Tcc *)hw)->CCBUF[index].reg;
2467 }
2468
hri_tcc_set_CTRLB_DIR_bit(const void * const hw)2469 static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw)
2470 {
2471 ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
2472 }
2473
hri_tcc_get_CTRLB_DIR_bit(const void * const hw)2474 static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw)
2475 {
2476 return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos;
2477 }
2478
hri_tcc_write_CTRLB_DIR_bit(const void * const hw,bool value)2479 static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value)
2480 {
2481 if (value == 0x0) {
2482 ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
2483 } else {
2484 ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR;
2485 }
2486 }
2487
hri_tcc_clear_CTRLB_DIR_bit(const void * const hw)2488 static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw)
2489 {
2490 ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR;
2491 }
2492
hri_tcc_set_CTRLB_LUPD_bit(const void * const hw)2493 static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw)
2494 {
2495 ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
2496 }
2497
hri_tcc_get_CTRLB_LUPD_bit(const void * const hw)2498 static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw)
2499 {
2500 return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos;
2501 }
2502
hri_tcc_write_CTRLB_LUPD_bit(const void * const hw,bool value)2503 static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value)
2504 {
2505 if (value == 0x0) {
2506 ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
2507 } else {
2508 ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD;
2509 }
2510 }
2511
hri_tcc_clear_CTRLB_LUPD_bit(const void * const hw)2512 static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw)
2513 {
2514 ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD;
2515 }
2516
hri_tcc_set_CTRLB_ONESHOT_bit(const void * const hw)2517 static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw)
2518 {
2519 ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
2520 }
2521
hri_tcc_get_CTRLB_ONESHOT_bit(const void * const hw)2522 static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw)
2523 {
2524 return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos;
2525 }
2526
hri_tcc_write_CTRLB_ONESHOT_bit(const void * const hw,bool value)2527 static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value)
2528 {
2529 if (value == 0x0) {
2530 ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
2531 } else {
2532 ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT;
2533 }
2534 }
2535
hri_tcc_clear_CTRLB_ONESHOT_bit(const void * const hw)2536 static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw)
2537 {
2538 ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT;
2539 }
2540
hri_tcc_set_CTRLB_IDXCMD_bf(const void * const hw,hri_tcc_ctrlbset_reg_t mask)2541 static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
2542 {
2543 ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask);
2544 }
2545
hri_tcc_get_CTRLB_IDXCMD_bf(const void * const hw,hri_tcc_ctrlbset_reg_t mask)2546 static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
2547 {
2548 uint8_t tmp;
2549 tmp = ((Tcc *)hw)->CTRLBSET.reg;
2550 tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos;
2551 return tmp;
2552 }
2553
hri_tcc_read_CTRLB_IDXCMD_bf(const void * const hw)2554 static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw)
2555 {
2556 uint8_t tmp;
2557 tmp = ((Tcc *)hw)->CTRLBSET.reg;
2558 tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos;
2559 return tmp;
2560 }
2561
hri_tcc_write_CTRLB_IDXCMD_bf(const void * const hw,hri_tcc_ctrlbset_reg_t data)2562 static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
2563 {
2564 ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data);
2565 ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data);
2566 }
2567
hri_tcc_clear_CTRLB_IDXCMD_bf(const void * const hw,hri_tcc_ctrlbset_reg_t mask)2568 static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
2569 {
2570 ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask);
2571 }
2572
hri_tcc_set_CTRLB_CMD_bf(const void * const hw,hri_tcc_ctrlbset_reg_t mask)2573 static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
2574 {
2575 ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask);
2576 }
2577
hri_tcc_get_CTRLB_CMD_bf(const void * const hw,hri_tcc_ctrlbset_reg_t mask)2578 static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
2579 {
2580 uint8_t tmp;
2581 tmp = ((Tcc *)hw)->CTRLBSET.reg;
2582 tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos;
2583 return tmp;
2584 }
2585
hri_tcc_read_CTRLB_CMD_bf(const void * const hw)2586 static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw)
2587 {
2588 uint8_t tmp;
2589 tmp = ((Tcc *)hw)->CTRLBSET.reg;
2590 tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos;
2591 return tmp;
2592 }
2593
hri_tcc_write_CTRLB_CMD_bf(const void * const hw,hri_tcc_ctrlbset_reg_t data)2594 static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data)
2595 {
2596 ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data);
2597 ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data);
2598 }
2599
hri_tcc_clear_CTRLB_CMD_bf(const void * const hw,hri_tcc_ctrlbset_reg_t mask)2600 static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
2601 {
2602 ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask);
2603 }
2604
hri_tcc_set_CTRLB_reg(const void * const hw,hri_tcc_ctrlbset_reg_t mask)2605 static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
2606 {
2607 ((Tcc *)hw)->CTRLBSET.reg = mask;
2608 }
2609
hri_tcc_get_CTRLB_reg(const void * const hw,hri_tcc_ctrlbset_reg_t mask)2610 static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
2611 {
2612 uint8_t tmp;
2613 tmp = ((Tcc *)hw)->CTRLBSET.reg;
2614 tmp &= mask;
2615 return tmp;
2616 }
2617
hri_tcc_read_CTRLB_reg(const void * const hw)2618 static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw)
2619 {
2620 return ((Tcc *)hw)->CTRLBSET.reg;
2621 }
2622
hri_tcc_write_CTRLB_reg(const void * const hw,hri_tcc_ctrlbset_reg_t data)2623 static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data)
2624 {
2625 ((Tcc *)hw)->CTRLBSET.reg = data;
2626 ((Tcc *)hw)->CTRLBCLR.reg = ~data;
2627 }
2628
hri_tcc_clear_CTRLB_reg(const void * const hw,hri_tcc_ctrlbset_reg_t mask)2629 static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask)
2630 {
2631 ((Tcc *)hw)->CTRLBCLR.reg = mask;
2632 }
2633
hri_tcc_set_INTEN_OVF_bit(const void * const hw)2634 static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw)
2635 {
2636 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
2637 }
2638
hri_tcc_get_INTEN_OVF_bit(const void * const hw)2639 static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw)
2640 {
2641 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos;
2642 }
2643
hri_tcc_write_INTEN_OVF_bit(const void * const hw,bool value)2644 static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value)
2645 {
2646 if (value == 0x0) {
2647 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
2648 } else {
2649 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF;
2650 }
2651 }
2652
hri_tcc_clear_INTEN_OVF_bit(const void * const hw)2653 static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw)
2654 {
2655 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF;
2656 }
2657
hri_tcc_set_INTEN_TRG_bit(const void * const hw)2658 static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw)
2659 {
2660 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
2661 }
2662
hri_tcc_get_INTEN_TRG_bit(const void * const hw)2663 static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw)
2664 {
2665 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos;
2666 }
2667
hri_tcc_write_INTEN_TRG_bit(const void * const hw,bool value)2668 static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value)
2669 {
2670 if (value == 0x0) {
2671 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
2672 } else {
2673 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG;
2674 }
2675 }
2676
hri_tcc_clear_INTEN_TRG_bit(const void * const hw)2677 static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw)
2678 {
2679 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG;
2680 }
2681
hri_tcc_set_INTEN_CNT_bit(const void * const hw)2682 static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw)
2683 {
2684 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
2685 }
2686
hri_tcc_get_INTEN_CNT_bit(const void * const hw)2687 static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw)
2688 {
2689 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos;
2690 }
2691
hri_tcc_write_INTEN_CNT_bit(const void * const hw,bool value)2692 static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value)
2693 {
2694 if (value == 0x0) {
2695 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
2696 } else {
2697 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT;
2698 }
2699 }
2700
hri_tcc_clear_INTEN_CNT_bit(const void * const hw)2701 static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw)
2702 {
2703 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT;
2704 }
2705
hri_tcc_set_INTEN_ERR_bit(const void * const hw)2706 static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw)
2707 {
2708 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
2709 }
2710
hri_tcc_get_INTEN_ERR_bit(const void * const hw)2711 static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw)
2712 {
2713 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos;
2714 }
2715
hri_tcc_write_INTEN_ERR_bit(const void * const hw,bool value)2716 static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value)
2717 {
2718 if (value == 0x0) {
2719 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
2720 } else {
2721 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR;
2722 }
2723 }
2724
hri_tcc_clear_INTEN_ERR_bit(const void * const hw)2725 static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw)
2726 {
2727 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR;
2728 }
2729
hri_tcc_set_INTEN_UFS_bit(const void * const hw)2730 static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw)
2731 {
2732 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
2733 }
2734
hri_tcc_get_INTEN_UFS_bit(const void * const hw)2735 static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw)
2736 {
2737 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos;
2738 }
2739
hri_tcc_write_INTEN_UFS_bit(const void * const hw,bool value)2740 static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value)
2741 {
2742 if (value == 0x0) {
2743 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
2744 } else {
2745 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS;
2746 }
2747 }
2748
hri_tcc_clear_INTEN_UFS_bit(const void * const hw)2749 static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw)
2750 {
2751 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS;
2752 }
2753
hri_tcc_set_INTEN_DFS_bit(const void * const hw)2754 static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw)
2755 {
2756 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
2757 }
2758
hri_tcc_get_INTEN_DFS_bit(const void * const hw)2759 static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw)
2760 {
2761 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos;
2762 }
2763
hri_tcc_write_INTEN_DFS_bit(const void * const hw,bool value)2764 static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value)
2765 {
2766 if (value == 0x0) {
2767 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
2768 } else {
2769 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS;
2770 }
2771 }
2772
hri_tcc_clear_INTEN_DFS_bit(const void * const hw)2773 static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw)
2774 {
2775 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS;
2776 }
2777
hri_tcc_set_INTEN_FAULTA_bit(const void * const hw)2778 static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw)
2779 {
2780 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
2781 }
2782
hri_tcc_get_INTEN_FAULTA_bit(const void * const hw)2783 static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw)
2784 {
2785 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos;
2786 }
2787
hri_tcc_write_INTEN_FAULTA_bit(const void * const hw,bool value)2788 static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value)
2789 {
2790 if (value == 0x0) {
2791 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
2792 } else {
2793 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA;
2794 }
2795 }
2796
hri_tcc_clear_INTEN_FAULTA_bit(const void * const hw)2797 static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw)
2798 {
2799 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA;
2800 }
2801
hri_tcc_set_INTEN_FAULTB_bit(const void * const hw)2802 static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw)
2803 {
2804 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
2805 }
2806
hri_tcc_get_INTEN_FAULTB_bit(const void * const hw)2807 static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw)
2808 {
2809 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos;
2810 }
2811
hri_tcc_write_INTEN_FAULTB_bit(const void * const hw,bool value)2812 static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value)
2813 {
2814 if (value == 0x0) {
2815 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
2816 } else {
2817 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB;
2818 }
2819 }
2820
hri_tcc_clear_INTEN_FAULTB_bit(const void * const hw)2821 static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw)
2822 {
2823 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB;
2824 }
2825
hri_tcc_set_INTEN_FAULT0_bit(const void * const hw)2826 static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw)
2827 {
2828 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
2829 }
2830
hri_tcc_get_INTEN_FAULT0_bit(const void * const hw)2831 static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw)
2832 {
2833 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos;
2834 }
2835
hri_tcc_write_INTEN_FAULT0_bit(const void * const hw,bool value)2836 static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value)
2837 {
2838 if (value == 0x0) {
2839 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
2840 } else {
2841 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0;
2842 }
2843 }
2844
hri_tcc_clear_INTEN_FAULT0_bit(const void * const hw)2845 static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw)
2846 {
2847 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0;
2848 }
2849
hri_tcc_set_INTEN_FAULT1_bit(const void * const hw)2850 static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw)
2851 {
2852 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
2853 }
2854
hri_tcc_get_INTEN_FAULT1_bit(const void * const hw)2855 static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw)
2856 {
2857 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos;
2858 }
2859
hri_tcc_write_INTEN_FAULT1_bit(const void * const hw,bool value)2860 static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value)
2861 {
2862 if (value == 0x0) {
2863 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
2864 } else {
2865 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1;
2866 }
2867 }
2868
hri_tcc_clear_INTEN_FAULT1_bit(const void * const hw)2869 static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw)
2870 {
2871 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1;
2872 }
2873
hri_tcc_set_INTEN_MC0_bit(const void * const hw)2874 static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw)
2875 {
2876 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
2877 }
2878
hri_tcc_get_INTEN_MC0_bit(const void * const hw)2879 static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw)
2880 {
2881 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos;
2882 }
2883
hri_tcc_write_INTEN_MC0_bit(const void * const hw,bool value)2884 static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value)
2885 {
2886 if (value == 0x0) {
2887 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
2888 } else {
2889 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0;
2890 }
2891 }
2892
hri_tcc_clear_INTEN_MC0_bit(const void * const hw)2893 static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw)
2894 {
2895 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0;
2896 }
2897
hri_tcc_set_INTEN_MC1_bit(const void * const hw)2898 static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw)
2899 {
2900 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
2901 }
2902
hri_tcc_get_INTEN_MC1_bit(const void * const hw)2903 static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw)
2904 {
2905 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos;
2906 }
2907
hri_tcc_write_INTEN_MC1_bit(const void * const hw,bool value)2908 static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value)
2909 {
2910 if (value == 0x0) {
2911 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
2912 } else {
2913 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1;
2914 }
2915 }
2916
hri_tcc_clear_INTEN_MC1_bit(const void * const hw)2917 static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw)
2918 {
2919 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1;
2920 }
2921
hri_tcc_set_INTEN_MC2_bit(const void * const hw)2922 static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw)
2923 {
2924 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
2925 }
2926
hri_tcc_get_INTEN_MC2_bit(const void * const hw)2927 static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw)
2928 {
2929 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos;
2930 }
2931
hri_tcc_write_INTEN_MC2_bit(const void * const hw,bool value)2932 static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value)
2933 {
2934 if (value == 0x0) {
2935 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
2936 } else {
2937 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2;
2938 }
2939 }
2940
hri_tcc_clear_INTEN_MC2_bit(const void * const hw)2941 static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw)
2942 {
2943 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2;
2944 }
2945
hri_tcc_set_INTEN_MC3_bit(const void * const hw)2946 static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw)
2947 {
2948 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
2949 }
2950
hri_tcc_get_INTEN_MC3_bit(const void * const hw)2951 static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw)
2952 {
2953 return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos;
2954 }
2955
hri_tcc_write_INTEN_MC3_bit(const void * const hw,bool value)2956 static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value)
2957 {
2958 if (value == 0x0) {
2959 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
2960 } else {
2961 ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3;
2962 }
2963 }
2964
hri_tcc_clear_INTEN_MC3_bit(const void * const hw)2965 static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw)
2966 {
2967 ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3;
2968 }
2969
hri_tcc_set_INTEN_reg(const void * const hw,hri_tcc_intenset_reg_t mask)2970 static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
2971 {
2972 ((Tcc *)hw)->INTENSET.reg = mask;
2973 }
2974
hri_tcc_get_INTEN_reg(const void * const hw,hri_tcc_intenset_reg_t mask)2975 static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
2976 {
2977 uint32_t tmp;
2978 tmp = ((Tcc *)hw)->INTENSET.reg;
2979 tmp &= mask;
2980 return tmp;
2981 }
2982
hri_tcc_read_INTEN_reg(const void * const hw)2983 static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw)
2984 {
2985 return ((Tcc *)hw)->INTENSET.reg;
2986 }
2987
hri_tcc_write_INTEN_reg(const void * const hw,hri_tcc_intenset_reg_t data)2988 static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data)
2989 {
2990 ((Tcc *)hw)->INTENSET.reg = data;
2991 ((Tcc *)hw)->INTENCLR.reg = ~data;
2992 }
2993
hri_tcc_clear_INTEN_reg(const void * const hw,hri_tcc_intenset_reg_t mask)2994 static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask)
2995 {
2996 ((Tcc *)hw)->INTENCLR.reg = mask;
2997 }
2998
hri_tcc_get_INTFLAG_OVF_bit(const void * const hw)2999 static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw)
3000 {
3001 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
3002 }
3003
hri_tcc_clear_INTFLAG_OVF_bit(const void * const hw)3004 static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw)
3005 {
3006 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
3007 }
3008
hri_tcc_get_INTFLAG_TRG_bit(const void * const hw)3009 static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw)
3010 {
3011 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
3012 }
3013
hri_tcc_clear_INTFLAG_TRG_bit(const void * const hw)3014 static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw)
3015 {
3016 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
3017 }
3018
hri_tcc_get_INTFLAG_CNT_bit(const void * const hw)3019 static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw)
3020 {
3021 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
3022 }
3023
hri_tcc_clear_INTFLAG_CNT_bit(const void * const hw)3024 static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw)
3025 {
3026 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
3027 }
3028
hri_tcc_get_INTFLAG_ERR_bit(const void * const hw)3029 static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw)
3030 {
3031 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
3032 }
3033
hri_tcc_clear_INTFLAG_ERR_bit(const void * const hw)3034 static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw)
3035 {
3036 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
3037 }
3038
hri_tcc_get_INTFLAG_UFS_bit(const void * const hw)3039 static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw)
3040 {
3041 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
3042 }
3043
hri_tcc_clear_INTFLAG_UFS_bit(const void * const hw)3044 static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw)
3045 {
3046 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
3047 }
3048
hri_tcc_get_INTFLAG_DFS_bit(const void * const hw)3049 static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw)
3050 {
3051 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
3052 }
3053
hri_tcc_clear_INTFLAG_DFS_bit(const void * const hw)3054 static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw)
3055 {
3056 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
3057 }
3058
hri_tcc_get_INTFLAG_FAULTA_bit(const void * const hw)3059 static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw)
3060 {
3061 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
3062 }
3063
hri_tcc_clear_INTFLAG_FAULTA_bit(const void * const hw)3064 static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw)
3065 {
3066 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
3067 }
3068
hri_tcc_get_INTFLAG_FAULTB_bit(const void * const hw)3069 static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw)
3070 {
3071 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
3072 }
3073
hri_tcc_clear_INTFLAG_FAULTB_bit(const void * const hw)3074 static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw)
3075 {
3076 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
3077 }
3078
hri_tcc_get_INTFLAG_FAULT0_bit(const void * const hw)3079 static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw)
3080 {
3081 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
3082 }
3083
hri_tcc_clear_INTFLAG_FAULT0_bit(const void * const hw)3084 static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw)
3085 {
3086 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
3087 }
3088
hri_tcc_get_INTFLAG_FAULT1_bit(const void * const hw)3089 static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw)
3090 {
3091 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
3092 }
3093
hri_tcc_clear_INTFLAG_FAULT1_bit(const void * const hw)3094 static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw)
3095 {
3096 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
3097 }
3098
hri_tcc_get_INTFLAG_MC0_bit(const void * const hw)3099 static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw)
3100 {
3101 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
3102 }
3103
hri_tcc_clear_INTFLAG_MC0_bit(const void * const hw)3104 static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw)
3105 {
3106 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
3107 }
3108
hri_tcc_get_INTFLAG_MC1_bit(const void * const hw)3109 static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw)
3110 {
3111 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
3112 }
3113
hri_tcc_clear_INTFLAG_MC1_bit(const void * const hw)3114 static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw)
3115 {
3116 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
3117 }
3118
hri_tcc_get_INTFLAG_MC2_bit(const void * const hw)3119 static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw)
3120 {
3121 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
3122 }
3123
hri_tcc_clear_INTFLAG_MC2_bit(const void * const hw)3124 static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw)
3125 {
3126 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
3127 }
3128
hri_tcc_get_INTFLAG_MC3_bit(const void * const hw)3129 static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw)
3130 {
3131 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
3132 }
3133
hri_tcc_clear_INTFLAG_MC3_bit(const void * const hw)3134 static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw)
3135 {
3136 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
3137 }
3138
hri_tcc_get_interrupt_OVF_bit(const void * const hw)3139 static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw)
3140 {
3141 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos;
3142 }
3143
hri_tcc_clear_interrupt_OVF_bit(const void * const hw)3144 static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw)
3145 {
3146 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF;
3147 }
3148
hri_tcc_get_interrupt_TRG_bit(const void * const hw)3149 static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw)
3150 {
3151 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos;
3152 }
3153
hri_tcc_clear_interrupt_TRG_bit(const void * const hw)3154 static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw)
3155 {
3156 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG;
3157 }
3158
hri_tcc_get_interrupt_CNT_bit(const void * const hw)3159 static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw)
3160 {
3161 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos;
3162 }
3163
hri_tcc_clear_interrupt_CNT_bit(const void * const hw)3164 static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw)
3165 {
3166 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT;
3167 }
3168
hri_tcc_get_interrupt_ERR_bit(const void * const hw)3169 static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw)
3170 {
3171 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos;
3172 }
3173
hri_tcc_clear_interrupt_ERR_bit(const void * const hw)3174 static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw)
3175 {
3176 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR;
3177 }
3178
hri_tcc_get_interrupt_UFS_bit(const void * const hw)3179 static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw)
3180 {
3181 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos;
3182 }
3183
hri_tcc_clear_interrupt_UFS_bit(const void * const hw)3184 static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw)
3185 {
3186 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS;
3187 }
3188
hri_tcc_get_interrupt_DFS_bit(const void * const hw)3189 static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw)
3190 {
3191 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos;
3192 }
3193
hri_tcc_clear_interrupt_DFS_bit(const void * const hw)3194 static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw)
3195 {
3196 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS;
3197 }
3198
hri_tcc_get_interrupt_FAULTA_bit(const void * const hw)3199 static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw)
3200 {
3201 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos;
3202 }
3203
hri_tcc_clear_interrupt_FAULTA_bit(const void * const hw)3204 static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw)
3205 {
3206 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA;
3207 }
3208
hri_tcc_get_interrupt_FAULTB_bit(const void * const hw)3209 static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw)
3210 {
3211 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos;
3212 }
3213
hri_tcc_clear_interrupt_FAULTB_bit(const void * const hw)3214 static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw)
3215 {
3216 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB;
3217 }
3218
hri_tcc_get_interrupt_FAULT0_bit(const void * const hw)3219 static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw)
3220 {
3221 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos;
3222 }
3223
hri_tcc_clear_interrupt_FAULT0_bit(const void * const hw)3224 static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw)
3225 {
3226 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0;
3227 }
3228
hri_tcc_get_interrupt_FAULT1_bit(const void * const hw)3229 static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw)
3230 {
3231 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos;
3232 }
3233
hri_tcc_clear_interrupt_FAULT1_bit(const void * const hw)3234 static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw)
3235 {
3236 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1;
3237 }
3238
hri_tcc_get_interrupt_MC0_bit(const void * const hw)3239 static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw)
3240 {
3241 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos;
3242 }
3243
hri_tcc_clear_interrupt_MC0_bit(const void * const hw)3244 static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw)
3245 {
3246 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0;
3247 }
3248
hri_tcc_get_interrupt_MC1_bit(const void * const hw)3249 static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw)
3250 {
3251 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos;
3252 }
3253
hri_tcc_clear_interrupt_MC1_bit(const void * const hw)3254 static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw)
3255 {
3256 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1;
3257 }
3258
hri_tcc_get_interrupt_MC2_bit(const void * const hw)3259 static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw)
3260 {
3261 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos;
3262 }
3263
hri_tcc_clear_interrupt_MC2_bit(const void * const hw)3264 static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw)
3265 {
3266 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2;
3267 }
3268
hri_tcc_get_interrupt_MC3_bit(const void * const hw)3269 static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw)
3270 {
3271 return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos;
3272 }
3273
hri_tcc_clear_interrupt_MC3_bit(const void * const hw)3274 static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw)
3275 {
3276 ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3;
3277 }
3278
hri_tcc_get_INTFLAG_reg(const void * const hw,hri_tcc_intflag_reg_t mask)3279 static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
3280 {
3281 uint32_t tmp;
3282 tmp = ((Tcc *)hw)->INTFLAG.reg;
3283 tmp &= mask;
3284 return tmp;
3285 }
3286
hri_tcc_read_INTFLAG_reg(const void * const hw)3287 static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw)
3288 {
3289 return ((Tcc *)hw)->INTFLAG.reg;
3290 }
3291
hri_tcc_clear_INTFLAG_reg(const void * const hw,hri_tcc_intflag_reg_t mask)3292 static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask)
3293 {
3294 ((Tcc *)hw)->INTFLAG.reg = mask;
3295 }
3296
hri_tcc_set_CTRLA_SWRST_bit(const void * const hw)3297 static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw)
3298 {
3299 TCC_CRITICAL_SECTION_ENTER();
3300 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
3301 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST;
3302 TCC_CRITICAL_SECTION_LEAVE();
3303 }
3304
hri_tcc_get_CTRLA_SWRST_bit(const void * const hw)3305 static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw)
3306 {
3307 uint32_t tmp;
3308 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST);
3309 tmp = ((Tcc *)hw)->CTRLA.reg;
3310 tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos;
3311 return (bool)tmp;
3312 }
3313
hri_tcc_set_CTRLA_ENABLE_bit(const void * const hw)3314 static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw)
3315 {
3316 TCC_CRITICAL_SECTION_ENTER();
3317 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
3318 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE;
3319 TCC_CRITICAL_SECTION_LEAVE();
3320 }
3321
hri_tcc_get_CTRLA_ENABLE_bit(const void * const hw)3322 static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw)
3323 {
3324 uint32_t tmp;
3325 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
3326 tmp = ((Tcc *)hw)->CTRLA.reg;
3327 tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos;
3328 return (bool)tmp;
3329 }
3330
hri_tcc_write_CTRLA_ENABLE_bit(const void * const hw,bool value)3331 static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
3332 {
3333 uint32_t tmp;
3334 TCC_CRITICAL_SECTION_ENTER();
3335 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
3336 tmp = ((Tcc *)hw)->CTRLA.reg;
3337 tmp &= ~TCC_CTRLA_ENABLE;
3338 tmp |= value << TCC_CTRLA_ENABLE_Pos;
3339 ((Tcc *)hw)->CTRLA.reg = tmp;
3340 TCC_CRITICAL_SECTION_LEAVE();
3341 }
3342
hri_tcc_clear_CTRLA_ENABLE_bit(const void * const hw)3343 static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw)
3344 {
3345 TCC_CRITICAL_SECTION_ENTER();
3346 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
3347 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE;
3348 TCC_CRITICAL_SECTION_LEAVE();
3349 }
3350
hri_tcc_toggle_CTRLA_ENABLE_bit(const void * const hw)3351 static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw)
3352 {
3353 TCC_CRITICAL_SECTION_ENTER();
3354 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE);
3355 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE;
3356 TCC_CRITICAL_SECTION_LEAVE();
3357 }
3358
hri_tcc_set_CTRLA_RUNSTDBY_bit(const void * const hw)3359 static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw)
3360 {
3361 TCC_CRITICAL_SECTION_ENTER();
3362 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3363 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY;
3364 TCC_CRITICAL_SECTION_LEAVE();
3365 }
3366
hri_tcc_get_CTRLA_RUNSTDBY_bit(const void * const hw)3367 static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw)
3368 {
3369 uint32_t tmp;
3370 tmp = ((Tcc *)hw)->CTRLA.reg;
3371 tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos;
3372 return (bool)tmp;
3373 }
3374
hri_tcc_write_CTRLA_RUNSTDBY_bit(const void * const hw,bool value)3375 static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value)
3376 {
3377 uint32_t tmp;
3378 TCC_CRITICAL_SECTION_ENTER();
3379 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3380 tmp = ((Tcc *)hw)->CTRLA.reg;
3381 tmp &= ~TCC_CTRLA_RUNSTDBY;
3382 tmp |= value << TCC_CTRLA_RUNSTDBY_Pos;
3383 ((Tcc *)hw)->CTRLA.reg = tmp;
3384 TCC_CRITICAL_SECTION_LEAVE();
3385 }
3386
hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void * const hw)3387 static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw)
3388 {
3389 TCC_CRITICAL_SECTION_ENTER();
3390 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3391 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY;
3392 TCC_CRITICAL_SECTION_LEAVE();
3393 }
3394
hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void * const hw)3395 static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw)
3396 {
3397 TCC_CRITICAL_SECTION_ENTER();
3398 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3399 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY;
3400 TCC_CRITICAL_SECTION_LEAVE();
3401 }
3402
hri_tcc_set_CTRLA_ALOCK_bit(const void * const hw)3403 static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw)
3404 {
3405 TCC_CRITICAL_SECTION_ENTER();
3406 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3407 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK;
3408 TCC_CRITICAL_SECTION_LEAVE();
3409 }
3410
hri_tcc_get_CTRLA_ALOCK_bit(const void * const hw)3411 static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw)
3412 {
3413 uint32_t tmp;
3414 tmp = ((Tcc *)hw)->CTRLA.reg;
3415 tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos;
3416 return (bool)tmp;
3417 }
3418
hri_tcc_write_CTRLA_ALOCK_bit(const void * const hw,bool value)3419 static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value)
3420 {
3421 uint32_t tmp;
3422 TCC_CRITICAL_SECTION_ENTER();
3423 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3424 tmp = ((Tcc *)hw)->CTRLA.reg;
3425 tmp &= ~TCC_CTRLA_ALOCK;
3426 tmp |= value << TCC_CTRLA_ALOCK_Pos;
3427 ((Tcc *)hw)->CTRLA.reg = tmp;
3428 TCC_CRITICAL_SECTION_LEAVE();
3429 }
3430
hri_tcc_clear_CTRLA_ALOCK_bit(const void * const hw)3431 static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw)
3432 {
3433 TCC_CRITICAL_SECTION_ENTER();
3434 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3435 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK;
3436 TCC_CRITICAL_SECTION_LEAVE();
3437 }
3438
hri_tcc_toggle_CTRLA_ALOCK_bit(const void * const hw)3439 static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw)
3440 {
3441 TCC_CRITICAL_SECTION_ENTER();
3442 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3443 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK;
3444 TCC_CRITICAL_SECTION_LEAVE();
3445 }
3446
hri_tcc_set_CTRLA_MSYNC_bit(const void * const hw)3447 static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw)
3448 {
3449 TCC_CRITICAL_SECTION_ENTER();
3450 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3451 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC;
3452 TCC_CRITICAL_SECTION_LEAVE();
3453 }
3454
hri_tcc_get_CTRLA_MSYNC_bit(const void * const hw)3455 static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw)
3456 {
3457 uint32_t tmp;
3458 tmp = ((Tcc *)hw)->CTRLA.reg;
3459 tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos;
3460 return (bool)tmp;
3461 }
3462
hri_tcc_write_CTRLA_MSYNC_bit(const void * const hw,bool value)3463 static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value)
3464 {
3465 uint32_t tmp;
3466 TCC_CRITICAL_SECTION_ENTER();
3467 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3468 tmp = ((Tcc *)hw)->CTRLA.reg;
3469 tmp &= ~TCC_CTRLA_MSYNC;
3470 tmp |= value << TCC_CTRLA_MSYNC_Pos;
3471 ((Tcc *)hw)->CTRLA.reg = tmp;
3472 TCC_CRITICAL_SECTION_LEAVE();
3473 }
3474
hri_tcc_clear_CTRLA_MSYNC_bit(const void * const hw)3475 static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw)
3476 {
3477 TCC_CRITICAL_SECTION_ENTER();
3478 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3479 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC;
3480 TCC_CRITICAL_SECTION_LEAVE();
3481 }
3482
hri_tcc_toggle_CTRLA_MSYNC_bit(const void * const hw)3483 static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw)
3484 {
3485 TCC_CRITICAL_SECTION_ENTER();
3486 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3487 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC;
3488 TCC_CRITICAL_SECTION_LEAVE();
3489 }
3490
hri_tcc_set_CTRLA_DMAOS_bit(const void * const hw)3491 static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw)
3492 {
3493 TCC_CRITICAL_SECTION_ENTER();
3494 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3495 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS;
3496 TCC_CRITICAL_SECTION_LEAVE();
3497 }
3498
hri_tcc_get_CTRLA_DMAOS_bit(const void * const hw)3499 static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw)
3500 {
3501 uint32_t tmp;
3502 tmp = ((Tcc *)hw)->CTRLA.reg;
3503 tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos;
3504 return (bool)tmp;
3505 }
3506
hri_tcc_write_CTRLA_DMAOS_bit(const void * const hw,bool value)3507 static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value)
3508 {
3509 uint32_t tmp;
3510 TCC_CRITICAL_SECTION_ENTER();
3511 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3512 tmp = ((Tcc *)hw)->CTRLA.reg;
3513 tmp &= ~TCC_CTRLA_DMAOS;
3514 tmp |= value << TCC_CTRLA_DMAOS_Pos;
3515 ((Tcc *)hw)->CTRLA.reg = tmp;
3516 TCC_CRITICAL_SECTION_LEAVE();
3517 }
3518
hri_tcc_clear_CTRLA_DMAOS_bit(const void * const hw)3519 static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw)
3520 {
3521 TCC_CRITICAL_SECTION_ENTER();
3522 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3523 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS;
3524 TCC_CRITICAL_SECTION_LEAVE();
3525 }
3526
hri_tcc_toggle_CTRLA_DMAOS_bit(const void * const hw)3527 static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw)
3528 {
3529 TCC_CRITICAL_SECTION_ENTER();
3530 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3531 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS;
3532 TCC_CRITICAL_SECTION_LEAVE();
3533 }
3534
hri_tcc_set_CTRLA_CPTEN0_bit(const void * const hw)3535 static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw)
3536 {
3537 TCC_CRITICAL_SECTION_ENTER();
3538 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3539 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0;
3540 TCC_CRITICAL_SECTION_LEAVE();
3541 }
3542
hri_tcc_get_CTRLA_CPTEN0_bit(const void * const hw)3543 static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw)
3544 {
3545 uint32_t tmp;
3546 tmp = ((Tcc *)hw)->CTRLA.reg;
3547 tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos;
3548 return (bool)tmp;
3549 }
3550
hri_tcc_write_CTRLA_CPTEN0_bit(const void * const hw,bool value)3551 static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value)
3552 {
3553 uint32_t tmp;
3554 TCC_CRITICAL_SECTION_ENTER();
3555 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3556 tmp = ((Tcc *)hw)->CTRLA.reg;
3557 tmp &= ~TCC_CTRLA_CPTEN0;
3558 tmp |= value << TCC_CTRLA_CPTEN0_Pos;
3559 ((Tcc *)hw)->CTRLA.reg = tmp;
3560 TCC_CRITICAL_SECTION_LEAVE();
3561 }
3562
hri_tcc_clear_CTRLA_CPTEN0_bit(const void * const hw)3563 static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw)
3564 {
3565 TCC_CRITICAL_SECTION_ENTER();
3566 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3567 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0;
3568 TCC_CRITICAL_SECTION_LEAVE();
3569 }
3570
hri_tcc_toggle_CTRLA_CPTEN0_bit(const void * const hw)3571 static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw)
3572 {
3573 TCC_CRITICAL_SECTION_ENTER();
3574 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3575 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0;
3576 TCC_CRITICAL_SECTION_LEAVE();
3577 }
3578
hri_tcc_set_CTRLA_CPTEN1_bit(const void * const hw)3579 static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw)
3580 {
3581 TCC_CRITICAL_SECTION_ENTER();
3582 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3583 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1;
3584 TCC_CRITICAL_SECTION_LEAVE();
3585 }
3586
hri_tcc_get_CTRLA_CPTEN1_bit(const void * const hw)3587 static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw)
3588 {
3589 uint32_t tmp;
3590 tmp = ((Tcc *)hw)->CTRLA.reg;
3591 tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos;
3592 return (bool)tmp;
3593 }
3594
hri_tcc_write_CTRLA_CPTEN1_bit(const void * const hw,bool value)3595 static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value)
3596 {
3597 uint32_t tmp;
3598 TCC_CRITICAL_SECTION_ENTER();
3599 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3600 tmp = ((Tcc *)hw)->CTRLA.reg;
3601 tmp &= ~TCC_CTRLA_CPTEN1;
3602 tmp |= value << TCC_CTRLA_CPTEN1_Pos;
3603 ((Tcc *)hw)->CTRLA.reg = tmp;
3604 TCC_CRITICAL_SECTION_LEAVE();
3605 }
3606
hri_tcc_clear_CTRLA_CPTEN1_bit(const void * const hw)3607 static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw)
3608 {
3609 TCC_CRITICAL_SECTION_ENTER();
3610 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3611 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1;
3612 TCC_CRITICAL_SECTION_LEAVE();
3613 }
3614
hri_tcc_toggle_CTRLA_CPTEN1_bit(const void * const hw)3615 static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw)
3616 {
3617 TCC_CRITICAL_SECTION_ENTER();
3618 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3619 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1;
3620 TCC_CRITICAL_SECTION_LEAVE();
3621 }
3622
hri_tcc_set_CTRLA_CPTEN2_bit(const void * const hw)3623 static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw)
3624 {
3625 TCC_CRITICAL_SECTION_ENTER();
3626 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3627 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2;
3628 TCC_CRITICAL_SECTION_LEAVE();
3629 }
3630
hri_tcc_get_CTRLA_CPTEN2_bit(const void * const hw)3631 static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw)
3632 {
3633 uint32_t tmp;
3634 tmp = ((Tcc *)hw)->CTRLA.reg;
3635 tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos;
3636 return (bool)tmp;
3637 }
3638
hri_tcc_write_CTRLA_CPTEN2_bit(const void * const hw,bool value)3639 static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value)
3640 {
3641 uint32_t tmp;
3642 TCC_CRITICAL_SECTION_ENTER();
3643 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3644 tmp = ((Tcc *)hw)->CTRLA.reg;
3645 tmp &= ~TCC_CTRLA_CPTEN2;
3646 tmp |= value << TCC_CTRLA_CPTEN2_Pos;
3647 ((Tcc *)hw)->CTRLA.reg = tmp;
3648 TCC_CRITICAL_SECTION_LEAVE();
3649 }
3650
hri_tcc_clear_CTRLA_CPTEN2_bit(const void * const hw)3651 static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw)
3652 {
3653 TCC_CRITICAL_SECTION_ENTER();
3654 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3655 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2;
3656 TCC_CRITICAL_SECTION_LEAVE();
3657 }
3658
hri_tcc_toggle_CTRLA_CPTEN2_bit(const void * const hw)3659 static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw)
3660 {
3661 TCC_CRITICAL_SECTION_ENTER();
3662 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3663 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2;
3664 TCC_CRITICAL_SECTION_LEAVE();
3665 }
3666
hri_tcc_set_CTRLA_CPTEN3_bit(const void * const hw)3667 static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw)
3668 {
3669 TCC_CRITICAL_SECTION_ENTER();
3670 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3671 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3;
3672 TCC_CRITICAL_SECTION_LEAVE();
3673 }
3674
hri_tcc_get_CTRLA_CPTEN3_bit(const void * const hw)3675 static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw)
3676 {
3677 uint32_t tmp;
3678 tmp = ((Tcc *)hw)->CTRLA.reg;
3679 tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos;
3680 return (bool)tmp;
3681 }
3682
hri_tcc_write_CTRLA_CPTEN3_bit(const void * const hw,bool value)3683 static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value)
3684 {
3685 uint32_t tmp;
3686 TCC_CRITICAL_SECTION_ENTER();
3687 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3688 tmp = ((Tcc *)hw)->CTRLA.reg;
3689 tmp &= ~TCC_CTRLA_CPTEN3;
3690 tmp |= value << TCC_CTRLA_CPTEN3_Pos;
3691 ((Tcc *)hw)->CTRLA.reg = tmp;
3692 TCC_CRITICAL_SECTION_LEAVE();
3693 }
3694
hri_tcc_clear_CTRLA_CPTEN3_bit(const void * const hw)3695 static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw)
3696 {
3697 TCC_CRITICAL_SECTION_ENTER();
3698 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3699 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3;
3700 TCC_CRITICAL_SECTION_LEAVE();
3701 }
3702
hri_tcc_toggle_CTRLA_CPTEN3_bit(const void * const hw)3703 static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw)
3704 {
3705 TCC_CRITICAL_SECTION_ENTER();
3706 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3707 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3;
3708 TCC_CRITICAL_SECTION_LEAVE();
3709 }
3710
hri_tcc_set_CTRLA_RESOLUTION_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3711 static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3712 {
3713 TCC_CRITICAL_SECTION_ENTER();
3714 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3715 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask);
3716 TCC_CRITICAL_SECTION_LEAVE();
3717 }
3718
hri_tcc_get_CTRLA_RESOLUTION_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3719 static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3720 {
3721 uint32_t tmp;
3722 tmp = ((Tcc *)hw)->CTRLA.reg;
3723 tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos;
3724 return tmp;
3725 }
3726
hri_tcc_write_CTRLA_RESOLUTION_bf(const void * const hw,hri_tcc_ctrla_reg_t data)3727 static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
3728 {
3729 uint32_t tmp;
3730 TCC_CRITICAL_SECTION_ENTER();
3731 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3732 tmp = ((Tcc *)hw)->CTRLA.reg;
3733 tmp &= ~TCC_CTRLA_RESOLUTION_Msk;
3734 tmp |= TCC_CTRLA_RESOLUTION(data);
3735 ((Tcc *)hw)->CTRLA.reg = tmp;
3736 TCC_CRITICAL_SECTION_LEAVE();
3737 }
3738
hri_tcc_clear_CTRLA_RESOLUTION_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3739 static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3740 {
3741 TCC_CRITICAL_SECTION_ENTER();
3742 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3743 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask);
3744 TCC_CRITICAL_SECTION_LEAVE();
3745 }
3746
hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3747 static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3748 {
3749 TCC_CRITICAL_SECTION_ENTER();
3750 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3751 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask);
3752 TCC_CRITICAL_SECTION_LEAVE();
3753 }
3754
hri_tcc_read_CTRLA_RESOLUTION_bf(const void * const hw)3755 static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw)
3756 {
3757 uint32_t tmp;
3758 tmp = ((Tcc *)hw)->CTRLA.reg;
3759 tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos;
3760 return tmp;
3761 }
3762
hri_tcc_set_CTRLA_PRESCALER_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3763 static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3764 {
3765 TCC_CRITICAL_SECTION_ENTER();
3766 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3767 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask);
3768 TCC_CRITICAL_SECTION_LEAVE();
3769 }
3770
hri_tcc_get_CTRLA_PRESCALER_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3771 static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3772 {
3773 uint32_t tmp;
3774 tmp = ((Tcc *)hw)->CTRLA.reg;
3775 tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos;
3776 return tmp;
3777 }
3778
hri_tcc_write_CTRLA_PRESCALER_bf(const void * const hw,hri_tcc_ctrla_reg_t data)3779 static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
3780 {
3781 uint32_t tmp;
3782 TCC_CRITICAL_SECTION_ENTER();
3783 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3784 tmp = ((Tcc *)hw)->CTRLA.reg;
3785 tmp &= ~TCC_CTRLA_PRESCALER_Msk;
3786 tmp |= TCC_CTRLA_PRESCALER(data);
3787 ((Tcc *)hw)->CTRLA.reg = tmp;
3788 TCC_CRITICAL_SECTION_LEAVE();
3789 }
3790
hri_tcc_clear_CTRLA_PRESCALER_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3791 static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3792 {
3793 TCC_CRITICAL_SECTION_ENTER();
3794 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3795 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask);
3796 TCC_CRITICAL_SECTION_LEAVE();
3797 }
3798
hri_tcc_toggle_CTRLA_PRESCALER_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3799 static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3800 {
3801 TCC_CRITICAL_SECTION_ENTER();
3802 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3803 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask);
3804 TCC_CRITICAL_SECTION_LEAVE();
3805 }
3806
hri_tcc_read_CTRLA_PRESCALER_bf(const void * const hw)3807 static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw)
3808 {
3809 uint32_t tmp;
3810 tmp = ((Tcc *)hw)->CTRLA.reg;
3811 tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos;
3812 return tmp;
3813 }
3814
hri_tcc_set_CTRLA_PRESCSYNC_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3815 static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3816 {
3817 TCC_CRITICAL_SECTION_ENTER();
3818 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3819 ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask);
3820 TCC_CRITICAL_SECTION_LEAVE();
3821 }
3822
hri_tcc_get_CTRLA_PRESCSYNC_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3823 static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3824 {
3825 uint32_t tmp;
3826 tmp = ((Tcc *)hw)->CTRLA.reg;
3827 tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos;
3828 return tmp;
3829 }
3830
hri_tcc_write_CTRLA_PRESCSYNC_bf(const void * const hw,hri_tcc_ctrla_reg_t data)3831 static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data)
3832 {
3833 uint32_t tmp;
3834 TCC_CRITICAL_SECTION_ENTER();
3835 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3836 tmp = ((Tcc *)hw)->CTRLA.reg;
3837 tmp &= ~TCC_CTRLA_PRESCSYNC_Msk;
3838 tmp |= TCC_CTRLA_PRESCSYNC(data);
3839 ((Tcc *)hw)->CTRLA.reg = tmp;
3840 TCC_CRITICAL_SECTION_LEAVE();
3841 }
3842
hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3843 static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3844 {
3845 TCC_CRITICAL_SECTION_ENTER();
3846 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3847 ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask);
3848 TCC_CRITICAL_SECTION_LEAVE();
3849 }
3850
hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void * const hw,hri_tcc_ctrla_reg_t mask)3851 static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask)
3852 {
3853 TCC_CRITICAL_SECTION_ENTER();
3854 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
3855 ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask);
3856 TCC_CRITICAL_SECTION_LEAVE();
3857 }
3858
hri_tcc_read_CTRLA_PRESCSYNC_bf(const void * const hw)3859 static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw)
3860 {
3861 uint32_t tmp;
3862 tmp = ((Tcc *)hw)->CTRLA.reg;
3863 tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos;
3864 return tmp;
3865 }
3866
hri_tcc_set_CTRLA_reg(const void * const hw,hri_tcc_ctrla_reg_t mask)3867 static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
3868 {
3869 TCC_CRITICAL_SECTION_ENTER();
3870 ((Tcc *)hw)->CTRLA.reg |= mask;
3871 TCC_CRITICAL_SECTION_LEAVE();
3872 }
3873
hri_tcc_get_CTRLA_reg(const void * const hw,hri_tcc_ctrla_reg_t mask)3874 static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
3875 {
3876 uint32_t tmp;
3877 tmp = ((Tcc *)hw)->CTRLA.reg;
3878 tmp &= mask;
3879 return tmp;
3880 }
3881
hri_tcc_write_CTRLA_reg(const void * const hw,hri_tcc_ctrla_reg_t data)3882 static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data)
3883 {
3884 TCC_CRITICAL_SECTION_ENTER();
3885 ((Tcc *)hw)->CTRLA.reg = data;
3886 TCC_CRITICAL_SECTION_LEAVE();
3887 }
3888
hri_tcc_clear_CTRLA_reg(const void * const hw,hri_tcc_ctrla_reg_t mask)3889 static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
3890 {
3891 TCC_CRITICAL_SECTION_ENTER();
3892 ((Tcc *)hw)->CTRLA.reg &= ~mask;
3893 TCC_CRITICAL_SECTION_LEAVE();
3894 }
3895
hri_tcc_toggle_CTRLA_reg(const void * const hw,hri_tcc_ctrla_reg_t mask)3896 static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask)
3897 {
3898 TCC_CRITICAL_SECTION_ENTER();
3899 ((Tcc *)hw)->CTRLA.reg ^= mask;
3900 TCC_CRITICAL_SECTION_LEAVE();
3901 }
3902
hri_tcc_read_CTRLA_reg(const void * const hw)3903 static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw)
3904 {
3905 return ((Tcc *)hw)->CTRLA.reg;
3906 }
3907
hri_tcc_set_FCTRLA_KEEP_bit(const void * const hw)3908 static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw)
3909 {
3910 TCC_CRITICAL_SECTION_ENTER();
3911 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP;
3912 TCC_CRITICAL_SECTION_LEAVE();
3913 }
3914
hri_tcc_get_FCTRLA_KEEP_bit(const void * const hw)3915 static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw)
3916 {
3917 uint32_t tmp;
3918 tmp = ((Tcc *)hw)->FCTRLA.reg;
3919 tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos;
3920 return (bool)tmp;
3921 }
3922
hri_tcc_write_FCTRLA_KEEP_bit(const void * const hw,bool value)3923 static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value)
3924 {
3925 uint32_t tmp;
3926 TCC_CRITICAL_SECTION_ENTER();
3927 tmp = ((Tcc *)hw)->FCTRLA.reg;
3928 tmp &= ~TCC_FCTRLA_KEEP;
3929 tmp |= value << TCC_FCTRLA_KEEP_Pos;
3930 ((Tcc *)hw)->FCTRLA.reg = tmp;
3931 TCC_CRITICAL_SECTION_LEAVE();
3932 }
3933
hri_tcc_clear_FCTRLA_KEEP_bit(const void * const hw)3934 static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw)
3935 {
3936 TCC_CRITICAL_SECTION_ENTER();
3937 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP;
3938 TCC_CRITICAL_SECTION_LEAVE();
3939 }
3940
hri_tcc_toggle_FCTRLA_KEEP_bit(const void * const hw)3941 static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw)
3942 {
3943 TCC_CRITICAL_SECTION_ENTER();
3944 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP;
3945 TCC_CRITICAL_SECTION_LEAVE();
3946 }
3947
hri_tcc_set_FCTRLA_QUAL_bit(const void * const hw)3948 static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw)
3949 {
3950 TCC_CRITICAL_SECTION_ENTER();
3951 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL;
3952 TCC_CRITICAL_SECTION_LEAVE();
3953 }
3954
hri_tcc_get_FCTRLA_QUAL_bit(const void * const hw)3955 static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw)
3956 {
3957 uint32_t tmp;
3958 tmp = ((Tcc *)hw)->FCTRLA.reg;
3959 tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos;
3960 return (bool)tmp;
3961 }
3962
hri_tcc_write_FCTRLA_QUAL_bit(const void * const hw,bool value)3963 static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value)
3964 {
3965 uint32_t tmp;
3966 TCC_CRITICAL_SECTION_ENTER();
3967 tmp = ((Tcc *)hw)->FCTRLA.reg;
3968 tmp &= ~TCC_FCTRLA_QUAL;
3969 tmp |= value << TCC_FCTRLA_QUAL_Pos;
3970 ((Tcc *)hw)->FCTRLA.reg = tmp;
3971 TCC_CRITICAL_SECTION_LEAVE();
3972 }
3973
hri_tcc_clear_FCTRLA_QUAL_bit(const void * const hw)3974 static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw)
3975 {
3976 TCC_CRITICAL_SECTION_ENTER();
3977 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL;
3978 TCC_CRITICAL_SECTION_LEAVE();
3979 }
3980
hri_tcc_toggle_FCTRLA_QUAL_bit(const void * const hw)3981 static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw)
3982 {
3983 TCC_CRITICAL_SECTION_ENTER();
3984 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL;
3985 TCC_CRITICAL_SECTION_LEAVE();
3986 }
3987
hri_tcc_set_FCTRLA_RESTART_bit(const void * const hw)3988 static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw)
3989 {
3990 TCC_CRITICAL_SECTION_ENTER();
3991 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART;
3992 TCC_CRITICAL_SECTION_LEAVE();
3993 }
3994
hri_tcc_get_FCTRLA_RESTART_bit(const void * const hw)3995 static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw)
3996 {
3997 uint32_t tmp;
3998 tmp = ((Tcc *)hw)->FCTRLA.reg;
3999 tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos;
4000 return (bool)tmp;
4001 }
4002
hri_tcc_write_FCTRLA_RESTART_bit(const void * const hw,bool value)4003 static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value)
4004 {
4005 uint32_t tmp;
4006 TCC_CRITICAL_SECTION_ENTER();
4007 tmp = ((Tcc *)hw)->FCTRLA.reg;
4008 tmp &= ~TCC_FCTRLA_RESTART;
4009 tmp |= value << TCC_FCTRLA_RESTART_Pos;
4010 ((Tcc *)hw)->FCTRLA.reg = tmp;
4011 TCC_CRITICAL_SECTION_LEAVE();
4012 }
4013
hri_tcc_clear_FCTRLA_RESTART_bit(const void * const hw)4014 static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw)
4015 {
4016 TCC_CRITICAL_SECTION_ENTER();
4017 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART;
4018 TCC_CRITICAL_SECTION_LEAVE();
4019 }
4020
hri_tcc_toggle_FCTRLA_RESTART_bit(const void * const hw)4021 static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw)
4022 {
4023 TCC_CRITICAL_SECTION_ENTER();
4024 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART;
4025 TCC_CRITICAL_SECTION_LEAVE();
4026 }
4027
hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void * const hw)4028 static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw)
4029 {
4030 TCC_CRITICAL_SECTION_ENTER();
4031 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC;
4032 TCC_CRITICAL_SECTION_LEAVE();
4033 }
4034
hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void * const hw)4035 static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw)
4036 {
4037 uint32_t tmp;
4038 tmp = ((Tcc *)hw)->FCTRLA.reg;
4039 tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos;
4040 return (bool)tmp;
4041 }
4042
hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void * const hw,bool value)4043 static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value)
4044 {
4045 uint32_t tmp;
4046 TCC_CRITICAL_SECTION_ENTER();
4047 tmp = ((Tcc *)hw)->FCTRLA.reg;
4048 tmp &= ~TCC_FCTRLA_BLANKPRESC;
4049 tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos;
4050 ((Tcc *)hw)->FCTRLA.reg = tmp;
4051 TCC_CRITICAL_SECTION_LEAVE();
4052 }
4053
hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void * const hw)4054 static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw)
4055 {
4056 TCC_CRITICAL_SECTION_ENTER();
4057 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC;
4058 TCC_CRITICAL_SECTION_LEAVE();
4059 }
4060
hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void * const hw)4061 static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw)
4062 {
4063 TCC_CRITICAL_SECTION_ENTER();
4064 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC;
4065 TCC_CRITICAL_SECTION_LEAVE();
4066 }
4067
hri_tcc_set_FCTRLA_SRC_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4068 static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4069 {
4070 TCC_CRITICAL_SECTION_ENTER();
4071 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask);
4072 TCC_CRITICAL_SECTION_LEAVE();
4073 }
4074
hri_tcc_get_FCTRLA_SRC_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4075 static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4076 {
4077 uint32_t tmp;
4078 tmp = ((Tcc *)hw)->FCTRLA.reg;
4079 tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos;
4080 return tmp;
4081 }
4082
hri_tcc_write_FCTRLA_SRC_bf(const void * const hw,hri_tcc_fctrla_reg_t data)4083 static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
4084 {
4085 uint32_t tmp;
4086 TCC_CRITICAL_SECTION_ENTER();
4087 tmp = ((Tcc *)hw)->FCTRLA.reg;
4088 tmp &= ~TCC_FCTRLA_SRC_Msk;
4089 tmp |= TCC_FCTRLA_SRC(data);
4090 ((Tcc *)hw)->FCTRLA.reg = tmp;
4091 TCC_CRITICAL_SECTION_LEAVE();
4092 }
4093
hri_tcc_clear_FCTRLA_SRC_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4094 static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4095 {
4096 TCC_CRITICAL_SECTION_ENTER();
4097 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask);
4098 TCC_CRITICAL_SECTION_LEAVE();
4099 }
4100
hri_tcc_toggle_FCTRLA_SRC_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4101 static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4102 {
4103 TCC_CRITICAL_SECTION_ENTER();
4104 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask);
4105 TCC_CRITICAL_SECTION_LEAVE();
4106 }
4107
hri_tcc_read_FCTRLA_SRC_bf(const void * const hw)4108 static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw)
4109 {
4110 uint32_t tmp;
4111 tmp = ((Tcc *)hw)->FCTRLA.reg;
4112 tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos;
4113 return tmp;
4114 }
4115
hri_tcc_set_FCTRLA_BLANK_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4116 static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4117 {
4118 TCC_CRITICAL_SECTION_ENTER();
4119 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask);
4120 TCC_CRITICAL_SECTION_LEAVE();
4121 }
4122
hri_tcc_get_FCTRLA_BLANK_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4123 static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4124 {
4125 uint32_t tmp;
4126 tmp = ((Tcc *)hw)->FCTRLA.reg;
4127 tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos;
4128 return tmp;
4129 }
4130
hri_tcc_write_FCTRLA_BLANK_bf(const void * const hw,hri_tcc_fctrla_reg_t data)4131 static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
4132 {
4133 uint32_t tmp;
4134 TCC_CRITICAL_SECTION_ENTER();
4135 tmp = ((Tcc *)hw)->FCTRLA.reg;
4136 tmp &= ~TCC_FCTRLA_BLANK_Msk;
4137 tmp |= TCC_FCTRLA_BLANK(data);
4138 ((Tcc *)hw)->FCTRLA.reg = tmp;
4139 TCC_CRITICAL_SECTION_LEAVE();
4140 }
4141
hri_tcc_clear_FCTRLA_BLANK_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4142 static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4143 {
4144 TCC_CRITICAL_SECTION_ENTER();
4145 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask);
4146 TCC_CRITICAL_SECTION_LEAVE();
4147 }
4148
hri_tcc_toggle_FCTRLA_BLANK_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4149 static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4150 {
4151 TCC_CRITICAL_SECTION_ENTER();
4152 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask);
4153 TCC_CRITICAL_SECTION_LEAVE();
4154 }
4155
hri_tcc_read_FCTRLA_BLANK_bf(const void * const hw)4156 static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw)
4157 {
4158 uint32_t tmp;
4159 tmp = ((Tcc *)hw)->FCTRLA.reg;
4160 tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos;
4161 return tmp;
4162 }
4163
hri_tcc_set_FCTRLA_HALT_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4164 static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4165 {
4166 TCC_CRITICAL_SECTION_ENTER();
4167 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask);
4168 TCC_CRITICAL_SECTION_LEAVE();
4169 }
4170
hri_tcc_get_FCTRLA_HALT_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4171 static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4172 {
4173 uint32_t tmp;
4174 tmp = ((Tcc *)hw)->FCTRLA.reg;
4175 tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos;
4176 return tmp;
4177 }
4178
hri_tcc_write_FCTRLA_HALT_bf(const void * const hw,hri_tcc_fctrla_reg_t data)4179 static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
4180 {
4181 uint32_t tmp;
4182 TCC_CRITICAL_SECTION_ENTER();
4183 tmp = ((Tcc *)hw)->FCTRLA.reg;
4184 tmp &= ~TCC_FCTRLA_HALT_Msk;
4185 tmp |= TCC_FCTRLA_HALT(data);
4186 ((Tcc *)hw)->FCTRLA.reg = tmp;
4187 TCC_CRITICAL_SECTION_LEAVE();
4188 }
4189
hri_tcc_clear_FCTRLA_HALT_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4190 static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4191 {
4192 TCC_CRITICAL_SECTION_ENTER();
4193 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask);
4194 TCC_CRITICAL_SECTION_LEAVE();
4195 }
4196
hri_tcc_toggle_FCTRLA_HALT_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4197 static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4198 {
4199 TCC_CRITICAL_SECTION_ENTER();
4200 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask);
4201 TCC_CRITICAL_SECTION_LEAVE();
4202 }
4203
hri_tcc_read_FCTRLA_HALT_bf(const void * const hw)4204 static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw)
4205 {
4206 uint32_t tmp;
4207 tmp = ((Tcc *)hw)->FCTRLA.reg;
4208 tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos;
4209 return tmp;
4210 }
4211
hri_tcc_set_FCTRLA_CHSEL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4212 static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4213 {
4214 TCC_CRITICAL_SECTION_ENTER();
4215 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask);
4216 TCC_CRITICAL_SECTION_LEAVE();
4217 }
4218
hri_tcc_get_FCTRLA_CHSEL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4219 static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4220 {
4221 uint32_t tmp;
4222 tmp = ((Tcc *)hw)->FCTRLA.reg;
4223 tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos;
4224 return tmp;
4225 }
4226
hri_tcc_write_FCTRLA_CHSEL_bf(const void * const hw,hri_tcc_fctrla_reg_t data)4227 static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
4228 {
4229 uint32_t tmp;
4230 TCC_CRITICAL_SECTION_ENTER();
4231 tmp = ((Tcc *)hw)->FCTRLA.reg;
4232 tmp &= ~TCC_FCTRLA_CHSEL_Msk;
4233 tmp |= TCC_FCTRLA_CHSEL(data);
4234 ((Tcc *)hw)->FCTRLA.reg = tmp;
4235 TCC_CRITICAL_SECTION_LEAVE();
4236 }
4237
hri_tcc_clear_FCTRLA_CHSEL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4238 static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4239 {
4240 TCC_CRITICAL_SECTION_ENTER();
4241 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask);
4242 TCC_CRITICAL_SECTION_LEAVE();
4243 }
4244
hri_tcc_toggle_FCTRLA_CHSEL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4245 static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4246 {
4247 TCC_CRITICAL_SECTION_ENTER();
4248 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask);
4249 TCC_CRITICAL_SECTION_LEAVE();
4250 }
4251
hri_tcc_read_FCTRLA_CHSEL_bf(const void * const hw)4252 static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw)
4253 {
4254 uint32_t tmp;
4255 tmp = ((Tcc *)hw)->FCTRLA.reg;
4256 tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos;
4257 return tmp;
4258 }
4259
hri_tcc_set_FCTRLA_CAPTURE_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4260 static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4261 {
4262 TCC_CRITICAL_SECTION_ENTER();
4263 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask);
4264 TCC_CRITICAL_SECTION_LEAVE();
4265 }
4266
hri_tcc_get_FCTRLA_CAPTURE_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4267 static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4268 {
4269 uint32_t tmp;
4270 tmp = ((Tcc *)hw)->FCTRLA.reg;
4271 tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos;
4272 return tmp;
4273 }
4274
hri_tcc_write_FCTRLA_CAPTURE_bf(const void * const hw,hri_tcc_fctrla_reg_t data)4275 static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
4276 {
4277 uint32_t tmp;
4278 TCC_CRITICAL_SECTION_ENTER();
4279 tmp = ((Tcc *)hw)->FCTRLA.reg;
4280 tmp &= ~TCC_FCTRLA_CAPTURE_Msk;
4281 tmp |= TCC_FCTRLA_CAPTURE(data);
4282 ((Tcc *)hw)->FCTRLA.reg = tmp;
4283 TCC_CRITICAL_SECTION_LEAVE();
4284 }
4285
hri_tcc_clear_FCTRLA_CAPTURE_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4286 static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4287 {
4288 TCC_CRITICAL_SECTION_ENTER();
4289 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask);
4290 TCC_CRITICAL_SECTION_LEAVE();
4291 }
4292
hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4293 static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4294 {
4295 TCC_CRITICAL_SECTION_ENTER();
4296 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask);
4297 TCC_CRITICAL_SECTION_LEAVE();
4298 }
4299
hri_tcc_read_FCTRLA_CAPTURE_bf(const void * const hw)4300 static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw)
4301 {
4302 uint32_t tmp;
4303 tmp = ((Tcc *)hw)->FCTRLA.reg;
4304 tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos;
4305 return tmp;
4306 }
4307
hri_tcc_set_FCTRLA_BLANKVAL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4308 static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4309 {
4310 TCC_CRITICAL_SECTION_ENTER();
4311 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask);
4312 TCC_CRITICAL_SECTION_LEAVE();
4313 }
4314
hri_tcc_get_FCTRLA_BLANKVAL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4315 static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4316 {
4317 uint32_t tmp;
4318 tmp = ((Tcc *)hw)->FCTRLA.reg;
4319 tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos;
4320 return tmp;
4321 }
4322
hri_tcc_write_FCTRLA_BLANKVAL_bf(const void * const hw,hri_tcc_fctrla_reg_t data)4323 static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
4324 {
4325 uint32_t tmp;
4326 TCC_CRITICAL_SECTION_ENTER();
4327 tmp = ((Tcc *)hw)->FCTRLA.reg;
4328 tmp &= ~TCC_FCTRLA_BLANKVAL_Msk;
4329 tmp |= TCC_FCTRLA_BLANKVAL(data);
4330 ((Tcc *)hw)->FCTRLA.reg = tmp;
4331 TCC_CRITICAL_SECTION_LEAVE();
4332 }
4333
hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4334 static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4335 {
4336 TCC_CRITICAL_SECTION_ENTER();
4337 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask);
4338 TCC_CRITICAL_SECTION_LEAVE();
4339 }
4340
hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4341 static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4342 {
4343 TCC_CRITICAL_SECTION_ENTER();
4344 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask);
4345 TCC_CRITICAL_SECTION_LEAVE();
4346 }
4347
hri_tcc_read_FCTRLA_BLANKVAL_bf(const void * const hw)4348 static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw)
4349 {
4350 uint32_t tmp;
4351 tmp = ((Tcc *)hw)->FCTRLA.reg;
4352 tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos;
4353 return tmp;
4354 }
4355
hri_tcc_set_FCTRLA_FILTERVAL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4356 static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4357 {
4358 TCC_CRITICAL_SECTION_ENTER();
4359 ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask);
4360 TCC_CRITICAL_SECTION_LEAVE();
4361 }
4362
hri_tcc_get_FCTRLA_FILTERVAL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4363 static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4364 {
4365 uint32_t tmp;
4366 tmp = ((Tcc *)hw)->FCTRLA.reg;
4367 tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos;
4368 return tmp;
4369 }
4370
hri_tcc_write_FCTRLA_FILTERVAL_bf(const void * const hw,hri_tcc_fctrla_reg_t data)4371 static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data)
4372 {
4373 uint32_t tmp;
4374 TCC_CRITICAL_SECTION_ENTER();
4375 tmp = ((Tcc *)hw)->FCTRLA.reg;
4376 tmp &= ~TCC_FCTRLA_FILTERVAL_Msk;
4377 tmp |= TCC_FCTRLA_FILTERVAL(data);
4378 ((Tcc *)hw)->FCTRLA.reg = tmp;
4379 TCC_CRITICAL_SECTION_LEAVE();
4380 }
4381
hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4382 static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4383 {
4384 TCC_CRITICAL_SECTION_ENTER();
4385 ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask);
4386 TCC_CRITICAL_SECTION_LEAVE();
4387 }
4388
hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void * const hw,hri_tcc_fctrla_reg_t mask)4389 static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask)
4390 {
4391 TCC_CRITICAL_SECTION_ENTER();
4392 ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask);
4393 TCC_CRITICAL_SECTION_LEAVE();
4394 }
4395
hri_tcc_read_FCTRLA_FILTERVAL_bf(const void * const hw)4396 static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw)
4397 {
4398 uint32_t tmp;
4399 tmp = ((Tcc *)hw)->FCTRLA.reg;
4400 tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos;
4401 return tmp;
4402 }
4403
hri_tcc_set_FCTRLA_reg(const void * const hw,hri_tcc_fctrla_reg_t mask)4404 static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
4405 {
4406 TCC_CRITICAL_SECTION_ENTER();
4407 ((Tcc *)hw)->FCTRLA.reg |= mask;
4408 TCC_CRITICAL_SECTION_LEAVE();
4409 }
4410
hri_tcc_get_FCTRLA_reg(const void * const hw,hri_tcc_fctrla_reg_t mask)4411 static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
4412 {
4413 uint32_t tmp;
4414 tmp = ((Tcc *)hw)->FCTRLA.reg;
4415 tmp &= mask;
4416 return tmp;
4417 }
4418
hri_tcc_write_FCTRLA_reg(const void * const hw,hri_tcc_fctrla_reg_t data)4419 static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data)
4420 {
4421 TCC_CRITICAL_SECTION_ENTER();
4422 ((Tcc *)hw)->FCTRLA.reg = data;
4423 TCC_CRITICAL_SECTION_LEAVE();
4424 }
4425
hri_tcc_clear_FCTRLA_reg(const void * const hw,hri_tcc_fctrla_reg_t mask)4426 static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
4427 {
4428 TCC_CRITICAL_SECTION_ENTER();
4429 ((Tcc *)hw)->FCTRLA.reg &= ~mask;
4430 TCC_CRITICAL_SECTION_LEAVE();
4431 }
4432
hri_tcc_toggle_FCTRLA_reg(const void * const hw,hri_tcc_fctrla_reg_t mask)4433 static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask)
4434 {
4435 TCC_CRITICAL_SECTION_ENTER();
4436 ((Tcc *)hw)->FCTRLA.reg ^= mask;
4437 TCC_CRITICAL_SECTION_LEAVE();
4438 }
4439
hri_tcc_read_FCTRLA_reg(const void * const hw)4440 static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw)
4441 {
4442 return ((Tcc *)hw)->FCTRLA.reg;
4443 }
4444
hri_tcc_set_FCTRLB_KEEP_bit(const void * const hw)4445 static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw)
4446 {
4447 TCC_CRITICAL_SECTION_ENTER();
4448 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP;
4449 TCC_CRITICAL_SECTION_LEAVE();
4450 }
4451
hri_tcc_get_FCTRLB_KEEP_bit(const void * const hw)4452 static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw)
4453 {
4454 uint32_t tmp;
4455 tmp = ((Tcc *)hw)->FCTRLB.reg;
4456 tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos;
4457 return (bool)tmp;
4458 }
4459
hri_tcc_write_FCTRLB_KEEP_bit(const void * const hw,bool value)4460 static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value)
4461 {
4462 uint32_t tmp;
4463 TCC_CRITICAL_SECTION_ENTER();
4464 tmp = ((Tcc *)hw)->FCTRLB.reg;
4465 tmp &= ~TCC_FCTRLB_KEEP;
4466 tmp |= value << TCC_FCTRLB_KEEP_Pos;
4467 ((Tcc *)hw)->FCTRLB.reg = tmp;
4468 TCC_CRITICAL_SECTION_LEAVE();
4469 }
4470
hri_tcc_clear_FCTRLB_KEEP_bit(const void * const hw)4471 static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw)
4472 {
4473 TCC_CRITICAL_SECTION_ENTER();
4474 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP;
4475 TCC_CRITICAL_SECTION_LEAVE();
4476 }
4477
hri_tcc_toggle_FCTRLB_KEEP_bit(const void * const hw)4478 static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw)
4479 {
4480 TCC_CRITICAL_SECTION_ENTER();
4481 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP;
4482 TCC_CRITICAL_SECTION_LEAVE();
4483 }
4484
hri_tcc_set_FCTRLB_QUAL_bit(const void * const hw)4485 static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw)
4486 {
4487 TCC_CRITICAL_SECTION_ENTER();
4488 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL;
4489 TCC_CRITICAL_SECTION_LEAVE();
4490 }
4491
hri_tcc_get_FCTRLB_QUAL_bit(const void * const hw)4492 static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw)
4493 {
4494 uint32_t tmp;
4495 tmp = ((Tcc *)hw)->FCTRLB.reg;
4496 tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos;
4497 return (bool)tmp;
4498 }
4499
hri_tcc_write_FCTRLB_QUAL_bit(const void * const hw,bool value)4500 static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value)
4501 {
4502 uint32_t tmp;
4503 TCC_CRITICAL_SECTION_ENTER();
4504 tmp = ((Tcc *)hw)->FCTRLB.reg;
4505 tmp &= ~TCC_FCTRLB_QUAL;
4506 tmp |= value << TCC_FCTRLB_QUAL_Pos;
4507 ((Tcc *)hw)->FCTRLB.reg = tmp;
4508 TCC_CRITICAL_SECTION_LEAVE();
4509 }
4510
hri_tcc_clear_FCTRLB_QUAL_bit(const void * const hw)4511 static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw)
4512 {
4513 TCC_CRITICAL_SECTION_ENTER();
4514 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL;
4515 TCC_CRITICAL_SECTION_LEAVE();
4516 }
4517
hri_tcc_toggle_FCTRLB_QUAL_bit(const void * const hw)4518 static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw)
4519 {
4520 TCC_CRITICAL_SECTION_ENTER();
4521 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL;
4522 TCC_CRITICAL_SECTION_LEAVE();
4523 }
4524
hri_tcc_set_FCTRLB_RESTART_bit(const void * const hw)4525 static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw)
4526 {
4527 TCC_CRITICAL_SECTION_ENTER();
4528 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART;
4529 TCC_CRITICAL_SECTION_LEAVE();
4530 }
4531
hri_tcc_get_FCTRLB_RESTART_bit(const void * const hw)4532 static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw)
4533 {
4534 uint32_t tmp;
4535 tmp = ((Tcc *)hw)->FCTRLB.reg;
4536 tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos;
4537 return (bool)tmp;
4538 }
4539
hri_tcc_write_FCTRLB_RESTART_bit(const void * const hw,bool value)4540 static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value)
4541 {
4542 uint32_t tmp;
4543 TCC_CRITICAL_SECTION_ENTER();
4544 tmp = ((Tcc *)hw)->FCTRLB.reg;
4545 tmp &= ~TCC_FCTRLB_RESTART;
4546 tmp |= value << TCC_FCTRLB_RESTART_Pos;
4547 ((Tcc *)hw)->FCTRLB.reg = tmp;
4548 TCC_CRITICAL_SECTION_LEAVE();
4549 }
4550
hri_tcc_clear_FCTRLB_RESTART_bit(const void * const hw)4551 static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw)
4552 {
4553 TCC_CRITICAL_SECTION_ENTER();
4554 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART;
4555 TCC_CRITICAL_SECTION_LEAVE();
4556 }
4557
hri_tcc_toggle_FCTRLB_RESTART_bit(const void * const hw)4558 static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw)
4559 {
4560 TCC_CRITICAL_SECTION_ENTER();
4561 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART;
4562 TCC_CRITICAL_SECTION_LEAVE();
4563 }
4564
hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void * const hw)4565 static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw)
4566 {
4567 TCC_CRITICAL_SECTION_ENTER();
4568 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC;
4569 TCC_CRITICAL_SECTION_LEAVE();
4570 }
4571
hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void * const hw)4572 static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw)
4573 {
4574 uint32_t tmp;
4575 tmp = ((Tcc *)hw)->FCTRLB.reg;
4576 tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos;
4577 return (bool)tmp;
4578 }
4579
hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void * const hw,bool value)4580 static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value)
4581 {
4582 uint32_t tmp;
4583 TCC_CRITICAL_SECTION_ENTER();
4584 tmp = ((Tcc *)hw)->FCTRLB.reg;
4585 tmp &= ~TCC_FCTRLB_BLANKPRESC;
4586 tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos;
4587 ((Tcc *)hw)->FCTRLB.reg = tmp;
4588 TCC_CRITICAL_SECTION_LEAVE();
4589 }
4590
hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void * const hw)4591 static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw)
4592 {
4593 TCC_CRITICAL_SECTION_ENTER();
4594 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC;
4595 TCC_CRITICAL_SECTION_LEAVE();
4596 }
4597
hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void * const hw)4598 static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw)
4599 {
4600 TCC_CRITICAL_SECTION_ENTER();
4601 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC;
4602 TCC_CRITICAL_SECTION_LEAVE();
4603 }
4604
hri_tcc_set_FCTRLB_SRC_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4605 static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4606 {
4607 TCC_CRITICAL_SECTION_ENTER();
4608 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask);
4609 TCC_CRITICAL_SECTION_LEAVE();
4610 }
4611
hri_tcc_get_FCTRLB_SRC_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4612 static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4613 {
4614 uint32_t tmp;
4615 tmp = ((Tcc *)hw)->FCTRLB.reg;
4616 tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos;
4617 return tmp;
4618 }
4619
hri_tcc_write_FCTRLB_SRC_bf(const void * const hw,hri_tcc_fctrlb_reg_t data)4620 static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
4621 {
4622 uint32_t tmp;
4623 TCC_CRITICAL_SECTION_ENTER();
4624 tmp = ((Tcc *)hw)->FCTRLB.reg;
4625 tmp &= ~TCC_FCTRLB_SRC_Msk;
4626 tmp |= TCC_FCTRLB_SRC(data);
4627 ((Tcc *)hw)->FCTRLB.reg = tmp;
4628 TCC_CRITICAL_SECTION_LEAVE();
4629 }
4630
hri_tcc_clear_FCTRLB_SRC_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4631 static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4632 {
4633 TCC_CRITICAL_SECTION_ENTER();
4634 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask);
4635 TCC_CRITICAL_SECTION_LEAVE();
4636 }
4637
hri_tcc_toggle_FCTRLB_SRC_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4638 static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4639 {
4640 TCC_CRITICAL_SECTION_ENTER();
4641 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask);
4642 TCC_CRITICAL_SECTION_LEAVE();
4643 }
4644
hri_tcc_read_FCTRLB_SRC_bf(const void * const hw)4645 static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw)
4646 {
4647 uint32_t tmp;
4648 tmp = ((Tcc *)hw)->FCTRLB.reg;
4649 tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos;
4650 return tmp;
4651 }
4652
hri_tcc_set_FCTRLB_BLANK_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4653 static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4654 {
4655 TCC_CRITICAL_SECTION_ENTER();
4656 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask);
4657 TCC_CRITICAL_SECTION_LEAVE();
4658 }
4659
hri_tcc_get_FCTRLB_BLANK_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4660 static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4661 {
4662 uint32_t tmp;
4663 tmp = ((Tcc *)hw)->FCTRLB.reg;
4664 tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos;
4665 return tmp;
4666 }
4667
hri_tcc_write_FCTRLB_BLANK_bf(const void * const hw,hri_tcc_fctrlb_reg_t data)4668 static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
4669 {
4670 uint32_t tmp;
4671 TCC_CRITICAL_SECTION_ENTER();
4672 tmp = ((Tcc *)hw)->FCTRLB.reg;
4673 tmp &= ~TCC_FCTRLB_BLANK_Msk;
4674 tmp |= TCC_FCTRLB_BLANK(data);
4675 ((Tcc *)hw)->FCTRLB.reg = tmp;
4676 TCC_CRITICAL_SECTION_LEAVE();
4677 }
4678
hri_tcc_clear_FCTRLB_BLANK_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4679 static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4680 {
4681 TCC_CRITICAL_SECTION_ENTER();
4682 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask);
4683 TCC_CRITICAL_SECTION_LEAVE();
4684 }
4685
hri_tcc_toggle_FCTRLB_BLANK_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4686 static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4687 {
4688 TCC_CRITICAL_SECTION_ENTER();
4689 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask);
4690 TCC_CRITICAL_SECTION_LEAVE();
4691 }
4692
hri_tcc_read_FCTRLB_BLANK_bf(const void * const hw)4693 static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw)
4694 {
4695 uint32_t tmp;
4696 tmp = ((Tcc *)hw)->FCTRLB.reg;
4697 tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos;
4698 return tmp;
4699 }
4700
hri_tcc_set_FCTRLB_HALT_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4701 static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4702 {
4703 TCC_CRITICAL_SECTION_ENTER();
4704 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask);
4705 TCC_CRITICAL_SECTION_LEAVE();
4706 }
4707
hri_tcc_get_FCTRLB_HALT_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4708 static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4709 {
4710 uint32_t tmp;
4711 tmp = ((Tcc *)hw)->FCTRLB.reg;
4712 tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos;
4713 return tmp;
4714 }
4715
hri_tcc_write_FCTRLB_HALT_bf(const void * const hw,hri_tcc_fctrlb_reg_t data)4716 static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
4717 {
4718 uint32_t tmp;
4719 TCC_CRITICAL_SECTION_ENTER();
4720 tmp = ((Tcc *)hw)->FCTRLB.reg;
4721 tmp &= ~TCC_FCTRLB_HALT_Msk;
4722 tmp |= TCC_FCTRLB_HALT(data);
4723 ((Tcc *)hw)->FCTRLB.reg = tmp;
4724 TCC_CRITICAL_SECTION_LEAVE();
4725 }
4726
hri_tcc_clear_FCTRLB_HALT_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4727 static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4728 {
4729 TCC_CRITICAL_SECTION_ENTER();
4730 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask);
4731 TCC_CRITICAL_SECTION_LEAVE();
4732 }
4733
hri_tcc_toggle_FCTRLB_HALT_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4734 static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4735 {
4736 TCC_CRITICAL_SECTION_ENTER();
4737 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask);
4738 TCC_CRITICAL_SECTION_LEAVE();
4739 }
4740
hri_tcc_read_FCTRLB_HALT_bf(const void * const hw)4741 static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw)
4742 {
4743 uint32_t tmp;
4744 tmp = ((Tcc *)hw)->FCTRLB.reg;
4745 tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos;
4746 return tmp;
4747 }
4748
hri_tcc_set_FCTRLB_CHSEL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4749 static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4750 {
4751 TCC_CRITICAL_SECTION_ENTER();
4752 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask);
4753 TCC_CRITICAL_SECTION_LEAVE();
4754 }
4755
hri_tcc_get_FCTRLB_CHSEL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4756 static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4757 {
4758 uint32_t tmp;
4759 tmp = ((Tcc *)hw)->FCTRLB.reg;
4760 tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos;
4761 return tmp;
4762 }
4763
hri_tcc_write_FCTRLB_CHSEL_bf(const void * const hw,hri_tcc_fctrlb_reg_t data)4764 static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
4765 {
4766 uint32_t tmp;
4767 TCC_CRITICAL_SECTION_ENTER();
4768 tmp = ((Tcc *)hw)->FCTRLB.reg;
4769 tmp &= ~TCC_FCTRLB_CHSEL_Msk;
4770 tmp |= TCC_FCTRLB_CHSEL(data);
4771 ((Tcc *)hw)->FCTRLB.reg = tmp;
4772 TCC_CRITICAL_SECTION_LEAVE();
4773 }
4774
hri_tcc_clear_FCTRLB_CHSEL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4775 static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4776 {
4777 TCC_CRITICAL_SECTION_ENTER();
4778 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask);
4779 TCC_CRITICAL_SECTION_LEAVE();
4780 }
4781
hri_tcc_toggle_FCTRLB_CHSEL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4782 static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4783 {
4784 TCC_CRITICAL_SECTION_ENTER();
4785 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask);
4786 TCC_CRITICAL_SECTION_LEAVE();
4787 }
4788
hri_tcc_read_FCTRLB_CHSEL_bf(const void * const hw)4789 static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw)
4790 {
4791 uint32_t tmp;
4792 tmp = ((Tcc *)hw)->FCTRLB.reg;
4793 tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos;
4794 return tmp;
4795 }
4796
hri_tcc_set_FCTRLB_CAPTURE_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4797 static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4798 {
4799 TCC_CRITICAL_SECTION_ENTER();
4800 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask);
4801 TCC_CRITICAL_SECTION_LEAVE();
4802 }
4803
hri_tcc_get_FCTRLB_CAPTURE_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4804 static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4805 {
4806 uint32_t tmp;
4807 tmp = ((Tcc *)hw)->FCTRLB.reg;
4808 tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos;
4809 return tmp;
4810 }
4811
hri_tcc_write_FCTRLB_CAPTURE_bf(const void * const hw,hri_tcc_fctrlb_reg_t data)4812 static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
4813 {
4814 uint32_t tmp;
4815 TCC_CRITICAL_SECTION_ENTER();
4816 tmp = ((Tcc *)hw)->FCTRLB.reg;
4817 tmp &= ~TCC_FCTRLB_CAPTURE_Msk;
4818 tmp |= TCC_FCTRLB_CAPTURE(data);
4819 ((Tcc *)hw)->FCTRLB.reg = tmp;
4820 TCC_CRITICAL_SECTION_LEAVE();
4821 }
4822
hri_tcc_clear_FCTRLB_CAPTURE_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4823 static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4824 {
4825 TCC_CRITICAL_SECTION_ENTER();
4826 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask);
4827 TCC_CRITICAL_SECTION_LEAVE();
4828 }
4829
hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4830 static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4831 {
4832 TCC_CRITICAL_SECTION_ENTER();
4833 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask);
4834 TCC_CRITICAL_SECTION_LEAVE();
4835 }
4836
hri_tcc_read_FCTRLB_CAPTURE_bf(const void * const hw)4837 static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw)
4838 {
4839 uint32_t tmp;
4840 tmp = ((Tcc *)hw)->FCTRLB.reg;
4841 tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos;
4842 return tmp;
4843 }
4844
hri_tcc_set_FCTRLB_BLANKVAL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4845 static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4846 {
4847 TCC_CRITICAL_SECTION_ENTER();
4848 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask);
4849 TCC_CRITICAL_SECTION_LEAVE();
4850 }
4851
hri_tcc_get_FCTRLB_BLANKVAL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4852 static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4853 {
4854 uint32_t tmp;
4855 tmp = ((Tcc *)hw)->FCTRLB.reg;
4856 tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos;
4857 return tmp;
4858 }
4859
hri_tcc_write_FCTRLB_BLANKVAL_bf(const void * const hw,hri_tcc_fctrlb_reg_t data)4860 static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
4861 {
4862 uint32_t tmp;
4863 TCC_CRITICAL_SECTION_ENTER();
4864 tmp = ((Tcc *)hw)->FCTRLB.reg;
4865 tmp &= ~TCC_FCTRLB_BLANKVAL_Msk;
4866 tmp |= TCC_FCTRLB_BLANKVAL(data);
4867 ((Tcc *)hw)->FCTRLB.reg = tmp;
4868 TCC_CRITICAL_SECTION_LEAVE();
4869 }
4870
hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4871 static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4872 {
4873 TCC_CRITICAL_SECTION_ENTER();
4874 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask);
4875 TCC_CRITICAL_SECTION_LEAVE();
4876 }
4877
hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4878 static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4879 {
4880 TCC_CRITICAL_SECTION_ENTER();
4881 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask);
4882 TCC_CRITICAL_SECTION_LEAVE();
4883 }
4884
hri_tcc_read_FCTRLB_BLANKVAL_bf(const void * const hw)4885 static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw)
4886 {
4887 uint32_t tmp;
4888 tmp = ((Tcc *)hw)->FCTRLB.reg;
4889 tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos;
4890 return tmp;
4891 }
4892
hri_tcc_set_FCTRLB_FILTERVAL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4893 static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4894 {
4895 TCC_CRITICAL_SECTION_ENTER();
4896 ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask);
4897 TCC_CRITICAL_SECTION_LEAVE();
4898 }
4899
hri_tcc_get_FCTRLB_FILTERVAL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4900 static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4901 {
4902 uint32_t tmp;
4903 tmp = ((Tcc *)hw)->FCTRLB.reg;
4904 tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos;
4905 return tmp;
4906 }
4907
hri_tcc_write_FCTRLB_FILTERVAL_bf(const void * const hw,hri_tcc_fctrlb_reg_t data)4908 static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data)
4909 {
4910 uint32_t tmp;
4911 TCC_CRITICAL_SECTION_ENTER();
4912 tmp = ((Tcc *)hw)->FCTRLB.reg;
4913 tmp &= ~TCC_FCTRLB_FILTERVAL_Msk;
4914 tmp |= TCC_FCTRLB_FILTERVAL(data);
4915 ((Tcc *)hw)->FCTRLB.reg = tmp;
4916 TCC_CRITICAL_SECTION_LEAVE();
4917 }
4918
hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4919 static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4920 {
4921 TCC_CRITICAL_SECTION_ENTER();
4922 ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask);
4923 TCC_CRITICAL_SECTION_LEAVE();
4924 }
4925
hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void * const hw,hri_tcc_fctrlb_reg_t mask)4926 static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4927 {
4928 TCC_CRITICAL_SECTION_ENTER();
4929 ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask);
4930 TCC_CRITICAL_SECTION_LEAVE();
4931 }
4932
hri_tcc_read_FCTRLB_FILTERVAL_bf(const void * const hw)4933 static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw)
4934 {
4935 uint32_t tmp;
4936 tmp = ((Tcc *)hw)->FCTRLB.reg;
4937 tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos;
4938 return tmp;
4939 }
4940
hri_tcc_set_FCTRLB_reg(const void * const hw,hri_tcc_fctrlb_reg_t mask)4941 static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4942 {
4943 TCC_CRITICAL_SECTION_ENTER();
4944 ((Tcc *)hw)->FCTRLB.reg |= mask;
4945 TCC_CRITICAL_SECTION_LEAVE();
4946 }
4947
hri_tcc_get_FCTRLB_reg(const void * const hw,hri_tcc_fctrlb_reg_t mask)4948 static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4949 {
4950 uint32_t tmp;
4951 tmp = ((Tcc *)hw)->FCTRLB.reg;
4952 tmp &= mask;
4953 return tmp;
4954 }
4955
hri_tcc_write_FCTRLB_reg(const void * const hw,hri_tcc_fctrlb_reg_t data)4956 static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data)
4957 {
4958 TCC_CRITICAL_SECTION_ENTER();
4959 ((Tcc *)hw)->FCTRLB.reg = data;
4960 TCC_CRITICAL_SECTION_LEAVE();
4961 }
4962
hri_tcc_clear_FCTRLB_reg(const void * const hw,hri_tcc_fctrlb_reg_t mask)4963 static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4964 {
4965 TCC_CRITICAL_SECTION_ENTER();
4966 ((Tcc *)hw)->FCTRLB.reg &= ~mask;
4967 TCC_CRITICAL_SECTION_LEAVE();
4968 }
4969
hri_tcc_toggle_FCTRLB_reg(const void * const hw,hri_tcc_fctrlb_reg_t mask)4970 static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask)
4971 {
4972 TCC_CRITICAL_SECTION_ENTER();
4973 ((Tcc *)hw)->FCTRLB.reg ^= mask;
4974 TCC_CRITICAL_SECTION_LEAVE();
4975 }
4976
hri_tcc_read_FCTRLB_reg(const void * const hw)4977 static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw)
4978 {
4979 return ((Tcc *)hw)->FCTRLB.reg;
4980 }
4981
hri_tcc_set_WEXCTRL_DTIEN0_bit(const void * const hw)4982 static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw)
4983 {
4984 TCC_CRITICAL_SECTION_ENTER();
4985 ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0;
4986 TCC_CRITICAL_SECTION_LEAVE();
4987 }
4988
hri_tcc_get_WEXCTRL_DTIEN0_bit(const void * const hw)4989 static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw)
4990 {
4991 uint32_t tmp;
4992 tmp = ((Tcc *)hw)->WEXCTRL.reg;
4993 tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos;
4994 return (bool)tmp;
4995 }
4996
hri_tcc_write_WEXCTRL_DTIEN0_bit(const void * const hw,bool value)4997 static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value)
4998 {
4999 uint32_t tmp;
5000 TCC_CRITICAL_SECTION_ENTER();
5001 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5002 tmp &= ~TCC_WEXCTRL_DTIEN0;
5003 tmp |= value << TCC_WEXCTRL_DTIEN0_Pos;
5004 ((Tcc *)hw)->WEXCTRL.reg = tmp;
5005 TCC_CRITICAL_SECTION_LEAVE();
5006 }
5007
hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void * const hw)5008 static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw)
5009 {
5010 TCC_CRITICAL_SECTION_ENTER();
5011 ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0;
5012 TCC_CRITICAL_SECTION_LEAVE();
5013 }
5014
hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void * const hw)5015 static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw)
5016 {
5017 TCC_CRITICAL_SECTION_ENTER();
5018 ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0;
5019 TCC_CRITICAL_SECTION_LEAVE();
5020 }
5021
hri_tcc_set_WEXCTRL_DTIEN1_bit(const void * const hw)5022 static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw)
5023 {
5024 TCC_CRITICAL_SECTION_ENTER();
5025 ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1;
5026 TCC_CRITICAL_SECTION_LEAVE();
5027 }
5028
hri_tcc_get_WEXCTRL_DTIEN1_bit(const void * const hw)5029 static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw)
5030 {
5031 uint32_t tmp;
5032 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5033 tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos;
5034 return (bool)tmp;
5035 }
5036
hri_tcc_write_WEXCTRL_DTIEN1_bit(const void * const hw,bool value)5037 static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value)
5038 {
5039 uint32_t tmp;
5040 TCC_CRITICAL_SECTION_ENTER();
5041 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5042 tmp &= ~TCC_WEXCTRL_DTIEN1;
5043 tmp |= value << TCC_WEXCTRL_DTIEN1_Pos;
5044 ((Tcc *)hw)->WEXCTRL.reg = tmp;
5045 TCC_CRITICAL_SECTION_LEAVE();
5046 }
5047
hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void * const hw)5048 static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw)
5049 {
5050 TCC_CRITICAL_SECTION_ENTER();
5051 ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1;
5052 TCC_CRITICAL_SECTION_LEAVE();
5053 }
5054
hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void * const hw)5055 static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw)
5056 {
5057 TCC_CRITICAL_SECTION_ENTER();
5058 ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1;
5059 TCC_CRITICAL_SECTION_LEAVE();
5060 }
5061
hri_tcc_set_WEXCTRL_DTIEN2_bit(const void * const hw)5062 static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw)
5063 {
5064 TCC_CRITICAL_SECTION_ENTER();
5065 ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2;
5066 TCC_CRITICAL_SECTION_LEAVE();
5067 }
5068
hri_tcc_get_WEXCTRL_DTIEN2_bit(const void * const hw)5069 static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw)
5070 {
5071 uint32_t tmp;
5072 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5073 tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos;
5074 return (bool)tmp;
5075 }
5076
hri_tcc_write_WEXCTRL_DTIEN2_bit(const void * const hw,bool value)5077 static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value)
5078 {
5079 uint32_t tmp;
5080 TCC_CRITICAL_SECTION_ENTER();
5081 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5082 tmp &= ~TCC_WEXCTRL_DTIEN2;
5083 tmp |= value << TCC_WEXCTRL_DTIEN2_Pos;
5084 ((Tcc *)hw)->WEXCTRL.reg = tmp;
5085 TCC_CRITICAL_SECTION_LEAVE();
5086 }
5087
hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void * const hw)5088 static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw)
5089 {
5090 TCC_CRITICAL_SECTION_ENTER();
5091 ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2;
5092 TCC_CRITICAL_SECTION_LEAVE();
5093 }
5094
hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void * const hw)5095 static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw)
5096 {
5097 TCC_CRITICAL_SECTION_ENTER();
5098 ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2;
5099 TCC_CRITICAL_SECTION_LEAVE();
5100 }
5101
hri_tcc_set_WEXCTRL_DTIEN3_bit(const void * const hw)5102 static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw)
5103 {
5104 TCC_CRITICAL_SECTION_ENTER();
5105 ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3;
5106 TCC_CRITICAL_SECTION_LEAVE();
5107 }
5108
hri_tcc_get_WEXCTRL_DTIEN3_bit(const void * const hw)5109 static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw)
5110 {
5111 uint32_t tmp;
5112 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5113 tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos;
5114 return (bool)tmp;
5115 }
5116
hri_tcc_write_WEXCTRL_DTIEN3_bit(const void * const hw,bool value)5117 static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value)
5118 {
5119 uint32_t tmp;
5120 TCC_CRITICAL_SECTION_ENTER();
5121 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5122 tmp &= ~TCC_WEXCTRL_DTIEN3;
5123 tmp |= value << TCC_WEXCTRL_DTIEN3_Pos;
5124 ((Tcc *)hw)->WEXCTRL.reg = tmp;
5125 TCC_CRITICAL_SECTION_LEAVE();
5126 }
5127
hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void * const hw)5128 static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw)
5129 {
5130 TCC_CRITICAL_SECTION_ENTER();
5131 ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3;
5132 TCC_CRITICAL_SECTION_LEAVE();
5133 }
5134
hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void * const hw)5135 static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw)
5136 {
5137 TCC_CRITICAL_SECTION_ENTER();
5138 ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3;
5139 TCC_CRITICAL_SECTION_LEAVE();
5140 }
5141
hri_tcc_set_WEXCTRL_OTMX_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5142 static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5143 {
5144 TCC_CRITICAL_SECTION_ENTER();
5145 ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask);
5146 TCC_CRITICAL_SECTION_LEAVE();
5147 }
5148
hri_tcc_get_WEXCTRL_OTMX_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5149 static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5150 {
5151 uint32_t tmp;
5152 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5153 tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos;
5154 return tmp;
5155 }
5156
hri_tcc_write_WEXCTRL_OTMX_bf(const void * const hw,hri_tcc_wexctrl_reg_t data)5157 static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
5158 {
5159 uint32_t tmp;
5160 TCC_CRITICAL_SECTION_ENTER();
5161 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5162 tmp &= ~TCC_WEXCTRL_OTMX_Msk;
5163 tmp |= TCC_WEXCTRL_OTMX(data);
5164 ((Tcc *)hw)->WEXCTRL.reg = tmp;
5165 TCC_CRITICAL_SECTION_LEAVE();
5166 }
5167
hri_tcc_clear_WEXCTRL_OTMX_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5168 static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5169 {
5170 TCC_CRITICAL_SECTION_ENTER();
5171 ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask);
5172 TCC_CRITICAL_SECTION_LEAVE();
5173 }
5174
hri_tcc_toggle_WEXCTRL_OTMX_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5175 static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5176 {
5177 TCC_CRITICAL_SECTION_ENTER();
5178 ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask);
5179 TCC_CRITICAL_SECTION_LEAVE();
5180 }
5181
hri_tcc_read_WEXCTRL_OTMX_bf(const void * const hw)5182 static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw)
5183 {
5184 uint32_t tmp;
5185 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5186 tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos;
5187 return tmp;
5188 }
5189
hri_tcc_set_WEXCTRL_DTLS_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5190 static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5191 {
5192 TCC_CRITICAL_SECTION_ENTER();
5193 ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask);
5194 TCC_CRITICAL_SECTION_LEAVE();
5195 }
5196
hri_tcc_get_WEXCTRL_DTLS_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5197 static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5198 {
5199 uint32_t tmp;
5200 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5201 tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos;
5202 return tmp;
5203 }
5204
hri_tcc_write_WEXCTRL_DTLS_bf(const void * const hw,hri_tcc_wexctrl_reg_t data)5205 static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
5206 {
5207 uint32_t tmp;
5208 TCC_CRITICAL_SECTION_ENTER();
5209 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5210 tmp &= ~TCC_WEXCTRL_DTLS_Msk;
5211 tmp |= TCC_WEXCTRL_DTLS(data);
5212 ((Tcc *)hw)->WEXCTRL.reg = tmp;
5213 TCC_CRITICAL_SECTION_LEAVE();
5214 }
5215
hri_tcc_clear_WEXCTRL_DTLS_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5216 static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5217 {
5218 TCC_CRITICAL_SECTION_ENTER();
5219 ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask);
5220 TCC_CRITICAL_SECTION_LEAVE();
5221 }
5222
hri_tcc_toggle_WEXCTRL_DTLS_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5223 static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5224 {
5225 TCC_CRITICAL_SECTION_ENTER();
5226 ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask);
5227 TCC_CRITICAL_SECTION_LEAVE();
5228 }
5229
hri_tcc_read_WEXCTRL_DTLS_bf(const void * const hw)5230 static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw)
5231 {
5232 uint32_t tmp;
5233 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5234 tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos;
5235 return tmp;
5236 }
5237
hri_tcc_set_WEXCTRL_DTHS_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5238 static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5239 {
5240 TCC_CRITICAL_SECTION_ENTER();
5241 ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask);
5242 TCC_CRITICAL_SECTION_LEAVE();
5243 }
5244
hri_tcc_get_WEXCTRL_DTHS_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5245 static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5246 {
5247 uint32_t tmp;
5248 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5249 tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos;
5250 return tmp;
5251 }
5252
hri_tcc_write_WEXCTRL_DTHS_bf(const void * const hw,hri_tcc_wexctrl_reg_t data)5253 static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data)
5254 {
5255 uint32_t tmp;
5256 TCC_CRITICAL_SECTION_ENTER();
5257 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5258 tmp &= ~TCC_WEXCTRL_DTHS_Msk;
5259 tmp |= TCC_WEXCTRL_DTHS(data);
5260 ((Tcc *)hw)->WEXCTRL.reg = tmp;
5261 TCC_CRITICAL_SECTION_LEAVE();
5262 }
5263
hri_tcc_clear_WEXCTRL_DTHS_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5264 static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5265 {
5266 TCC_CRITICAL_SECTION_ENTER();
5267 ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask);
5268 TCC_CRITICAL_SECTION_LEAVE();
5269 }
5270
hri_tcc_toggle_WEXCTRL_DTHS_bf(const void * const hw,hri_tcc_wexctrl_reg_t mask)5271 static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5272 {
5273 TCC_CRITICAL_SECTION_ENTER();
5274 ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask);
5275 TCC_CRITICAL_SECTION_LEAVE();
5276 }
5277
hri_tcc_read_WEXCTRL_DTHS_bf(const void * const hw)5278 static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw)
5279 {
5280 uint32_t tmp;
5281 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5282 tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos;
5283 return tmp;
5284 }
5285
hri_tcc_set_WEXCTRL_reg(const void * const hw,hri_tcc_wexctrl_reg_t mask)5286 static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5287 {
5288 TCC_CRITICAL_SECTION_ENTER();
5289 ((Tcc *)hw)->WEXCTRL.reg |= mask;
5290 TCC_CRITICAL_SECTION_LEAVE();
5291 }
5292
hri_tcc_get_WEXCTRL_reg(const void * const hw,hri_tcc_wexctrl_reg_t mask)5293 static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5294 {
5295 uint32_t tmp;
5296 tmp = ((Tcc *)hw)->WEXCTRL.reg;
5297 tmp &= mask;
5298 return tmp;
5299 }
5300
hri_tcc_write_WEXCTRL_reg(const void * const hw,hri_tcc_wexctrl_reg_t data)5301 static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data)
5302 {
5303 TCC_CRITICAL_SECTION_ENTER();
5304 ((Tcc *)hw)->WEXCTRL.reg = data;
5305 TCC_CRITICAL_SECTION_LEAVE();
5306 }
5307
hri_tcc_clear_WEXCTRL_reg(const void * const hw,hri_tcc_wexctrl_reg_t mask)5308 static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5309 {
5310 TCC_CRITICAL_SECTION_ENTER();
5311 ((Tcc *)hw)->WEXCTRL.reg &= ~mask;
5312 TCC_CRITICAL_SECTION_LEAVE();
5313 }
5314
hri_tcc_toggle_WEXCTRL_reg(const void * const hw,hri_tcc_wexctrl_reg_t mask)5315 static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask)
5316 {
5317 TCC_CRITICAL_SECTION_ENTER();
5318 ((Tcc *)hw)->WEXCTRL.reg ^= mask;
5319 TCC_CRITICAL_SECTION_LEAVE();
5320 }
5321
hri_tcc_read_WEXCTRL_reg(const void * const hw)5322 static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw)
5323 {
5324 return ((Tcc *)hw)->WEXCTRL.reg;
5325 }
5326
hri_tcc_set_DRVCTRL_NRE0_bit(const void * const hw)5327 static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw)
5328 {
5329 TCC_CRITICAL_SECTION_ENTER();
5330 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0;
5331 TCC_CRITICAL_SECTION_LEAVE();
5332 }
5333
hri_tcc_get_DRVCTRL_NRE0_bit(const void * const hw)5334 static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw)
5335 {
5336 uint32_t tmp;
5337 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5338 tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos;
5339 return (bool)tmp;
5340 }
5341
hri_tcc_write_DRVCTRL_NRE0_bit(const void * const hw,bool value)5342 static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value)
5343 {
5344 uint32_t tmp;
5345 TCC_CRITICAL_SECTION_ENTER();
5346 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5347 tmp &= ~TCC_DRVCTRL_NRE0;
5348 tmp |= value << TCC_DRVCTRL_NRE0_Pos;
5349 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5350 TCC_CRITICAL_SECTION_LEAVE();
5351 }
5352
hri_tcc_clear_DRVCTRL_NRE0_bit(const void * const hw)5353 static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw)
5354 {
5355 TCC_CRITICAL_SECTION_ENTER();
5356 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0;
5357 TCC_CRITICAL_SECTION_LEAVE();
5358 }
5359
hri_tcc_toggle_DRVCTRL_NRE0_bit(const void * const hw)5360 static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw)
5361 {
5362 TCC_CRITICAL_SECTION_ENTER();
5363 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0;
5364 TCC_CRITICAL_SECTION_LEAVE();
5365 }
5366
hri_tcc_set_DRVCTRL_NRE1_bit(const void * const hw)5367 static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw)
5368 {
5369 TCC_CRITICAL_SECTION_ENTER();
5370 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1;
5371 TCC_CRITICAL_SECTION_LEAVE();
5372 }
5373
hri_tcc_get_DRVCTRL_NRE1_bit(const void * const hw)5374 static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw)
5375 {
5376 uint32_t tmp;
5377 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5378 tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos;
5379 return (bool)tmp;
5380 }
5381
hri_tcc_write_DRVCTRL_NRE1_bit(const void * const hw,bool value)5382 static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value)
5383 {
5384 uint32_t tmp;
5385 TCC_CRITICAL_SECTION_ENTER();
5386 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5387 tmp &= ~TCC_DRVCTRL_NRE1;
5388 tmp |= value << TCC_DRVCTRL_NRE1_Pos;
5389 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5390 TCC_CRITICAL_SECTION_LEAVE();
5391 }
5392
hri_tcc_clear_DRVCTRL_NRE1_bit(const void * const hw)5393 static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw)
5394 {
5395 TCC_CRITICAL_SECTION_ENTER();
5396 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1;
5397 TCC_CRITICAL_SECTION_LEAVE();
5398 }
5399
hri_tcc_toggle_DRVCTRL_NRE1_bit(const void * const hw)5400 static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw)
5401 {
5402 TCC_CRITICAL_SECTION_ENTER();
5403 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1;
5404 TCC_CRITICAL_SECTION_LEAVE();
5405 }
5406
hri_tcc_set_DRVCTRL_NRE2_bit(const void * const hw)5407 static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw)
5408 {
5409 TCC_CRITICAL_SECTION_ENTER();
5410 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2;
5411 TCC_CRITICAL_SECTION_LEAVE();
5412 }
5413
hri_tcc_get_DRVCTRL_NRE2_bit(const void * const hw)5414 static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw)
5415 {
5416 uint32_t tmp;
5417 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5418 tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos;
5419 return (bool)tmp;
5420 }
5421
hri_tcc_write_DRVCTRL_NRE2_bit(const void * const hw,bool value)5422 static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value)
5423 {
5424 uint32_t tmp;
5425 TCC_CRITICAL_SECTION_ENTER();
5426 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5427 tmp &= ~TCC_DRVCTRL_NRE2;
5428 tmp |= value << TCC_DRVCTRL_NRE2_Pos;
5429 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5430 TCC_CRITICAL_SECTION_LEAVE();
5431 }
5432
hri_tcc_clear_DRVCTRL_NRE2_bit(const void * const hw)5433 static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw)
5434 {
5435 TCC_CRITICAL_SECTION_ENTER();
5436 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2;
5437 TCC_CRITICAL_SECTION_LEAVE();
5438 }
5439
hri_tcc_toggle_DRVCTRL_NRE2_bit(const void * const hw)5440 static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw)
5441 {
5442 TCC_CRITICAL_SECTION_ENTER();
5443 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2;
5444 TCC_CRITICAL_SECTION_LEAVE();
5445 }
5446
hri_tcc_set_DRVCTRL_NRE3_bit(const void * const hw)5447 static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw)
5448 {
5449 TCC_CRITICAL_SECTION_ENTER();
5450 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3;
5451 TCC_CRITICAL_SECTION_LEAVE();
5452 }
5453
hri_tcc_get_DRVCTRL_NRE3_bit(const void * const hw)5454 static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw)
5455 {
5456 uint32_t tmp;
5457 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5458 tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos;
5459 return (bool)tmp;
5460 }
5461
hri_tcc_write_DRVCTRL_NRE3_bit(const void * const hw,bool value)5462 static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value)
5463 {
5464 uint32_t tmp;
5465 TCC_CRITICAL_SECTION_ENTER();
5466 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5467 tmp &= ~TCC_DRVCTRL_NRE3;
5468 tmp |= value << TCC_DRVCTRL_NRE3_Pos;
5469 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5470 TCC_CRITICAL_SECTION_LEAVE();
5471 }
5472
hri_tcc_clear_DRVCTRL_NRE3_bit(const void * const hw)5473 static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw)
5474 {
5475 TCC_CRITICAL_SECTION_ENTER();
5476 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3;
5477 TCC_CRITICAL_SECTION_LEAVE();
5478 }
5479
hri_tcc_toggle_DRVCTRL_NRE3_bit(const void * const hw)5480 static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw)
5481 {
5482 TCC_CRITICAL_SECTION_ENTER();
5483 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3;
5484 TCC_CRITICAL_SECTION_LEAVE();
5485 }
5486
hri_tcc_set_DRVCTRL_NRE4_bit(const void * const hw)5487 static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw)
5488 {
5489 TCC_CRITICAL_SECTION_ENTER();
5490 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4;
5491 TCC_CRITICAL_SECTION_LEAVE();
5492 }
5493
hri_tcc_get_DRVCTRL_NRE4_bit(const void * const hw)5494 static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw)
5495 {
5496 uint32_t tmp;
5497 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5498 tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos;
5499 return (bool)tmp;
5500 }
5501
hri_tcc_write_DRVCTRL_NRE4_bit(const void * const hw,bool value)5502 static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value)
5503 {
5504 uint32_t tmp;
5505 TCC_CRITICAL_SECTION_ENTER();
5506 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5507 tmp &= ~TCC_DRVCTRL_NRE4;
5508 tmp |= value << TCC_DRVCTRL_NRE4_Pos;
5509 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5510 TCC_CRITICAL_SECTION_LEAVE();
5511 }
5512
hri_tcc_clear_DRVCTRL_NRE4_bit(const void * const hw)5513 static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw)
5514 {
5515 TCC_CRITICAL_SECTION_ENTER();
5516 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4;
5517 TCC_CRITICAL_SECTION_LEAVE();
5518 }
5519
hri_tcc_toggle_DRVCTRL_NRE4_bit(const void * const hw)5520 static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw)
5521 {
5522 TCC_CRITICAL_SECTION_ENTER();
5523 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4;
5524 TCC_CRITICAL_SECTION_LEAVE();
5525 }
5526
hri_tcc_set_DRVCTRL_NRE5_bit(const void * const hw)5527 static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw)
5528 {
5529 TCC_CRITICAL_SECTION_ENTER();
5530 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5;
5531 TCC_CRITICAL_SECTION_LEAVE();
5532 }
5533
hri_tcc_get_DRVCTRL_NRE5_bit(const void * const hw)5534 static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw)
5535 {
5536 uint32_t tmp;
5537 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5538 tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos;
5539 return (bool)tmp;
5540 }
5541
hri_tcc_write_DRVCTRL_NRE5_bit(const void * const hw,bool value)5542 static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value)
5543 {
5544 uint32_t tmp;
5545 TCC_CRITICAL_SECTION_ENTER();
5546 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5547 tmp &= ~TCC_DRVCTRL_NRE5;
5548 tmp |= value << TCC_DRVCTRL_NRE5_Pos;
5549 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5550 TCC_CRITICAL_SECTION_LEAVE();
5551 }
5552
hri_tcc_clear_DRVCTRL_NRE5_bit(const void * const hw)5553 static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw)
5554 {
5555 TCC_CRITICAL_SECTION_ENTER();
5556 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5;
5557 TCC_CRITICAL_SECTION_LEAVE();
5558 }
5559
hri_tcc_toggle_DRVCTRL_NRE5_bit(const void * const hw)5560 static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw)
5561 {
5562 TCC_CRITICAL_SECTION_ENTER();
5563 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5;
5564 TCC_CRITICAL_SECTION_LEAVE();
5565 }
5566
hri_tcc_set_DRVCTRL_NRE6_bit(const void * const hw)5567 static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw)
5568 {
5569 TCC_CRITICAL_SECTION_ENTER();
5570 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6;
5571 TCC_CRITICAL_SECTION_LEAVE();
5572 }
5573
hri_tcc_get_DRVCTRL_NRE6_bit(const void * const hw)5574 static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw)
5575 {
5576 uint32_t tmp;
5577 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5578 tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos;
5579 return (bool)tmp;
5580 }
5581
hri_tcc_write_DRVCTRL_NRE6_bit(const void * const hw,bool value)5582 static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value)
5583 {
5584 uint32_t tmp;
5585 TCC_CRITICAL_SECTION_ENTER();
5586 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5587 tmp &= ~TCC_DRVCTRL_NRE6;
5588 tmp |= value << TCC_DRVCTRL_NRE6_Pos;
5589 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5590 TCC_CRITICAL_SECTION_LEAVE();
5591 }
5592
hri_tcc_clear_DRVCTRL_NRE6_bit(const void * const hw)5593 static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw)
5594 {
5595 TCC_CRITICAL_SECTION_ENTER();
5596 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6;
5597 TCC_CRITICAL_SECTION_LEAVE();
5598 }
5599
hri_tcc_toggle_DRVCTRL_NRE6_bit(const void * const hw)5600 static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw)
5601 {
5602 TCC_CRITICAL_SECTION_ENTER();
5603 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6;
5604 TCC_CRITICAL_SECTION_LEAVE();
5605 }
5606
hri_tcc_set_DRVCTRL_NRE7_bit(const void * const hw)5607 static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw)
5608 {
5609 TCC_CRITICAL_SECTION_ENTER();
5610 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7;
5611 TCC_CRITICAL_SECTION_LEAVE();
5612 }
5613
hri_tcc_get_DRVCTRL_NRE7_bit(const void * const hw)5614 static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw)
5615 {
5616 uint32_t tmp;
5617 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5618 tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos;
5619 return (bool)tmp;
5620 }
5621
hri_tcc_write_DRVCTRL_NRE7_bit(const void * const hw,bool value)5622 static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value)
5623 {
5624 uint32_t tmp;
5625 TCC_CRITICAL_SECTION_ENTER();
5626 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5627 tmp &= ~TCC_DRVCTRL_NRE7;
5628 tmp |= value << TCC_DRVCTRL_NRE7_Pos;
5629 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5630 TCC_CRITICAL_SECTION_LEAVE();
5631 }
5632
hri_tcc_clear_DRVCTRL_NRE7_bit(const void * const hw)5633 static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw)
5634 {
5635 TCC_CRITICAL_SECTION_ENTER();
5636 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7;
5637 TCC_CRITICAL_SECTION_LEAVE();
5638 }
5639
hri_tcc_toggle_DRVCTRL_NRE7_bit(const void * const hw)5640 static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw)
5641 {
5642 TCC_CRITICAL_SECTION_ENTER();
5643 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7;
5644 TCC_CRITICAL_SECTION_LEAVE();
5645 }
5646
hri_tcc_set_DRVCTRL_NRV0_bit(const void * const hw)5647 static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw)
5648 {
5649 TCC_CRITICAL_SECTION_ENTER();
5650 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0;
5651 TCC_CRITICAL_SECTION_LEAVE();
5652 }
5653
hri_tcc_get_DRVCTRL_NRV0_bit(const void * const hw)5654 static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw)
5655 {
5656 uint32_t tmp;
5657 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5658 tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos;
5659 return (bool)tmp;
5660 }
5661
hri_tcc_write_DRVCTRL_NRV0_bit(const void * const hw,bool value)5662 static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value)
5663 {
5664 uint32_t tmp;
5665 TCC_CRITICAL_SECTION_ENTER();
5666 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5667 tmp &= ~TCC_DRVCTRL_NRV0;
5668 tmp |= value << TCC_DRVCTRL_NRV0_Pos;
5669 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5670 TCC_CRITICAL_SECTION_LEAVE();
5671 }
5672
hri_tcc_clear_DRVCTRL_NRV0_bit(const void * const hw)5673 static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw)
5674 {
5675 TCC_CRITICAL_SECTION_ENTER();
5676 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0;
5677 TCC_CRITICAL_SECTION_LEAVE();
5678 }
5679
hri_tcc_toggle_DRVCTRL_NRV0_bit(const void * const hw)5680 static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw)
5681 {
5682 TCC_CRITICAL_SECTION_ENTER();
5683 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0;
5684 TCC_CRITICAL_SECTION_LEAVE();
5685 }
5686
hri_tcc_set_DRVCTRL_NRV1_bit(const void * const hw)5687 static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw)
5688 {
5689 TCC_CRITICAL_SECTION_ENTER();
5690 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1;
5691 TCC_CRITICAL_SECTION_LEAVE();
5692 }
5693
hri_tcc_get_DRVCTRL_NRV1_bit(const void * const hw)5694 static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw)
5695 {
5696 uint32_t tmp;
5697 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5698 tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos;
5699 return (bool)tmp;
5700 }
5701
hri_tcc_write_DRVCTRL_NRV1_bit(const void * const hw,bool value)5702 static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value)
5703 {
5704 uint32_t tmp;
5705 TCC_CRITICAL_SECTION_ENTER();
5706 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5707 tmp &= ~TCC_DRVCTRL_NRV1;
5708 tmp |= value << TCC_DRVCTRL_NRV1_Pos;
5709 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5710 TCC_CRITICAL_SECTION_LEAVE();
5711 }
5712
hri_tcc_clear_DRVCTRL_NRV1_bit(const void * const hw)5713 static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw)
5714 {
5715 TCC_CRITICAL_SECTION_ENTER();
5716 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1;
5717 TCC_CRITICAL_SECTION_LEAVE();
5718 }
5719
hri_tcc_toggle_DRVCTRL_NRV1_bit(const void * const hw)5720 static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw)
5721 {
5722 TCC_CRITICAL_SECTION_ENTER();
5723 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1;
5724 TCC_CRITICAL_SECTION_LEAVE();
5725 }
5726
hri_tcc_set_DRVCTRL_NRV2_bit(const void * const hw)5727 static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw)
5728 {
5729 TCC_CRITICAL_SECTION_ENTER();
5730 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2;
5731 TCC_CRITICAL_SECTION_LEAVE();
5732 }
5733
hri_tcc_get_DRVCTRL_NRV2_bit(const void * const hw)5734 static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw)
5735 {
5736 uint32_t tmp;
5737 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5738 tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos;
5739 return (bool)tmp;
5740 }
5741
hri_tcc_write_DRVCTRL_NRV2_bit(const void * const hw,bool value)5742 static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value)
5743 {
5744 uint32_t tmp;
5745 TCC_CRITICAL_SECTION_ENTER();
5746 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5747 tmp &= ~TCC_DRVCTRL_NRV2;
5748 tmp |= value << TCC_DRVCTRL_NRV2_Pos;
5749 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5750 TCC_CRITICAL_SECTION_LEAVE();
5751 }
5752
hri_tcc_clear_DRVCTRL_NRV2_bit(const void * const hw)5753 static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw)
5754 {
5755 TCC_CRITICAL_SECTION_ENTER();
5756 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2;
5757 TCC_CRITICAL_SECTION_LEAVE();
5758 }
5759
hri_tcc_toggle_DRVCTRL_NRV2_bit(const void * const hw)5760 static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw)
5761 {
5762 TCC_CRITICAL_SECTION_ENTER();
5763 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2;
5764 TCC_CRITICAL_SECTION_LEAVE();
5765 }
5766
hri_tcc_set_DRVCTRL_NRV3_bit(const void * const hw)5767 static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw)
5768 {
5769 TCC_CRITICAL_SECTION_ENTER();
5770 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3;
5771 TCC_CRITICAL_SECTION_LEAVE();
5772 }
5773
hri_tcc_get_DRVCTRL_NRV3_bit(const void * const hw)5774 static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw)
5775 {
5776 uint32_t tmp;
5777 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5778 tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos;
5779 return (bool)tmp;
5780 }
5781
hri_tcc_write_DRVCTRL_NRV3_bit(const void * const hw,bool value)5782 static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value)
5783 {
5784 uint32_t tmp;
5785 TCC_CRITICAL_SECTION_ENTER();
5786 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5787 tmp &= ~TCC_DRVCTRL_NRV3;
5788 tmp |= value << TCC_DRVCTRL_NRV3_Pos;
5789 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5790 TCC_CRITICAL_SECTION_LEAVE();
5791 }
5792
hri_tcc_clear_DRVCTRL_NRV3_bit(const void * const hw)5793 static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw)
5794 {
5795 TCC_CRITICAL_SECTION_ENTER();
5796 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3;
5797 TCC_CRITICAL_SECTION_LEAVE();
5798 }
5799
hri_tcc_toggle_DRVCTRL_NRV3_bit(const void * const hw)5800 static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw)
5801 {
5802 TCC_CRITICAL_SECTION_ENTER();
5803 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3;
5804 TCC_CRITICAL_SECTION_LEAVE();
5805 }
5806
hri_tcc_set_DRVCTRL_NRV4_bit(const void * const hw)5807 static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw)
5808 {
5809 TCC_CRITICAL_SECTION_ENTER();
5810 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4;
5811 TCC_CRITICAL_SECTION_LEAVE();
5812 }
5813
hri_tcc_get_DRVCTRL_NRV4_bit(const void * const hw)5814 static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw)
5815 {
5816 uint32_t tmp;
5817 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5818 tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos;
5819 return (bool)tmp;
5820 }
5821
hri_tcc_write_DRVCTRL_NRV4_bit(const void * const hw,bool value)5822 static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value)
5823 {
5824 uint32_t tmp;
5825 TCC_CRITICAL_SECTION_ENTER();
5826 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5827 tmp &= ~TCC_DRVCTRL_NRV4;
5828 tmp |= value << TCC_DRVCTRL_NRV4_Pos;
5829 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5830 TCC_CRITICAL_SECTION_LEAVE();
5831 }
5832
hri_tcc_clear_DRVCTRL_NRV4_bit(const void * const hw)5833 static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw)
5834 {
5835 TCC_CRITICAL_SECTION_ENTER();
5836 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4;
5837 TCC_CRITICAL_SECTION_LEAVE();
5838 }
5839
hri_tcc_toggle_DRVCTRL_NRV4_bit(const void * const hw)5840 static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw)
5841 {
5842 TCC_CRITICAL_SECTION_ENTER();
5843 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4;
5844 TCC_CRITICAL_SECTION_LEAVE();
5845 }
5846
hri_tcc_set_DRVCTRL_NRV5_bit(const void * const hw)5847 static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw)
5848 {
5849 TCC_CRITICAL_SECTION_ENTER();
5850 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5;
5851 TCC_CRITICAL_SECTION_LEAVE();
5852 }
5853
hri_tcc_get_DRVCTRL_NRV5_bit(const void * const hw)5854 static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw)
5855 {
5856 uint32_t tmp;
5857 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5858 tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos;
5859 return (bool)tmp;
5860 }
5861
hri_tcc_write_DRVCTRL_NRV5_bit(const void * const hw,bool value)5862 static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value)
5863 {
5864 uint32_t tmp;
5865 TCC_CRITICAL_SECTION_ENTER();
5866 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5867 tmp &= ~TCC_DRVCTRL_NRV5;
5868 tmp |= value << TCC_DRVCTRL_NRV5_Pos;
5869 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5870 TCC_CRITICAL_SECTION_LEAVE();
5871 }
5872
hri_tcc_clear_DRVCTRL_NRV5_bit(const void * const hw)5873 static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw)
5874 {
5875 TCC_CRITICAL_SECTION_ENTER();
5876 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5;
5877 TCC_CRITICAL_SECTION_LEAVE();
5878 }
5879
hri_tcc_toggle_DRVCTRL_NRV5_bit(const void * const hw)5880 static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw)
5881 {
5882 TCC_CRITICAL_SECTION_ENTER();
5883 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5;
5884 TCC_CRITICAL_SECTION_LEAVE();
5885 }
5886
hri_tcc_set_DRVCTRL_NRV6_bit(const void * const hw)5887 static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw)
5888 {
5889 TCC_CRITICAL_SECTION_ENTER();
5890 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6;
5891 TCC_CRITICAL_SECTION_LEAVE();
5892 }
5893
hri_tcc_get_DRVCTRL_NRV6_bit(const void * const hw)5894 static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw)
5895 {
5896 uint32_t tmp;
5897 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5898 tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos;
5899 return (bool)tmp;
5900 }
5901
hri_tcc_write_DRVCTRL_NRV6_bit(const void * const hw,bool value)5902 static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value)
5903 {
5904 uint32_t tmp;
5905 TCC_CRITICAL_SECTION_ENTER();
5906 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5907 tmp &= ~TCC_DRVCTRL_NRV6;
5908 tmp |= value << TCC_DRVCTRL_NRV6_Pos;
5909 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5910 TCC_CRITICAL_SECTION_LEAVE();
5911 }
5912
hri_tcc_clear_DRVCTRL_NRV6_bit(const void * const hw)5913 static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw)
5914 {
5915 TCC_CRITICAL_SECTION_ENTER();
5916 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6;
5917 TCC_CRITICAL_SECTION_LEAVE();
5918 }
5919
hri_tcc_toggle_DRVCTRL_NRV6_bit(const void * const hw)5920 static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw)
5921 {
5922 TCC_CRITICAL_SECTION_ENTER();
5923 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6;
5924 TCC_CRITICAL_SECTION_LEAVE();
5925 }
5926
hri_tcc_set_DRVCTRL_NRV7_bit(const void * const hw)5927 static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw)
5928 {
5929 TCC_CRITICAL_SECTION_ENTER();
5930 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7;
5931 TCC_CRITICAL_SECTION_LEAVE();
5932 }
5933
hri_tcc_get_DRVCTRL_NRV7_bit(const void * const hw)5934 static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw)
5935 {
5936 uint32_t tmp;
5937 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5938 tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos;
5939 return (bool)tmp;
5940 }
5941
hri_tcc_write_DRVCTRL_NRV7_bit(const void * const hw,bool value)5942 static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value)
5943 {
5944 uint32_t tmp;
5945 TCC_CRITICAL_SECTION_ENTER();
5946 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5947 tmp &= ~TCC_DRVCTRL_NRV7;
5948 tmp |= value << TCC_DRVCTRL_NRV7_Pos;
5949 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5950 TCC_CRITICAL_SECTION_LEAVE();
5951 }
5952
hri_tcc_clear_DRVCTRL_NRV7_bit(const void * const hw)5953 static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw)
5954 {
5955 TCC_CRITICAL_SECTION_ENTER();
5956 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7;
5957 TCC_CRITICAL_SECTION_LEAVE();
5958 }
5959
hri_tcc_toggle_DRVCTRL_NRV7_bit(const void * const hw)5960 static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw)
5961 {
5962 TCC_CRITICAL_SECTION_ENTER();
5963 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7;
5964 TCC_CRITICAL_SECTION_LEAVE();
5965 }
5966
hri_tcc_set_DRVCTRL_INVEN0_bit(const void * const hw)5967 static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw)
5968 {
5969 TCC_CRITICAL_SECTION_ENTER();
5970 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0;
5971 TCC_CRITICAL_SECTION_LEAVE();
5972 }
5973
hri_tcc_get_DRVCTRL_INVEN0_bit(const void * const hw)5974 static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw)
5975 {
5976 uint32_t tmp;
5977 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5978 tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos;
5979 return (bool)tmp;
5980 }
5981
hri_tcc_write_DRVCTRL_INVEN0_bit(const void * const hw,bool value)5982 static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value)
5983 {
5984 uint32_t tmp;
5985 TCC_CRITICAL_SECTION_ENTER();
5986 tmp = ((Tcc *)hw)->DRVCTRL.reg;
5987 tmp &= ~TCC_DRVCTRL_INVEN0;
5988 tmp |= value << TCC_DRVCTRL_INVEN0_Pos;
5989 ((Tcc *)hw)->DRVCTRL.reg = tmp;
5990 TCC_CRITICAL_SECTION_LEAVE();
5991 }
5992
hri_tcc_clear_DRVCTRL_INVEN0_bit(const void * const hw)5993 static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw)
5994 {
5995 TCC_CRITICAL_SECTION_ENTER();
5996 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0;
5997 TCC_CRITICAL_SECTION_LEAVE();
5998 }
5999
hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void * const hw)6000 static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw)
6001 {
6002 TCC_CRITICAL_SECTION_ENTER();
6003 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0;
6004 TCC_CRITICAL_SECTION_LEAVE();
6005 }
6006
hri_tcc_set_DRVCTRL_INVEN1_bit(const void * const hw)6007 static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw)
6008 {
6009 TCC_CRITICAL_SECTION_ENTER();
6010 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1;
6011 TCC_CRITICAL_SECTION_LEAVE();
6012 }
6013
hri_tcc_get_DRVCTRL_INVEN1_bit(const void * const hw)6014 static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw)
6015 {
6016 uint32_t tmp;
6017 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6018 tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos;
6019 return (bool)tmp;
6020 }
6021
hri_tcc_write_DRVCTRL_INVEN1_bit(const void * const hw,bool value)6022 static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value)
6023 {
6024 uint32_t tmp;
6025 TCC_CRITICAL_SECTION_ENTER();
6026 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6027 tmp &= ~TCC_DRVCTRL_INVEN1;
6028 tmp |= value << TCC_DRVCTRL_INVEN1_Pos;
6029 ((Tcc *)hw)->DRVCTRL.reg = tmp;
6030 TCC_CRITICAL_SECTION_LEAVE();
6031 }
6032
hri_tcc_clear_DRVCTRL_INVEN1_bit(const void * const hw)6033 static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw)
6034 {
6035 TCC_CRITICAL_SECTION_ENTER();
6036 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1;
6037 TCC_CRITICAL_SECTION_LEAVE();
6038 }
6039
hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void * const hw)6040 static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw)
6041 {
6042 TCC_CRITICAL_SECTION_ENTER();
6043 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1;
6044 TCC_CRITICAL_SECTION_LEAVE();
6045 }
6046
hri_tcc_set_DRVCTRL_INVEN2_bit(const void * const hw)6047 static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw)
6048 {
6049 TCC_CRITICAL_SECTION_ENTER();
6050 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2;
6051 TCC_CRITICAL_SECTION_LEAVE();
6052 }
6053
hri_tcc_get_DRVCTRL_INVEN2_bit(const void * const hw)6054 static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw)
6055 {
6056 uint32_t tmp;
6057 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6058 tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos;
6059 return (bool)tmp;
6060 }
6061
hri_tcc_write_DRVCTRL_INVEN2_bit(const void * const hw,bool value)6062 static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value)
6063 {
6064 uint32_t tmp;
6065 TCC_CRITICAL_SECTION_ENTER();
6066 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6067 tmp &= ~TCC_DRVCTRL_INVEN2;
6068 tmp |= value << TCC_DRVCTRL_INVEN2_Pos;
6069 ((Tcc *)hw)->DRVCTRL.reg = tmp;
6070 TCC_CRITICAL_SECTION_LEAVE();
6071 }
6072
hri_tcc_clear_DRVCTRL_INVEN2_bit(const void * const hw)6073 static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw)
6074 {
6075 TCC_CRITICAL_SECTION_ENTER();
6076 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2;
6077 TCC_CRITICAL_SECTION_LEAVE();
6078 }
6079
hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void * const hw)6080 static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw)
6081 {
6082 TCC_CRITICAL_SECTION_ENTER();
6083 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2;
6084 TCC_CRITICAL_SECTION_LEAVE();
6085 }
6086
hri_tcc_set_DRVCTRL_INVEN3_bit(const void * const hw)6087 static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw)
6088 {
6089 TCC_CRITICAL_SECTION_ENTER();
6090 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3;
6091 TCC_CRITICAL_SECTION_LEAVE();
6092 }
6093
hri_tcc_get_DRVCTRL_INVEN3_bit(const void * const hw)6094 static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw)
6095 {
6096 uint32_t tmp;
6097 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6098 tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos;
6099 return (bool)tmp;
6100 }
6101
hri_tcc_write_DRVCTRL_INVEN3_bit(const void * const hw,bool value)6102 static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value)
6103 {
6104 uint32_t tmp;
6105 TCC_CRITICAL_SECTION_ENTER();
6106 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6107 tmp &= ~TCC_DRVCTRL_INVEN3;
6108 tmp |= value << TCC_DRVCTRL_INVEN3_Pos;
6109 ((Tcc *)hw)->DRVCTRL.reg = tmp;
6110 TCC_CRITICAL_SECTION_LEAVE();
6111 }
6112
hri_tcc_clear_DRVCTRL_INVEN3_bit(const void * const hw)6113 static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw)
6114 {
6115 TCC_CRITICAL_SECTION_ENTER();
6116 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3;
6117 TCC_CRITICAL_SECTION_LEAVE();
6118 }
6119
hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void * const hw)6120 static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw)
6121 {
6122 TCC_CRITICAL_SECTION_ENTER();
6123 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3;
6124 TCC_CRITICAL_SECTION_LEAVE();
6125 }
6126
hri_tcc_set_DRVCTRL_INVEN4_bit(const void * const hw)6127 static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw)
6128 {
6129 TCC_CRITICAL_SECTION_ENTER();
6130 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4;
6131 TCC_CRITICAL_SECTION_LEAVE();
6132 }
6133
hri_tcc_get_DRVCTRL_INVEN4_bit(const void * const hw)6134 static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw)
6135 {
6136 uint32_t tmp;
6137 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6138 tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos;
6139 return (bool)tmp;
6140 }
6141
hri_tcc_write_DRVCTRL_INVEN4_bit(const void * const hw,bool value)6142 static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value)
6143 {
6144 uint32_t tmp;
6145 TCC_CRITICAL_SECTION_ENTER();
6146 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6147 tmp &= ~TCC_DRVCTRL_INVEN4;
6148 tmp |= value << TCC_DRVCTRL_INVEN4_Pos;
6149 ((Tcc *)hw)->DRVCTRL.reg = tmp;
6150 TCC_CRITICAL_SECTION_LEAVE();
6151 }
6152
hri_tcc_clear_DRVCTRL_INVEN4_bit(const void * const hw)6153 static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw)
6154 {
6155 TCC_CRITICAL_SECTION_ENTER();
6156 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4;
6157 TCC_CRITICAL_SECTION_LEAVE();
6158 }
6159
hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void * const hw)6160 static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw)
6161 {
6162 TCC_CRITICAL_SECTION_ENTER();
6163 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4;
6164 TCC_CRITICAL_SECTION_LEAVE();
6165 }
6166
hri_tcc_set_DRVCTRL_INVEN5_bit(const void * const hw)6167 static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw)
6168 {
6169 TCC_CRITICAL_SECTION_ENTER();
6170 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5;
6171 TCC_CRITICAL_SECTION_LEAVE();
6172 }
6173
hri_tcc_get_DRVCTRL_INVEN5_bit(const void * const hw)6174 static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw)
6175 {
6176 uint32_t tmp;
6177 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6178 tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos;
6179 return (bool)tmp;
6180 }
6181
hri_tcc_write_DRVCTRL_INVEN5_bit(const void * const hw,bool value)6182 static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value)
6183 {
6184 uint32_t tmp;
6185 TCC_CRITICAL_SECTION_ENTER();
6186 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6187 tmp &= ~TCC_DRVCTRL_INVEN5;
6188 tmp |= value << TCC_DRVCTRL_INVEN5_Pos;
6189 ((Tcc *)hw)->DRVCTRL.reg = tmp;
6190 TCC_CRITICAL_SECTION_LEAVE();
6191 }
6192
hri_tcc_clear_DRVCTRL_INVEN5_bit(const void * const hw)6193 static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw)
6194 {
6195 TCC_CRITICAL_SECTION_ENTER();
6196 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5;
6197 TCC_CRITICAL_SECTION_LEAVE();
6198 }
6199
hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void * const hw)6200 static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw)
6201 {
6202 TCC_CRITICAL_SECTION_ENTER();
6203 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5;
6204 TCC_CRITICAL_SECTION_LEAVE();
6205 }
6206
hri_tcc_set_DRVCTRL_INVEN6_bit(const void * const hw)6207 static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw)
6208 {
6209 TCC_CRITICAL_SECTION_ENTER();
6210 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6;
6211 TCC_CRITICAL_SECTION_LEAVE();
6212 }
6213
hri_tcc_get_DRVCTRL_INVEN6_bit(const void * const hw)6214 static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw)
6215 {
6216 uint32_t tmp;
6217 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6218 tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos;
6219 return (bool)tmp;
6220 }
6221
hri_tcc_write_DRVCTRL_INVEN6_bit(const void * const hw,bool value)6222 static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value)
6223 {
6224 uint32_t tmp;
6225 TCC_CRITICAL_SECTION_ENTER();
6226 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6227 tmp &= ~TCC_DRVCTRL_INVEN6;
6228 tmp |= value << TCC_DRVCTRL_INVEN6_Pos;
6229 ((Tcc *)hw)->DRVCTRL.reg = tmp;
6230 TCC_CRITICAL_SECTION_LEAVE();
6231 }
6232
hri_tcc_clear_DRVCTRL_INVEN6_bit(const void * const hw)6233 static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw)
6234 {
6235 TCC_CRITICAL_SECTION_ENTER();
6236 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6;
6237 TCC_CRITICAL_SECTION_LEAVE();
6238 }
6239
hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void * const hw)6240 static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw)
6241 {
6242 TCC_CRITICAL_SECTION_ENTER();
6243 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6;
6244 TCC_CRITICAL_SECTION_LEAVE();
6245 }
6246
hri_tcc_set_DRVCTRL_INVEN7_bit(const void * const hw)6247 static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw)
6248 {
6249 TCC_CRITICAL_SECTION_ENTER();
6250 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7;
6251 TCC_CRITICAL_SECTION_LEAVE();
6252 }
6253
hri_tcc_get_DRVCTRL_INVEN7_bit(const void * const hw)6254 static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw)
6255 {
6256 uint32_t tmp;
6257 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6258 tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos;
6259 return (bool)tmp;
6260 }
6261
hri_tcc_write_DRVCTRL_INVEN7_bit(const void * const hw,bool value)6262 static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value)
6263 {
6264 uint32_t tmp;
6265 TCC_CRITICAL_SECTION_ENTER();
6266 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6267 tmp &= ~TCC_DRVCTRL_INVEN7;
6268 tmp |= value << TCC_DRVCTRL_INVEN7_Pos;
6269 ((Tcc *)hw)->DRVCTRL.reg = tmp;
6270 TCC_CRITICAL_SECTION_LEAVE();
6271 }
6272
hri_tcc_clear_DRVCTRL_INVEN7_bit(const void * const hw)6273 static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw)
6274 {
6275 TCC_CRITICAL_SECTION_ENTER();
6276 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7;
6277 TCC_CRITICAL_SECTION_LEAVE();
6278 }
6279
hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void * const hw)6280 static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw)
6281 {
6282 TCC_CRITICAL_SECTION_ENTER();
6283 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7;
6284 TCC_CRITICAL_SECTION_LEAVE();
6285 }
6286
hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void * const hw,hri_tcc_drvctrl_reg_t mask)6287 static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6288 {
6289 TCC_CRITICAL_SECTION_ENTER();
6290 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask);
6291 TCC_CRITICAL_SECTION_LEAVE();
6292 }
6293
hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void * const hw,hri_tcc_drvctrl_reg_t mask)6294 static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6295 {
6296 uint32_t tmp;
6297 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6298 tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos;
6299 return tmp;
6300 }
6301
hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void * const hw,hri_tcc_drvctrl_reg_t data)6302 static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
6303 {
6304 uint32_t tmp;
6305 TCC_CRITICAL_SECTION_ENTER();
6306 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6307 tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk;
6308 tmp |= TCC_DRVCTRL_FILTERVAL0(data);
6309 ((Tcc *)hw)->DRVCTRL.reg = tmp;
6310 TCC_CRITICAL_SECTION_LEAVE();
6311 }
6312
hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void * const hw,hri_tcc_drvctrl_reg_t mask)6313 static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6314 {
6315 TCC_CRITICAL_SECTION_ENTER();
6316 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask);
6317 TCC_CRITICAL_SECTION_LEAVE();
6318 }
6319
hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void * const hw,hri_tcc_drvctrl_reg_t mask)6320 static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6321 {
6322 TCC_CRITICAL_SECTION_ENTER();
6323 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask);
6324 TCC_CRITICAL_SECTION_LEAVE();
6325 }
6326
hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void * const hw)6327 static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw)
6328 {
6329 uint32_t tmp;
6330 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6331 tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos;
6332 return tmp;
6333 }
6334
hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void * const hw,hri_tcc_drvctrl_reg_t mask)6335 static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6336 {
6337 TCC_CRITICAL_SECTION_ENTER();
6338 ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask);
6339 TCC_CRITICAL_SECTION_LEAVE();
6340 }
6341
hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void * const hw,hri_tcc_drvctrl_reg_t mask)6342 static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6343 {
6344 uint32_t tmp;
6345 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6346 tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos;
6347 return tmp;
6348 }
6349
hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void * const hw,hri_tcc_drvctrl_reg_t data)6350 static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data)
6351 {
6352 uint32_t tmp;
6353 TCC_CRITICAL_SECTION_ENTER();
6354 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6355 tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk;
6356 tmp |= TCC_DRVCTRL_FILTERVAL1(data);
6357 ((Tcc *)hw)->DRVCTRL.reg = tmp;
6358 TCC_CRITICAL_SECTION_LEAVE();
6359 }
6360
hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void * const hw,hri_tcc_drvctrl_reg_t mask)6361 static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6362 {
6363 TCC_CRITICAL_SECTION_ENTER();
6364 ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask);
6365 TCC_CRITICAL_SECTION_LEAVE();
6366 }
6367
hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void * const hw,hri_tcc_drvctrl_reg_t mask)6368 static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6369 {
6370 TCC_CRITICAL_SECTION_ENTER();
6371 ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask);
6372 TCC_CRITICAL_SECTION_LEAVE();
6373 }
6374
hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void * const hw)6375 static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw)
6376 {
6377 uint32_t tmp;
6378 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6379 tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos;
6380 return tmp;
6381 }
6382
hri_tcc_set_DRVCTRL_reg(const void * const hw,hri_tcc_drvctrl_reg_t mask)6383 static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6384 {
6385 TCC_CRITICAL_SECTION_ENTER();
6386 ((Tcc *)hw)->DRVCTRL.reg |= mask;
6387 TCC_CRITICAL_SECTION_LEAVE();
6388 }
6389
hri_tcc_get_DRVCTRL_reg(const void * const hw,hri_tcc_drvctrl_reg_t mask)6390 static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6391 {
6392 uint32_t tmp;
6393 tmp = ((Tcc *)hw)->DRVCTRL.reg;
6394 tmp &= mask;
6395 return tmp;
6396 }
6397
hri_tcc_write_DRVCTRL_reg(const void * const hw,hri_tcc_drvctrl_reg_t data)6398 static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data)
6399 {
6400 TCC_CRITICAL_SECTION_ENTER();
6401 ((Tcc *)hw)->DRVCTRL.reg = data;
6402 TCC_CRITICAL_SECTION_LEAVE();
6403 }
6404
hri_tcc_clear_DRVCTRL_reg(const void * const hw,hri_tcc_drvctrl_reg_t mask)6405 static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6406 {
6407 TCC_CRITICAL_SECTION_ENTER();
6408 ((Tcc *)hw)->DRVCTRL.reg &= ~mask;
6409 TCC_CRITICAL_SECTION_LEAVE();
6410 }
6411
hri_tcc_toggle_DRVCTRL_reg(const void * const hw,hri_tcc_drvctrl_reg_t mask)6412 static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask)
6413 {
6414 TCC_CRITICAL_SECTION_ENTER();
6415 ((Tcc *)hw)->DRVCTRL.reg ^= mask;
6416 TCC_CRITICAL_SECTION_LEAVE();
6417 }
6418
hri_tcc_read_DRVCTRL_reg(const void * const hw)6419 static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw)
6420 {
6421 return ((Tcc *)hw)->DRVCTRL.reg;
6422 }
6423
hri_tcc_set_DBGCTRL_DBGRUN_bit(const void * const hw)6424 static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw)
6425 {
6426 TCC_CRITICAL_SECTION_ENTER();
6427 ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN;
6428 TCC_CRITICAL_SECTION_LEAVE();
6429 }
6430
hri_tcc_get_DBGCTRL_DBGRUN_bit(const void * const hw)6431 static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw)
6432 {
6433 uint8_t tmp;
6434 tmp = ((Tcc *)hw)->DBGCTRL.reg;
6435 tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos;
6436 return (bool)tmp;
6437 }
6438
hri_tcc_write_DBGCTRL_DBGRUN_bit(const void * const hw,bool value)6439 static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value)
6440 {
6441 uint8_t tmp;
6442 TCC_CRITICAL_SECTION_ENTER();
6443 tmp = ((Tcc *)hw)->DBGCTRL.reg;
6444 tmp &= ~TCC_DBGCTRL_DBGRUN;
6445 tmp |= value << TCC_DBGCTRL_DBGRUN_Pos;
6446 ((Tcc *)hw)->DBGCTRL.reg = tmp;
6447 TCC_CRITICAL_SECTION_LEAVE();
6448 }
6449
hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void * const hw)6450 static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw)
6451 {
6452 TCC_CRITICAL_SECTION_ENTER();
6453 ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN;
6454 TCC_CRITICAL_SECTION_LEAVE();
6455 }
6456
hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void * const hw)6457 static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw)
6458 {
6459 TCC_CRITICAL_SECTION_ENTER();
6460 ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN;
6461 TCC_CRITICAL_SECTION_LEAVE();
6462 }
6463
hri_tcc_set_DBGCTRL_FDDBD_bit(const void * const hw)6464 static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw)
6465 {
6466 TCC_CRITICAL_SECTION_ENTER();
6467 ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD;
6468 TCC_CRITICAL_SECTION_LEAVE();
6469 }
6470
hri_tcc_get_DBGCTRL_FDDBD_bit(const void * const hw)6471 static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw)
6472 {
6473 uint8_t tmp;
6474 tmp = ((Tcc *)hw)->DBGCTRL.reg;
6475 tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos;
6476 return (bool)tmp;
6477 }
6478
hri_tcc_write_DBGCTRL_FDDBD_bit(const void * const hw,bool value)6479 static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value)
6480 {
6481 uint8_t tmp;
6482 TCC_CRITICAL_SECTION_ENTER();
6483 tmp = ((Tcc *)hw)->DBGCTRL.reg;
6484 tmp &= ~TCC_DBGCTRL_FDDBD;
6485 tmp |= value << TCC_DBGCTRL_FDDBD_Pos;
6486 ((Tcc *)hw)->DBGCTRL.reg = tmp;
6487 TCC_CRITICAL_SECTION_LEAVE();
6488 }
6489
hri_tcc_clear_DBGCTRL_FDDBD_bit(const void * const hw)6490 static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw)
6491 {
6492 TCC_CRITICAL_SECTION_ENTER();
6493 ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD;
6494 TCC_CRITICAL_SECTION_LEAVE();
6495 }
6496
hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void * const hw)6497 static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw)
6498 {
6499 TCC_CRITICAL_SECTION_ENTER();
6500 ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD;
6501 TCC_CRITICAL_SECTION_LEAVE();
6502 }
6503
hri_tcc_set_DBGCTRL_reg(const void * const hw,hri_tcc_dbgctrl_reg_t mask)6504 static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
6505 {
6506 TCC_CRITICAL_SECTION_ENTER();
6507 ((Tcc *)hw)->DBGCTRL.reg |= mask;
6508 TCC_CRITICAL_SECTION_LEAVE();
6509 }
6510
hri_tcc_get_DBGCTRL_reg(const void * const hw,hri_tcc_dbgctrl_reg_t mask)6511 static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
6512 {
6513 uint8_t tmp;
6514 tmp = ((Tcc *)hw)->DBGCTRL.reg;
6515 tmp &= mask;
6516 return tmp;
6517 }
6518
hri_tcc_write_DBGCTRL_reg(const void * const hw,hri_tcc_dbgctrl_reg_t data)6519 static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data)
6520 {
6521 TCC_CRITICAL_SECTION_ENTER();
6522 ((Tcc *)hw)->DBGCTRL.reg = data;
6523 TCC_CRITICAL_SECTION_LEAVE();
6524 }
6525
hri_tcc_clear_DBGCTRL_reg(const void * const hw,hri_tcc_dbgctrl_reg_t mask)6526 static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
6527 {
6528 TCC_CRITICAL_SECTION_ENTER();
6529 ((Tcc *)hw)->DBGCTRL.reg &= ~mask;
6530 TCC_CRITICAL_SECTION_LEAVE();
6531 }
6532
hri_tcc_toggle_DBGCTRL_reg(const void * const hw,hri_tcc_dbgctrl_reg_t mask)6533 static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask)
6534 {
6535 TCC_CRITICAL_SECTION_ENTER();
6536 ((Tcc *)hw)->DBGCTRL.reg ^= mask;
6537 TCC_CRITICAL_SECTION_LEAVE();
6538 }
6539
hri_tcc_read_DBGCTRL_reg(const void * const hw)6540 static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw)
6541 {
6542 return ((Tcc *)hw)->DBGCTRL.reg;
6543 }
6544
hri_tcc_set_EVCTRL_OVFEO_bit(const void * const hw)6545 static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw)
6546 {
6547 TCC_CRITICAL_SECTION_ENTER();
6548 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO;
6549 TCC_CRITICAL_SECTION_LEAVE();
6550 }
6551
hri_tcc_get_EVCTRL_OVFEO_bit(const void * const hw)6552 static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw)
6553 {
6554 uint32_t tmp;
6555 tmp = ((Tcc *)hw)->EVCTRL.reg;
6556 tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos;
6557 return (bool)tmp;
6558 }
6559
hri_tcc_write_EVCTRL_OVFEO_bit(const void * const hw,bool value)6560 static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value)
6561 {
6562 uint32_t tmp;
6563 TCC_CRITICAL_SECTION_ENTER();
6564 tmp = ((Tcc *)hw)->EVCTRL.reg;
6565 tmp &= ~TCC_EVCTRL_OVFEO;
6566 tmp |= value << TCC_EVCTRL_OVFEO_Pos;
6567 ((Tcc *)hw)->EVCTRL.reg = tmp;
6568 TCC_CRITICAL_SECTION_LEAVE();
6569 }
6570
hri_tcc_clear_EVCTRL_OVFEO_bit(const void * const hw)6571 static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw)
6572 {
6573 TCC_CRITICAL_SECTION_ENTER();
6574 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO;
6575 TCC_CRITICAL_SECTION_LEAVE();
6576 }
6577
hri_tcc_toggle_EVCTRL_OVFEO_bit(const void * const hw)6578 static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw)
6579 {
6580 TCC_CRITICAL_SECTION_ENTER();
6581 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO;
6582 TCC_CRITICAL_SECTION_LEAVE();
6583 }
6584
hri_tcc_set_EVCTRL_TRGEO_bit(const void * const hw)6585 static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw)
6586 {
6587 TCC_CRITICAL_SECTION_ENTER();
6588 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO;
6589 TCC_CRITICAL_SECTION_LEAVE();
6590 }
6591
hri_tcc_get_EVCTRL_TRGEO_bit(const void * const hw)6592 static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw)
6593 {
6594 uint32_t tmp;
6595 tmp = ((Tcc *)hw)->EVCTRL.reg;
6596 tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos;
6597 return (bool)tmp;
6598 }
6599
hri_tcc_write_EVCTRL_TRGEO_bit(const void * const hw,bool value)6600 static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value)
6601 {
6602 uint32_t tmp;
6603 TCC_CRITICAL_SECTION_ENTER();
6604 tmp = ((Tcc *)hw)->EVCTRL.reg;
6605 tmp &= ~TCC_EVCTRL_TRGEO;
6606 tmp |= value << TCC_EVCTRL_TRGEO_Pos;
6607 ((Tcc *)hw)->EVCTRL.reg = tmp;
6608 TCC_CRITICAL_SECTION_LEAVE();
6609 }
6610
hri_tcc_clear_EVCTRL_TRGEO_bit(const void * const hw)6611 static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw)
6612 {
6613 TCC_CRITICAL_SECTION_ENTER();
6614 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO;
6615 TCC_CRITICAL_SECTION_LEAVE();
6616 }
6617
hri_tcc_toggle_EVCTRL_TRGEO_bit(const void * const hw)6618 static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw)
6619 {
6620 TCC_CRITICAL_SECTION_ENTER();
6621 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO;
6622 TCC_CRITICAL_SECTION_LEAVE();
6623 }
6624
hri_tcc_set_EVCTRL_CNTEO_bit(const void * const hw)6625 static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw)
6626 {
6627 TCC_CRITICAL_SECTION_ENTER();
6628 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO;
6629 TCC_CRITICAL_SECTION_LEAVE();
6630 }
6631
hri_tcc_get_EVCTRL_CNTEO_bit(const void * const hw)6632 static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw)
6633 {
6634 uint32_t tmp;
6635 tmp = ((Tcc *)hw)->EVCTRL.reg;
6636 tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos;
6637 return (bool)tmp;
6638 }
6639
hri_tcc_write_EVCTRL_CNTEO_bit(const void * const hw,bool value)6640 static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value)
6641 {
6642 uint32_t tmp;
6643 TCC_CRITICAL_SECTION_ENTER();
6644 tmp = ((Tcc *)hw)->EVCTRL.reg;
6645 tmp &= ~TCC_EVCTRL_CNTEO;
6646 tmp |= value << TCC_EVCTRL_CNTEO_Pos;
6647 ((Tcc *)hw)->EVCTRL.reg = tmp;
6648 TCC_CRITICAL_SECTION_LEAVE();
6649 }
6650
hri_tcc_clear_EVCTRL_CNTEO_bit(const void * const hw)6651 static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw)
6652 {
6653 TCC_CRITICAL_SECTION_ENTER();
6654 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO;
6655 TCC_CRITICAL_SECTION_LEAVE();
6656 }
6657
hri_tcc_toggle_EVCTRL_CNTEO_bit(const void * const hw)6658 static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw)
6659 {
6660 TCC_CRITICAL_SECTION_ENTER();
6661 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO;
6662 TCC_CRITICAL_SECTION_LEAVE();
6663 }
6664
hri_tcc_set_EVCTRL_TCINV0_bit(const void * const hw)6665 static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw)
6666 {
6667 TCC_CRITICAL_SECTION_ENTER();
6668 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0;
6669 TCC_CRITICAL_SECTION_LEAVE();
6670 }
6671
hri_tcc_get_EVCTRL_TCINV0_bit(const void * const hw)6672 static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw)
6673 {
6674 uint32_t tmp;
6675 tmp = ((Tcc *)hw)->EVCTRL.reg;
6676 tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos;
6677 return (bool)tmp;
6678 }
6679
hri_tcc_write_EVCTRL_TCINV0_bit(const void * const hw,bool value)6680 static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value)
6681 {
6682 uint32_t tmp;
6683 TCC_CRITICAL_SECTION_ENTER();
6684 tmp = ((Tcc *)hw)->EVCTRL.reg;
6685 tmp &= ~TCC_EVCTRL_TCINV0;
6686 tmp |= value << TCC_EVCTRL_TCINV0_Pos;
6687 ((Tcc *)hw)->EVCTRL.reg = tmp;
6688 TCC_CRITICAL_SECTION_LEAVE();
6689 }
6690
hri_tcc_clear_EVCTRL_TCINV0_bit(const void * const hw)6691 static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw)
6692 {
6693 TCC_CRITICAL_SECTION_ENTER();
6694 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0;
6695 TCC_CRITICAL_SECTION_LEAVE();
6696 }
6697
hri_tcc_toggle_EVCTRL_TCINV0_bit(const void * const hw)6698 static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw)
6699 {
6700 TCC_CRITICAL_SECTION_ENTER();
6701 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0;
6702 TCC_CRITICAL_SECTION_LEAVE();
6703 }
6704
hri_tcc_set_EVCTRL_TCINV1_bit(const void * const hw)6705 static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw)
6706 {
6707 TCC_CRITICAL_SECTION_ENTER();
6708 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1;
6709 TCC_CRITICAL_SECTION_LEAVE();
6710 }
6711
hri_tcc_get_EVCTRL_TCINV1_bit(const void * const hw)6712 static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw)
6713 {
6714 uint32_t tmp;
6715 tmp = ((Tcc *)hw)->EVCTRL.reg;
6716 tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos;
6717 return (bool)tmp;
6718 }
6719
hri_tcc_write_EVCTRL_TCINV1_bit(const void * const hw,bool value)6720 static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value)
6721 {
6722 uint32_t tmp;
6723 TCC_CRITICAL_SECTION_ENTER();
6724 tmp = ((Tcc *)hw)->EVCTRL.reg;
6725 tmp &= ~TCC_EVCTRL_TCINV1;
6726 tmp |= value << TCC_EVCTRL_TCINV1_Pos;
6727 ((Tcc *)hw)->EVCTRL.reg = tmp;
6728 TCC_CRITICAL_SECTION_LEAVE();
6729 }
6730
hri_tcc_clear_EVCTRL_TCINV1_bit(const void * const hw)6731 static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw)
6732 {
6733 TCC_CRITICAL_SECTION_ENTER();
6734 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1;
6735 TCC_CRITICAL_SECTION_LEAVE();
6736 }
6737
hri_tcc_toggle_EVCTRL_TCINV1_bit(const void * const hw)6738 static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw)
6739 {
6740 TCC_CRITICAL_SECTION_ENTER();
6741 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1;
6742 TCC_CRITICAL_SECTION_LEAVE();
6743 }
6744
hri_tcc_set_EVCTRL_TCEI0_bit(const void * const hw)6745 static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw)
6746 {
6747 TCC_CRITICAL_SECTION_ENTER();
6748 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0;
6749 TCC_CRITICAL_SECTION_LEAVE();
6750 }
6751
hri_tcc_get_EVCTRL_TCEI0_bit(const void * const hw)6752 static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw)
6753 {
6754 uint32_t tmp;
6755 tmp = ((Tcc *)hw)->EVCTRL.reg;
6756 tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos;
6757 return (bool)tmp;
6758 }
6759
hri_tcc_write_EVCTRL_TCEI0_bit(const void * const hw,bool value)6760 static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value)
6761 {
6762 uint32_t tmp;
6763 TCC_CRITICAL_SECTION_ENTER();
6764 tmp = ((Tcc *)hw)->EVCTRL.reg;
6765 tmp &= ~TCC_EVCTRL_TCEI0;
6766 tmp |= value << TCC_EVCTRL_TCEI0_Pos;
6767 ((Tcc *)hw)->EVCTRL.reg = tmp;
6768 TCC_CRITICAL_SECTION_LEAVE();
6769 }
6770
hri_tcc_clear_EVCTRL_TCEI0_bit(const void * const hw)6771 static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw)
6772 {
6773 TCC_CRITICAL_SECTION_ENTER();
6774 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0;
6775 TCC_CRITICAL_SECTION_LEAVE();
6776 }
6777
hri_tcc_toggle_EVCTRL_TCEI0_bit(const void * const hw)6778 static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw)
6779 {
6780 TCC_CRITICAL_SECTION_ENTER();
6781 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0;
6782 TCC_CRITICAL_SECTION_LEAVE();
6783 }
6784
hri_tcc_set_EVCTRL_TCEI1_bit(const void * const hw)6785 static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw)
6786 {
6787 TCC_CRITICAL_SECTION_ENTER();
6788 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1;
6789 TCC_CRITICAL_SECTION_LEAVE();
6790 }
6791
hri_tcc_get_EVCTRL_TCEI1_bit(const void * const hw)6792 static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw)
6793 {
6794 uint32_t tmp;
6795 tmp = ((Tcc *)hw)->EVCTRL.reg;
6796 tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos;
6797 return (bool)tmp;
6798 }
6799
hri_tcc_write_EVCTRL_TCEI1_bit(const void * const hw,bool value)6800 static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value)
6801 {
6802 uint32_t tmp;
6803 TCC_CRITICAL_SECTION_ENTER();
6804 tmp = ((Tcc *)hw)->EVCTRL.reg;
6805 tmp &= ~TCC_EVCTRL_TCEI1;
6806 tmp |= value << TCC_EVCTRL_TCEI1_Pos;
6807 ((Tcc *)hw)->EVCTRL.reg = tmp;
6808 TCC_CRITICAL_SECTION_LEAVE();
6809 }
6810
hri_tcc_clear_EVCTRL_TCEI1_bit(const void * const hw)6811 static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw)
6812 {
6813 TCC_CRITICAL_SECTION_ENTER();
6814 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1;
6815 TCC_CRITICAL_SECTION_LEAVE();
6816 }
6817
hri_tcc_toggle_EVCTRL_TCEI1_bit(const void * const hw)6818 static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw)
6819 {
6820 TCC_CRITICAL_SECTION_ENTER();
6821 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1;
6822 TCC_CRITICAL_SECTION_LEAVE();
6823 }
6824
hri_tcc_set_EVCTRL_MCEI0_bit(const void * const hw)6825 static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw)
6826 {
6827 TCC_CRITICAL_SECTION_ENTER();
6828 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0;
6829 TCC_CRITICAL_SECTION_LEAVE();
6830 }
6831
hri_tcc_get_EVCTRL_MCEI0_bit(const void * const hw)6832 static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw)
6833 {
6834 uint32_t tmp;
6835 tmp = ((Tcc *)hw)->EVCTRL.reg;
6836 tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos;
6837 return (bool)tmp;
6838 }
6839
hri_tcc_write_EVCTRL_MCEI0_bit(const void * const hw,bool value)6840 static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value)
6841 {
6842 uint32_t tmp;
6843 TCC_CRITICAL_SECTION_ENTER();
6844 tmp = ((Tcc *)hw)->EVCTRL.reg;
6845 tmp &= ~TCC_EVCTRL_MCEI0;
6846 tmp |= value << TCC_EVCTRL_MCEI0_Pos;
6847 ((Tcc *)hw)->EVCTRL.reg = tmp;
6848 TCC_CRITICAL_SECTION_LEAVE();
6849 }
6850
hri_tcc_clear_EVCTRL_MCEI0_bit(const void * const hw)6851 static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw)
6852 {
6853 TCC_CRITICAL_SECTION_ENTER();
6854 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0;
6855 TCC_CRITICAL_SECTION_LEAVE();
6856 }
6857
hri_tcc_toggle_EVCTRL_MCEI0_bit(const void * const hw)6858 static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw)
6859 {
6860 TCC_CRITICAL_SECTION_ENTER();
6861 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0;
6862 TCC_CRITICAL_SECTION_LEAVE();
6863 }
6864
hri_tcc_set_EVCTRL_MCEI1_bit(const void * const hw)6865 static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw)
6866 {
6867 TCC_CRITICAL_SECTION_ENTER();
6868 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1;
6869 TCC_CRITICAL_SECTION_LEAVE();
6870 }
6871
hri_tcc_get_EVCTRL_MCEI1_bit(const void * const hw)6872 static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw)
6873 {
6874 uint32_t tmp;
6875 tmp = ((Tcc *)hw)->EVCTRL.reg;
6876 tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos;
6877 return (bool)tmp;
6878 }
6879
hri_tcc_write_EVCTRL_MCEI1_bit(const void * const hw,bool value)6880 static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value)
6881 {
6882 uint32_t tmp;
6883 TCC_CRITICAL_SECTION_ENTER();
6884 tmp = ((Tcc *)hw)->EVCTRL.reg;
6885 tmp &= ~TCC_EVCTRL_MCEI1;
6886 tmp |= value << TCC_EVCTRL_MCEI1_Pos;
6887 ((Tcc *)hw)->EVCTRL.reg = tmp;
6888 TCC_CRITICAL_SECTION_LEAVE();
6889 }
6890
hri_tcc_clear_EVCTRL_MCEI1_bit(const void * const hw)6891 static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw)
6892 {
6893 TCC_CRITICAL_SECTION_ENTER();
6894 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1;
6895 TCC_CRITICAL_SECTION_LEAVE();
6896 }
6897
hri_tcc_toggle_EVCTRL_MCEI1_bit(const void * const hw)6898 static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw)
6899 {
6900 TCC_CRITICAL_SECTION_ENTER();
6901 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1;
6902 TCC_CRITICAL_SECTION_LEAVE();
6903 }
6904
hri_tcc_set_EVCTRL_MCEI2_bit(const void * const hw)6905 static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw)
6906 {
6907 TCC_CRITICAL_SECTION_ENTER();
6908 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2;
6909 TCC_CRITICAL_SECTION_LEAVE();
6910 }
6911
hri_tcc_get_EVCTRL_MCEI2_bit(const void * const hw)6912 static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw)
6913 {
6914 uint32_t tmp;
6915 tmp = ((Tcc *)hw)->EVCTRL.reg;
6916 tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos;
6917 return (bool)tmp;
6918 }
6919
hri_tcc_write_EVCTRL_MCEI2_bit(const void * const hw,bool value)6920 static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value)
6921 {
6922 uint32_t tmp;
6923 TCC_CRITICAL_SECTION_ENTER();
6924 tmp = ((Tcc *)hw)->EVCTRL.reg;
6925 tmp &= ~TCC_EVCTRL_MCEI2;
6926 tmp |= value << TCC_EVCTRL_MCEI2_Pos;
6927 ((Tcc *)hw)->EVCTRL.reg = tmp;
6928 TCC_CRITICAL_SECTION_LEAVE();
6929 }
6930
hri_tcc_clear_EVCTRL_MCEI2_bit(const void * const hw)6931 static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw)
6932 {
6933 TCC_CRITICAL_SECTION_ENTER();
6934 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2;
6935 TCC_CRITICAL_SECTION_LEAVE();
6936 }
6937
hri_tcc_toggle_EVCTRL_MCEI2_bit(const void * const hw)6938 static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw)
6939 {
6940 TCC_CRITICAL_SECTION_ENTER();
6941 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2;
6942 TCC_CRITICAL_SECTION_LEAVE();
6943 }
6944
hri_tcc_set_EVCTRL_MCEI3_bit(const void * const hw)6945 static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw)
6946 {
6947 TCC_CRITICAL_SECTION_ENTER();
6948 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3;
6949 TCC_CRITICAL_SECTION_LEAVE();
6950 }
6951
hri_tcc_get_EVCTRL_MCEI3_bit(const void * const hw)6952 static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw)
6953 {
6954 uint32_t tmp;
6955 tmp = ((Tcc *)hw)->EVCTRL.reg;
6956 tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos;
6957 return (bool)tmp;
6958 }
6959
hri_tcc_write_EVCTRL_MCEI3_bit(const void * const hw,bool value)6960 static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value)
6961 {
6962 uint32_t tmp;
6963 TCC_CRITICAL_SECTION_ENTER();
6964 tmp = ((Tcc *)hw)->EVCTRL.reg;
6965 tmp &= ~TCC_EVCTRL_MCEI3;
6966 tmp |= value << TCC_EVCTRL_MCEI3_Pos;
6967 ((Tcc *)hw)->EVCTRL.reg = tmp;
6968 TCC_CRITICAL_SECTION_LEAVE();
6969 }
6970
hri_tcc_clear_EVCTRL_MCEI3_bit(const void * const hw)6971 static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw)
6972 {
6973 TCC_CRITICAL_SECTION_ENTER();
6974 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3;
6975 TCC_CRITICAL_SECTION_LEAVE();
6976 }
6977
hri_tcc_toggle_EVCTRL_MCEI3_bit(const void * const hw)6978 static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw)
6979 {
6980 TCC_CRITICAL_SECTION_ENTER();
6981 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3;
6982 TCC_CRITICAL_SECTION_LEAVE();
6983 }
6984
hri_tcc_set_EVCTRL_MCEO0_bit(const void * const hw)6985 static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw)
6986 {
6987 TCC_CRITICAL_SECTION_ENTER();
6988 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0;
6989 TCC_CRITICAL_SECTION_LEAVE();
6990 }
6991
hri_tcc_get_EVCTRL_MCEO0_bit(const void * const hw)6992 static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw)
6993 {
6994 uint32_t tmp;
6995 tmp = ((Tcc *)hw)->EVCTRL.reg;
6996 tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos;
6997 return (bool)tmp;
6998 }
6999
hri_tcc_write_EVCTRL_MCEO0_bit(const void * const hw,bool value)7000 static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value)
7001 {
7002 uint32_t tmp;
7003 TCC_CRITICAL_SECTION_ENTER();
7004 tmp = ((Tcc *)hw)->EVCTRL.reg;
7005 tmp &= ~TCC_EVCTRL_MCEO0;
7006 tmp |= value << TCC_EVCTRL_MCEO0_Pos;
7007 ((Tcc *)hw)->EVCTRL.reg = tmp;
7008 TCC_CRITICAL_SECTION_LEAVE();
7009 }
7010
hri_tcc_clear_EVCTRL_MCEO0_bit(const void * const hw)7011 static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw)
7012 {
7013 TCC_CRITICAL_SECTION_ENTER();
7014 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0;
7015 TCC_CRITICAL_SECTION_LEAVE();
7016 }
7017
hri_tcc_toggle_EVCTRL_MCEO0_bit(const void * const hw)7018 static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw)
7019 {
7020 TCC_CRITICAL_SECTION_ENTER();
7021 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0;
7022 TCC_CRITICAL_SECTION_LEAVE();
7023 }
7024
hri_tcc_set_EVCTRL_MCEO1_bit(const void * const hw)7025 static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw)
7026 {
7027 TCC_CRITICAL_SECTION_ENTER();
7028 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1;
7029 TCC_CRITICAL_SECTION_LEAVE();
7030 }
7031
hri_tcc_get_EVCTRL_MCEO1_bit(const void * const hw)7032 static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw)
7033 {
7034 uint32_t tmp;
7035 tmp = ((Tcc *)hw)->EVCTRL.reg;
7036 tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos;
7037 return (bool)tmp;
7038 }
7039
hri_tcc_write_EVCTRL_MCEO1_bit(const void * const hw,bool value)7040 static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value)
7041 {
7042 uint32_t tmp;
7043 TCC_CRITICAL_SECTION_ENTER();
7044 tmp = ((Tcc *)hw)->EVCTRL.reg;
7045 tmp &= ~TCC_EVCTRL_MCEO1;
7046 tmp |= value << TCC_EVCTRL_MCEO1_Pos;
7047 ((Tcc *)hw)->EVCTRL.reg = tmp;
7048 TCC_CRITICAL_SECTION_LEAVE();
7049 }
7050
hri_tcc_clear_EVCTRL_MCEO1_bit(const void * const hw)7051 static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw)
7052 {
7053 TCC_CRITICAL_SECTION_ENTER();
7054 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1;
7055 TCC_CRITICAL_SECTION_LEAVE();
7056 }
7057
hri_tcc_toggle_EVCTRL_MCEO1_bit(const void * const hw)7058 static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw)
7059 {
7060 TCC_CRITICAL_SECTION_ENTER();
7061 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1;
7062 TCC_CRITICAL_SECTION_LEAVE();
7063 }
7064
hri_tcc_set_EVCTRL_MCEO2_bit(const void * const hw)7065 static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw)
7066 {
7067 TCC_CRITICAL_SECTION_ENTER();
7068 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2;
7069 TCC_CRITICAL_SECTION_LEAVE();
7070 }
7071
hri_tcc_get_EVCTRL_MCEO2_bit(const void * const hw)7072 static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw)
7073 {
7074 uint32_t tmp;
7075 tmp = ((Tcc *)hw)->EVCTRL.reg;
7076 tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos;
7077 return (bool)tmp;
7078 }
7079
hri_tcc_write_EVCTRL_MCEO2_bit(const void * const hw,bool value)7080 static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value)
7081 {
7082 uint32_t tmp;
7083 TCC_CRITICAL_SECTION_ENTER();
7084 tmp = ((Tcc *)hw)->EVCTRL.reg;
7085 tmp &= ~TCC_EVCTRL_MCEO2;
7086 tmp |= value << TCC_EVCTRL_MCEO2_Pos;
7087 ((Tcc *)hw)->EVCTRL.reg = tmp;
7088 TCC_CRITICAL_SECTION_LEAVE();
7089 }
7090
hri_tcc_clear_EVCTRL_MCEO2_bit(const void * const hw)7091 static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw)
7092 {
7093 TCC_CRITICAL_SECTION_ENTER();
7094 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2;
7095 TCC_CRITICAL_SECTION_LEAVE();
7096 }
7097
hri_tcc_toggle_EVCTRL_MCEO2_bit(const void * const hw)7098 static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw)
7099 {
7100 TCC_CRITICAL_SECTION_ENTER();
7101 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2;
7102 TCC_CRITICAL_SECTION_LEAVE();
7103 }
7104
hri_tcc_set_EVCTRL_MCEO3_bit(const void * const hw)7105 static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw)
7106 {
7107 TCC_CRITICAL_SECTION_ENTER();
7108 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3;
7109 TCC_CRITICAL_SECTION_LEAVE();
7110 }
7111
hri_tcc_get_EVCTRL_MCEO3_bit(const void * const hw)7112 static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw)
7113 {
7114 uint32_t tmp;
7115 tmp = ((Tcc *)hw)->EVCTRL.reg;
7116 tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos;
7117 return (bool)tmp;
7118 }
7119
hri_tcc_write_EVCTRL_MCEO3_bit(const void * const hw,bool value)7120 static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value)
7121 {
7122 uint32_t tmp;
7123 TCC_CRITICAL_SECTION_ENTER();
7124 tmp = ((Tcc *)hw)->EVCTRL.reg;
7125 tmp &= ~TCC_EVCTRL_MCEO3;
7126 tmp |= value << TCC_EVCTRL_MCEO3_Pos;
7127 ((Tcc *)hw)->EVCTRL.reg = tmp;
7128 TCC_CRITICAL_SECTION_LEAVE();
7129 }
7130
hri_tcc_clear_EVCTRL_MCEO3_bit(const void * const hw)7131 static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw)
7132 {
7133 TCC_CRITICAL_SECTION_ENTER();
7134 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3;
7135 TCC_CRITICAL_SECTION_LEAVE();
7136 }
7137
hri_tcc_toggle_EVCTRL_MCEO3_bit(const void * const hw)7138 static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw)
7139 {
7140 TCC_CRITICAL_SECTION_ENTER();
7141 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3;
7142 TCC_CRITICAL_SECTION_LEAVE();
7143 }
7144
hri_tcc_set_EVCTRL_EVACT0_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7145 static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7146 {
7147 TCC_CRITICAL_SECTION_ENTER();
7148 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask);
7149 TCC_CRITICAL_SECTION_LEAVE();
7150 }
7151
hri_tcc_get_EVCTRL_EVACT0_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7152 static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7153 {
7154 uint32_t tmp;
7155 tmp = ((Tcc *)hw)->EVCTRL.reg;
7156 tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos;
7157 return tmp;
7158 }
7159
hri_tcc_write_EVCTRL_EVACT0_bf(const void * const hw,hri_tcc_evctrl_reg_t data)7160 static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
7161 {
7162 uint32_t tmp;
7163 TCC_CRITICAL_SECTION_ENTER();
7164 tmp = ((Tcc *)hw)->EVCTRL.reg;
7165 tmp &= ~TCC_EVCTRL_EVACT0_Msk;
7166 tmp |= TCC_EVCTRL_EVACT0(data);
7167 ((Tcc *)hw)->EVCTRL.reg = tmp;
7168 TCC_CRITICAL_SECTION_LEAVE();
7169 }
7170
hri_tcc_clear_EVCTRL_EVACT0_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7171 static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7172 {
7173 TCC_CRITICAL_SECTION_ENTER();
7174 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask);
7175 TCC_CRITICAL_SECTION_LEAVE();
7176 }
7177
hri_tcc_toggle_EVCTRL_EVACT0_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7178 static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7179 {
7180 TCC_CRITICAL_SECTION_ENTER();
7181 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask);
7182 TCC_CRITICAL_SECTION_LEAVE();
7183 }
7184
hri_tcc_read_EVCTRL_EVACT0_bf(const void * const hw)7185 static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw)
7186 {
7187 uint32_t tmp;
7188 tmp = ((Tcc *)hw)->EVCTRL.reg;
7189 tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos;
7190 return tmp;
7191 }
7192
hri_tcc_set_EVCTRL_EVACT1_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7193 static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7194 {
7195 TCC_CRITICAL_SECTION_ENTER();
7196 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask);
7197 TCC_CRITICAL_SECTION_LEAVE();
7198 }
7199
hri_tcc_get_EVCTRL_EVACT1_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7200 static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7201 {
7202 uint32_t tmp;
7203 tmp = ((Tcc *)hw)->EVCTRL.reg;
7204 tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos;
7205 return tmp;
7206 }
7207
hri_tcc_write_EVCTRL_EVACT1_bf(const void * const hw,hri_tcc_evctrl_reg_t data)7208 static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
7209 {
7210 uint32_t tmp;
7211 TCC_CRITICAL_SECTION_ENTER();
7212 tmp = ((Tcc *)hw)->EVCTRL.reg;
7213 tmp &= ~TCC_EVCTRL_EVACT1_Msk;
7214 tmp |= TCC_EVCTRL_EVACT1(data);
7215 ((Tcc *)hw)->EVCTRL.reg = tmp;
7216 TCC_CRITICAL_SECTION_LEAVE();
7217 }
7218
hri_tcc_clear_EVCTRL_EVACT1_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7219 static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7220 {
7221 TCC_CRITICAL_SECTION_ENTER();
7222 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask);
7223 TCC_CRITICAL_SECTION_LEAVE();
7224 }
7225
hri_tcc_toggle_EVCTRL_EVACT1_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7226 static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7227 {
7228 TCC_CRITICAL_SECTION_ENTER();
7229 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask);
7230 TCC_CRITICAL_SECTION_LEAVE();
7231 }
7232
hri_tcc_read_EVCTRL_EVACT1_bf(const void * const hw)7233 static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw)
7234 {
7235 uint32_t tmp;
7236 tmp = ((Tcc *)hw)->EVCTRL.reg;
7237 tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos;
7238 return tmp;
7239 }
7240
hri_tcc_set_EVCTRL_CNTSEL_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7241 static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7242 {
7243 TCC_CRITICAL_SECTION_ENTER();
7244 ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask);
7245 TCC_CRITICAL_SECTION_LEAVE();
7246 }
7247
hri_tcc_get_EVCTRL_CNTSEL_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7248 static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7249 {
7250 uint32_t tmp;
7251 tmp = ((Tcc *)hw)->EVCTRL.reg;
7252 tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos;
7253 return tmp;
7254 }
7255
hri_tcc_write_EVCTRL_CNTSEL_bf(const void * const hw,hri_tcc_evctrl_reg_t data)7256 static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data)
7257 {
7258 uint32_t tmp;
7259 TCC_CRITICAL_SECTION_ENTER();
7260 tmp = ((Tcc *)hw)->EVCTRL.reg;
7261 tmp &= ~TCC_EVCTRL_CNTSEL_Msk;
7262 tmp |= TCC_EVCTRL_CNTSEL(data);
7263 ((Tcc *)hw)->EVCTRL.reg = tmp;
7264 TCC_CRITICAL_SECTION_LEAVE();
7265 }
7266
hri_tcc_clear_EVCTRL_CNTSEL_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7267 static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7268 {
7269 TCC_CRITICAL_SECTION_ENTER();
7270 ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask);
7271 TCC_CRITICAL_SECTION_LEAVE();
7272 }
7273
hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void * const hw,hri_tcc_evctrl_reg_t mask)7274 static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask)
7275 {
7276 TCC_CRITICAL_SECTION_ENTER();
7277 ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask);
7278 TCC_CRITICAL_SECTION_LEAVE();
7279 }
7280
hri_tcc_read_EVCTRL_CNTSEL_bf(const void * const hw)7281 static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw)
7282 {
7283 uint32_t tmp;
7284 tmp = ((Tcc *)hw)->EVCTRL.reg;
7285 tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos;
7286 return tmp;
7287 }
7288
hri_tcc_set_EVCTRL_reg(const void * const hw,hri_tcc_evctrl_reg_t mask)7289 static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
7290 {
7291 TCC_CRITICAL_SECTION_ENTER();
7292 ((Tcc *)hw)->EVCTRL.reg |= mask;
7293 TCC_CRITICAL_SECTION_LEAVE();
7294 }
7295
hri_tcc_get_EVCTRL_reg(const void * const hw,hri_tcc_evctrl_reg_t mask)7296 static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
7297 {
7298 uint32_t tmp;
7299 tmp = ((Tcc *)hw)->EVCTRL.reg;
7300 tmp &= mask;
7301 return tmp;
7302 }
7303
hri_tcc_write_EVCTRL_reg(const void * const hw,hri_tcc_evctrl_reg_t data)7304 static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data)
7305 {
7306 TCC_CRITICAL_SECTION_ENTER();
7307 ((Tcc *)hw)->EVCTRL.reg = data;
7308 TCC_CRITICAL_SECTION_LEAVE();
7309 }
7310
hri_tcc_clear_EVCTRL_reg(const void * const hw,hri_tcc_evctrl_reg_t mask)7311 static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
7312 {
7313 TCC_CRITICAL_SECTION_ENTER();
7314 ((Tcc *)hw)->EVCTRL.reg &= ~mask;
7315 TCC_CRITICAL_SECTION_LEAVE();
7316 }
7317
hri_tcc_toggle_EVCTRL_reg(const void * const hw,hri_tcc_evctrl_reg_t mask)7318 static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask)
7319 {
7320 TCC_CRITICAL_SECTION_ENTER();
7321 ((Tcc *)hw)->EVCTRL.reg ^= mask;
7322 TCC_CRITICAL_SECTION_LEAVE();
7323 }
7324
hri_tcc_read_EVCTRL_reg(const void * const hw)7325 static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw)
7326 {
7327 return ((Tcc *)hw)->EVCTRL.reg;
7328 }
7329
hri_tcc_set_PATT_PGE0_bit(const void * const hw)7330 static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw)
7331 {
7332 TCC_CRITICAL_SECTION_ENTER();
7333 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7334 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0;
7335 TCC_CRITICAL_SECTION_LEAVE();
7336 }
7337
hri_tcc_get_PATT_PGE0_bit(const void * const hw)7338 static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw)
7339 {
7340 uint16_t tmp;
7341 tmp = ((Tcc *)hw)->PATT.reg;
7342 tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos;
7343 return (bool)tmp;
7344 }
7345
hri_tcc_write_PATT_PGE0_bit(const void * const hw,bool value)7346 static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value)
7347 {
7348 uint16_t tmp;
7349 TCC_CRITICAL_SECTION_ENTER();
7350 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7351 tmp = ((Tcc *)hw)->PATT.reg;
7352 tmp &= ~TCC_PATT_PGE0;
7353 tmp |= value << TCC_PATT_PGE0_Pos;
7354 ((Tcc *)hw)->PATT.reg = tmp;
7355 TCC_CRITICAL_SECTION_LEAVE();
7356 }
7357
hri_tcc_clear_PATT_PGE0_bit(const void * const hw)7358 static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw)
7359 {
7360 TCC_CRITICAL_SECTION_ENTER();
7361 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7362 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0;
7363 TCC_CRITICAL_SECTION_LEAVE();
7364 }
7365
hri_tcc_toggle_PATT_PGE0_bit(const void * const hw)7366 static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw)
7367 {
7368 TCC_CRITICAL_SECTION_ENTER();
7369 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7370 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0;
7371 TCC_CRITICAL_SECTION_LEAVE();
7372 }
7373
hri_tcc_set_PATT_PGE1_bit(const void * const hw)7374 static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw)
7375 {
7376 TCC_CRITICAL_SECTION_ENTER();
7377 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7378 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1;
7379 TCC_CRITICAL_SECTION_LEAVE();
7380 }
7381
hri_tcc_get_PATT_PGE1_bit(const void * const hw)7382 static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw)
7383 {
7384 uint16_t tmp;
7385 tmp = ((Tcc *)hw)->PATT.reg;
7386 tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos;
7387 return (bool)tmp;
7388 }
7389
hri_tcc_write_PATT_PGE1_bit(const void * const hw,bool value)7390 static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value)
7391 {
7392 uint16_t tmp;
7393 TCC_CRITICAL_SECTION_ENTER();
7394 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7395 tmp = ((Tcc *)hw)->PATT.reg;
7396 tmp &= ~TCC_PATT_PGE1;
7397 tmp |= value << TCC_PATT_PGE1_Pos;
7398 ((Tcc *)hw)->PATT.reg = tmp;
7399 TCC_CRITICAL_SECTION_LEAVE();
7400 }
7401
hri_tcc_clear_PATT_PGE1_bit(const void * const hw)7402 static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw)
7403 {
7404 TCC_CRITICAL_SECTION_ENTER();
7405 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7406 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1;
7407 TCC_CRITICAL_SECTION_LEAVE();
7408 }
7409
hri_tcc_toggle_PATT_PGE1_bit(const void * const hw)7410 static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw)
7411 {
7412 TCC_CRITICAL_SECTION_ENTER();
7413 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7414 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1;
7415 TCC_CRITICAL_SECTION_LEAVE();
7416 }
7417
hri_tcc_set_PATT_PGE2_bit(const void * const hw)7418 static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw)
7419 {
7420 TCC_CRITICAL_SECTION_ENTER();
7421 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7422 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2;
7423 TCC_CRITICAL_SECTION_LEAVE();
7424 }
7425
hri_tcc_get_PATT_PGE2_bit(const void * const hw)7426 static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw)
7427 {
7428 uint16_t tmp;
7429 tmp = ((Tcc *)hw)->PATT.reg;
7430 tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos;
7431 return (bool)tmp;
7432 }
7433
hri_tcc_write_PATT_PGE2_bit(const void * const hw,bool value)7434 static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value)
7435 {
7436 uint16_t tmp;
7437 TCC_CRITICAL_SECTION_ENTER();
7438 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7439 tmp = ((Tcc *)hw)->PATT.reg;
7440 tmp &= ~TCC_PATT_PGE2;
7441 tmp |= value << TCC_PATT_PGE2_Pos;
7442 ((Tcc *)hw)->PATT.reg = tmp;
7443 TCC_CRITICAL_SECTION_LEAVE();
7444 }
7445
hri_tcc_clear_PATT_PGE2_bit(const void * const hw)7446 static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw)
7447 {
7448 TCC_CRITICAL_SECTION_ENTER();
7449 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7450 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2;
7451 TCC_CRITICAL_SECTION_LEAVE();
7452 }
7453
hri_tcc_toggle_PATT_PGE2_bit(const void * const hw)7454 static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw)
7455 {
7456 TCC_CRITICAL_SECTION_ENTER();
7457 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7458 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2;
7459 TCC_CRITICAL_SECTION_LEAVE();
7460 }
7461
hri_tcc_set_PATT_PGE3_bit(const void * const hw)7462 static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw)
7463 {
7464 TCC_CRITICAL_SECTION_ENTER();
7465 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7466 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3;
7467 TCC_CRITICAL_SECTION_LEAVE();
7468 }
7469
hri_tcc_get_PATT_PGE3_bit(const void * const hw)7470 static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw)
7471 {
7472 uint16_t tmp;
7473 tmp = ((Tcc *)hw)->PATT.reg;
7474 tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos;
7475 return (bool)tmp;
7476 }
7477
hri_tcc_write_PATT_PGE3_bit(const void * const hw,bool value)7478 static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value)
7479 {
7480 uint16_t tmp;
7481 TCC_CRITICAL_SECTION_ENTER();
7482 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7483 tmp = ((Tcc *)hw)->PATT.reg;
7484 tmp &= ~TCC_PATT_PGE3;
7485 tmp |= value << TCC_PATT_PGE3_Pos;
7486 ((Tcc *)hw)->PATT.reg = tmp;
7487 TCC_CRITICAL_SECTION_LEAVE();
7488 }
7489
hri_tcc_clear_PATT_PGE3_bit(const void * const hw)7490 static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw)
7491 {
7492 TCC_CRITICAL_SECTION_ENTER();
7493 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7494 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3;
7495 TCC_CRITICAL_SECTION_LEAVE();
7496 }
7497
hri_tcc_toggle_PATT_PGE3_bit(const void * const hw)7498 static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw)
7499 {
7500 TCC_CRITICAL_SECTION_ENTER();
7501 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7502 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3;
7503 TCC_CRITICAL_SECTION_LEAVE();
7504 }
7505
hri_tcc_set_PATT_PGE4_bit(const void * const hw)7506 static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw)
7507 {
7508 TCC_CRITICAL_SECTION_ENTER();
7509 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7510 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4;
7511 TCC_CRITICAL_SECTION_LEAVE();
7512 }
7513
hri_tcc_get_PATT_PGE4_bit(const void * const hw)7514 static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw)
7515 {
7516 uint16_t tmp;
7517 tmp = ((Tcc *)hw)->PATT.reg;
7518 tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos;
7519 return (bool)tmp;
7520 }
7521
hri_tcc_write_PATT_PGE4_bit(const void * const hw,bool value)7522 static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value)
7523 {
7524 uint16_t tmp;
7525 TCC_CRITICAL_SECTION_ENTER();
7526 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7527 tmp = ((Tcc *)hw)->PATT.reg;
7528 tmp &= ~TCC_PATT_PGE4;
7529 tmp |= value << TCC_PATT_PGE4_Pos;
7530 ((Tcc *)hw)->PATT.reg = tmp;
7531 TCC_CRITICAL_SECTION_LEAVE();
7532 }
7533
hri_tcc_clear_PATT_PGE4_bit(const void * const hw)7534 static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw)
7535 {
7536 TCC_CRITICAL_SECTION_ENTER();
7537 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7538 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4;
7539 TCC_CRITICAL_SECTION_LEAVE();
7540 }
7541
hri_tcc_toggle_PATT_PGE4_bit(const void * const hw)7542 static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw)
7543 {
7544 TCC_CRITICAL_SECTION_ENTER();
7545 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7546 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4;
7547 TCC_CRITICAL_SECTION_LEAVE();
7548 }
7549
hri_tcc_set_PATT_PGE5_bit(const void * const hw)7550 static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw)
7551 {
7552 TCC_CRITICAL_SECTION_ENTER();
7553 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7554 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5;
7555 TCC_CRITICAL_SECTION_LEAVE();
7556 }
7557
hri_tcc_get_PATT_PGE5_bit(const void * const hw)7558 static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw)
7559 {
7560 uint16_t tmp;
7561 tmp = ((Tcc *)hw)->PATT.reg;
7562 tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos;
7563 return (bool)tmp;
7564 }
7565
hri_tcc_write_PATT_PGE5_bit(const void * const hw,bool value)7566 static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value)
7567 {
7568 uint16_t tmp;
7569 TCC_CRITICAL_SECTION_ENTER();
7570 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7571 tmp = ((Tcc *)hw)->PATT.reg;
7572 tmp &= ~TCC_PATT_PGE5;
7573 tmp |= value << TCC_PATT_PGE5_Pos;
7574 ((Tcc *)hw)->PATT.reg = tmp;
7575 TCC_CRITICAL_SECTION_LEAVE();
7576 }
7577
hri_tcc_clear_PATT_PGE5_bit(const void * const hw)7578 static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw)
7579 {
7580 TCC_CRITICAL_SECTION_ENTER();
7581 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7582 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5;
7583 TCC_CRITICAL_SECTION_LEAVE();
7584 }
7585
hri_tcc_toggle_PATT_PGE5_bit(const void * const hw)7586 static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw)
7587 {
7588 TCC_CRITICAL_SECTION_ENTER();
7589 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7590 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5;
7591 TCC_CRITICAL_SECTION_LEAVE();
7592 }
7593
hri_tcc_set_PATT_PGE6_bit(const void * const hw)7594 static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw)
7595 {
7596 TCC_CRITICAL_SECTION_ENTER();
7597 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7598 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6;
7599 TCC_CRITICAL_SECTION_LEAVE();
7600 }
7601
hri_tcc_get_PATT_PGE6_bit(const void * const hw)7602 static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw)
7603 {
7604 uint16_t tmp;
7605 tmp = ((Tcc *)hw)->PATT.reg;
7606 tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos;
7607 return (bool)tmp;
7608 }
7609
hri_tcc_write_PATT_PGE6_bit(const void * const hw,bool value)7610 static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value)
7611 {
7612 uint16_t tmp;
7613 TCC_CRITICAL_SECTION_ENTER();
7614 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7615 tmp = ((Tcc *)hw)->PATT.reg;
7616 tmp &= ~TCC_PATT_PGE6;
7617 tmp |= value << TCC_PATT_PGE6_Pos;
7618 ((Tcc *)hw)->PATT.reg = tmp;
7619 TCC_CRITICAL_SECTION_LEAVE();
7620 }
7621
hri_tcc_clear_PATT_PGE6_bit(const void * const hw)7622 static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw)
7623 {
7624 TCC_CRITICAL_SECTION_ENTER();
7625 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7626 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6;
7627 TCC_CRITICAL_SECTION_LEAVE();
7628 }
7629
hri_tcc_toggle_PATT_PGE6_bit(const void * const hw)7630 static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw)
7631 {
7632 TCC_CRITICAL_SECTION_ENTER();
7633 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7634 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6;
7635 TCC_CRITICAL_SECTION_LEAVE();
7636 }
7637
hri_tcc_set_PATT_PGE7_bit(const void * const hw)7638 static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw)
7639 {
7640 TCC_CRITICAL_SECTION_ENTER();
7641 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7642 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7;
7643 TCC_CRITICAL_SECTION_LEAVE();
7644 }
7645
hri_tcc_get_PATT_PGE7_bit(const void * const hw)7646 static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw)
7647 {
7648 uint16_t tmp;
7649 tmp = ((Tcc *)hw)->PATT.reg;
7650 tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos;
7651 return (bool)tmp;
7652 }
7653
hri_tcc_write_PATT_PGE7_bit(const void * const hw,bool value)7654 static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value)
7655 {
7656 uint16_t tmp;
7657 TCC_CRITICAL_SECTION_ENTER();
7658 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7659 tmp = ((Tcc *)hw)->PATT.reg;
7660 tmp &= ~TCC_PATT_PGE7;
7661 tmp |= value << TCC_PATT_PGE7_Pos;
7662 ((Tcc *)hw)->PATT.reg = tmp;
7663 TCC_CRITICAL_SECTION_LEAVE();
7664 }
7665
hri_tcc_clear_PATT_PGE7_bit(const void * const hw)7666 static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw)
7667 {
7668 TCC_CRITICAL_SECTION_ENTER();
7669 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7670 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7;
7671 TCC_CRITICAL_SECTION_LEAVE();
7672 }
7673
hri_tcc_toggle_PATT_PGE7_bit(const void * const hw)7674 static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw)
7675 {
7676 TCC_CRITICAL_SECTION_ENTER();
7677 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7678 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7;
7679 TCC_CRITICAL_SECTION_LEAVE();
7680 }
7681
hri_tcc_set_PATT_PGV0_bit(const void * const hw)7682 static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw)
7683 {
7684 TCC_CRITICAL_SECTION_ENTER();
7685 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7686 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0;
7687 TCC_CRITICAL_SECTION_LEAVE();
7688 }
7689
hri_tcc_get_PATT_PGV0_bit(const void * const hw)7690 static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw)
7691 {
7692 uint16_t tmp;
7693 tmp = ((Tcc *)hw)->PATT.reg;
7694 tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos;
7695 return (bool)tmp;
7696 }
7697
hri_tcc_write_PATT_PGV0_bit(const void * const hw,bool value)7698 static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value)
7699 {
7700 uint16_t tmp;
7701 TCC_CRITICAL_SECTION_ENTER();
7702 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7703 tmp = ((Tcc *)hw)->PATT.reg;
7704 tmp &= ~TCC_PATT_PGV0;
7705 tmp |= value << TCC_PATT_PGV0_Pos;
7706 ((Tcc *)hw)->PATT.reg = tmp;
7707 TCC_CRITICAL_SECTION_LEAVE();
7708 }
7709
hri_tcc_clear_PATT_PGV0_bit(const void * const hw)7710 static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw)
7711 {
7712 TCC_CRITICAL_SECTION_ENTER();
7713 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7714 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0;
7715 TCC_CRITICAL_SECTION_LEAVE();
7716 }
7717
hri_tcc_toggle_PATT_PGV0_bit(const void * const hw)7718 static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw)
7719 {
7720 TCC_CRITICAL_SECTION_ENTER();
7721 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7722 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0;
7723 TCC_CRITICAL_SECTION_LEAVE();
7724 }
7725
hri_tcc_set_PATT_PGV1_bit(const void * const hw)7726 static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw)
7727 {
7728 TCC_CRITICAL_SECTION_ENTER();
7729 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7730 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1;
7731 TCC_CRITICAL_SECTION_LEAVE();
7732 }
7733
hri_tcc_get_PATT_PGV1_bit(const void * const hw)7734 static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw)
7735 {
7736 uint16_t tmp;
7737 tmp = ((Tcc *)hw)->PATT.reg;
7738 tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos;
7739 return (bool)tmp;
7740 }
7741
hri_tcc_write_PATT_PGV1_bit(const void * const hw,bool value)7742 static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value)
7743 {
7744 uint16_t tmp;
7745 TCC_CRITICAL_SECTION_ENTER();
7746 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7747 tmp = ((Tcc *)hw)->PATT.reg;
7748 tmp &= ~TCC_PATT_PGV1;
7749 tmp |= value << TCC_PATT_PGV1_Pos;
7750 ((Tcc *)hw)->PATT.reg = tmp;
7751 TCC_CRITICAL_SECTION_LEAVE();
7752 }
7753
hri_tcc_clear_PATT_PGV1_bit(const void * const hw)7754 static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw)
7755 {
7756 TCC_CRITICAL_SECTION_ENTER();
7757 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7758 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1;
7759 TCC_CRITICAL_SECTION_LEAVE();
7760 }
7761
hri_tcc_toggle_PATT_PGV1_bit(const void * const hw)7762 static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw)
7763 {
7764 TCC_CRITICAL_SECTION_ENTER();
7765 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7766 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1;
7767 TCC_CRITICAL_SECTION_LEAVE();
7768 }
7769
hri_tcc_set_PATT_PGV2_bit(const void * const hw)7770 static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw)
7771 {
7772 TCC_CRITICAL_SECTION_ENTER();
7773 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7774 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2;
7775 TCC_CRITICAL_SECTION_LEAVE();
7776 }
7777
hri_tcc_get_PATT_PGV2_bit(const void * const hw)7778 static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw)
7779 {
7780 uint16_t tmp;
7781 tmp = ((Tcc *)hw)->PATT.reg;
7782 tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos;
7783 return (bool)tmp;
7784 }
7785
hri_tcc_write_PATT_PGV2_bit(const void * const hw,bool value)7786 static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value)
7787 {
7788 uint16_t tmp;
7789 TCC_CRITICAL_SECTION_ENTER();
7790 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7791 tmp = ((Tcc *)hw)->PATT.reg;
7792 tmp &= ~TCC_PATT_PGV2;
7793 tmp |= value << TCC_PATT_PGV2_Pos;
7794 ((Tcc *)hw)->PATT.reg = tmp;
7795 TCC_CRITICAL_SECTION_LEAVE();
7796 }
7797
hri_tcc_clear_PATT_PGV2_bit(const void * const hw)7798 static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw)
7799 {
7800 TCC_CRITICAL_SECTION_ENTER();
7801 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7802 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2;
7803 TCC_CRITICAL_SECTION_LEAVE();
7804 }
7805
hri_tcc_toggle_PATT_PGV2_bit(const void * const hw)7806 static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw)
7807 {
7808 TCC_CRITICAL_SECTION_ENTER();
7809 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7810 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2;
7811 TCC_CRITICAL_SECTION_LEAVE();
7812 }
7813
hri_tcc_set_PATT_PGV3_bit(const void * const hw)7814 static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw)
7815 {
7816 TCC_CRITICAL_SECTION_ENTER();
7817 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7818 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3;
7819 TCC_CRITICAL_SECTION_LEAVE();
7820 }
7821
hri_tcc_get_PATT_PGV3_bit(const void * const hw)7822 static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw)
7823 {
7824 uint16_t tmp;
7825 tmp = ((Tcc *)hw)->PATT.reg;
7826 tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos;
7827 return (bool)tmp;
7828 }
7829
hri_tcc_write_PATT_PGV3_bit(const void * const hw,bool value)7830 static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value)
7831 {
7832 uint16_t tmp;
7833 TCC_CRITICAL_SECTION_ENTER();
7834 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7835 tmp = ((Tcc *)hw)->PATT.reg;
7836 tmp &= ~TCC_PATT_PGV3;
7837 tmp |= value << TCC_PATT_PGV3_Pos;
7838 ((Tcc *)hw)->PATT.reg = tmp;
7839 TCC_CRITICAL_SECTION_LEAVE();
7840 }
7841
hri_tcc_clear_PATT_PGV3_bit(const void * const hw)7842 static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw)
7843 {
7844 TCC_CRITICAL_SECTION_ENTER();
7845 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7846 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3;
7847 TCC_CRITICAL_SECTION_LEAVE();
7848 }
7849
hri_tcc_toggle_PATT_PGV3_bit(const void * const hw)7850 static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw)
7851 {
7852 TCC_CRITICAL_SECTION_ENTER();
7853 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7854 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3;
7855 TCC_CRITICAL_SECTION_LEAVE();
7856 }
7857
hri_tcc_set_PATT_PGV4_bit(const void * const hw)7858 static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw)
7859 {
7860 TCC_CRITICAL_SECTION_ENTER();
7861 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7862 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4;
7863 TCC_CRITICAL_SECTION_LEAVE();
7864 }
7865
hri_tcc_get_PATT_PGV4_bit(const void * const hw)7866 static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw)
7867 {
7868 uint16_t tmp;
7869 tmp = ((Tcc *)hw)->PATT.reg;
7870 tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos;
7871 return (bool)tmp;
7872 }
7873
hri_tcc_write_PATT_PGV4_bit(const void * const hw,bool value)7874 static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value)
7875 {
7876 uint16_t tmp;
7877 TCC_CRITICAL_SECTION_ENTER();
7878 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7879 tmp = ((Tcc *)hw)->PATT.reg;
7880 tmp &= ~TCC_PATT_PGV4;
7881 tmp |= value << TCC_PATT_PGV4_Pos;
7882 ((Tcc *)hw)->PATT.reg = tmp;
7883 TCC_CRITICAL_SECTION_LEAVE();
7884 }
7885
hri_tcc_clear_PATT_PGV4_bit(const void * const hw)7886 static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw)
7887 {
7888 TCC_CRITICAL_SECTION_ENTER();
7889 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7890 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4;
7891 TCC_CRITICAL_SECTION_LEAVE();
7892 }
7893
hri_tcc_toggle_PATT_PGV4_bit(const void * const hw)7894 static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw)
7895 {
7896 TCC_CRITICAL_SECTION_ENTER();
7897 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7898 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4;
7899 TCC_CRITICAL_SECTION_LEAVE();
7900 }
7901
hri_tcc_set_PATT_PGV5_bit(const void * const hw)7902 static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw)
7903 {
7904 TCC_CRITICAL_SECTION_ENTER();
7905 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7906 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5;
7907 TCC_CRITICAL_SECTION_LEAVE();
7908 }
7909
hri_tcc_get_PATT_PGV5_bit(const void * const hw)7910 static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw)
7911 {
7912 uint16_t tmp;
7913 tmp = ((Tcc *)hw)->PATT.reg;
7914 tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos;
7915 return (bool)tmp;
7916 }
7917
hri_tcc_write_PATT_PGV5_bit(const void * const hw,bool value)7918 static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value)
7919 {
7920 uint16_t tmp;
7921 TCC_CRITICAL_SECTION_ENTER();
7922 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7923 tmp = ((Tcc *)hw)->PATT.reg;
7924 tmp &= ~TCC_PATT_PGV5;
7925 tmp |= value << TCC_PATT_PGV5_Pos;
7926 ((Tcc *)hw)->PATT.reg = tmp;
7927 TCC_CRITICAL_SECTION_LEAVE();
7928 }
7929
hri_tcc_clear_PATT_PGV5_bit(const void * const hw)7930 static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw)
7931 {
7932 TCC_CRITICAL_SECTION_ENTER();
7933 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7934 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5;
7935 TCC_CRITICAL_SECTION_LEAVE();
7936 }
7937
hri_tcc_toggle_PATT_PGV5_bit(const void * const hw)7938 static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw)
7939 {
7940 TCC_CRITICAL_SECTION_ENTER();
7941 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7942 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5;
7943 TCC_CRITICAL_SECTION_LEAVE();
7944 }
7945
hri_tcc_set_PATT_PGV6_bit(const void * const hw)7946 static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw)
7947 {
7948 TCC_CRITICAL_SECTION_ENTER();
7949 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7950 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6;
7951 TCC_CRITICAL_SECTION_LEAVE();
7952 }
7953
hri_tcc_get_PATT_PGV6_bit(const void * const hw)7954 static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw)
7955 {
7956 uint16_t tmp;
7957 tmp = ((Tcc *)hw)->PATT.reg;
7958 tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos;
7959 return (bool)tmp;
7960 }
7961
hri_tcc_write_PATT_PGV6_bit(const void * const hw,bool value)7962 static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value)
7963 {
7964 uint16_t tmp;
7965 TCC_CRITICAL_SECTION_ENTER();
7966 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7967 tmp = ((Tcc *)hw)->PATT.reg;
7968 tmp &= ~TCC_PATT_PGV6;
7969 tmp |= value << TCC_PATT_PGV6_Pos;
7970 ((Tcc *)hw)->PATT.reg = tmp;
7971 TCC_CRITICAL_SECTION_LEAVE();
7972 }
7973
hri_tcc_clear_PATT_PGV6_bit(const void * const hw)7974 static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw)
7975 {
7976 TCC_CRITICAL_SECTION_ENTER();
7977 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7978 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6;
7979 TCC_CRITICAL_SECTION_LEAVE();
7980 }
7981
hri_tcc_toggle_PATT_PGV6_bit(const void * const hw)7982 static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw)
7983 {
7984 TCC_CRITICAL_SECTION_ENTER();
7985 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7986 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6;
7987 TCC_CRITICAL_SECTION_LEAVE();
7988 }
7989
hri_tcc_set_PATT_PGV7_bit(const void * const hw)7990 static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw)
7991 {
7992 TCC_CRITICAL_SECTION_ENTER();
7993 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
7994 ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7;
7995 TCC_CRITICAL_SECTION_LEAVE();
7996 }
7997
hri_tcc_get_PATT_PGV7_bit(const void * const hw)7998 static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw)
7999 {
8000 uint16_t tmp;
8001 tmp = ((Tcc *)hw)->PATT.reg;
8002 tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos;
8003 return (bool)tmp;
8004 }
8005
hri_tcc_write_PATT_PGV7_bit(const void * const hw,bool value)8006 static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value)
8007 {
8008 uint16_t tmp;
8009 TCC_CRITICAL_SECTION_ENTER();
8010 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8011 tmp = ((Tcc *)hw)->PATT.reg;
8012 tmp &= ~TCC_PATT_PGV7;
8013 tmp |= value << TCC_PATT_PGV7_Pos;
8014 ((Tcc *)hw)->PATT.reg = tmp;
8015 TCC_CRITICAL_SECTION_LEAVE();
8016 }
8017
hri_tcc_clear_PATT_PGV7_bit(const void * const hw)8018 static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw)
8019 {
8020 TCC_CRITICAL_SECTION_ENTER();
8021 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8022 ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7;
8023 TCC_CRITICAL_SECTION_LEAVE();
8024 }
8025
hri_tcc_toggle_PATT_PGV7_bit(const void * const hw)8026 static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw)
8027 {
8028 TCC_CRITICAL_SECTION_ENTER();
8029 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8030 ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7;
8031 TCC_CRITICAL_SECTION_LEAVE();
8032 }
8033
hri_tcc_set_PATT_reg(const void * const hw,hri_tcc_patt_reg_t mask)8034 static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
8035 {
8036 TCC_CRITICAL_SECTION_ENTER();
8037 ((Tcc *)hw)->PATT.reg |= mask;
8038 TCC_CRITICAL_SECTION_LEAVE();
8039 }
8040
hri_tcc_get_PATT_reg(const void * const hw,hri_tcc_patt_reg_t mask)8041 static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
8042 {
8043 uint16_t tmp;
8044 tmp = ((Tcc *)hw)->PATT.reg;
8045 tmp &= mask;
8046 return tmp;
8047 }
8048
hri_tcc_write_PATT_reg(const void * const hw,hri_tcc_patt_reg_t data)8049 static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data)
8050 {
8051 TCC_CRITICAL_SECTION_ENTER();
8052 ((Tcc *)hw)->PATT.reg = data;
8053 TCC_CRITICAL_SECTION_LEAVE();
8054 }
8055
hri_tcc_clear_PATT_reg(const void * const hw,hri_tcc_patt_reg_t mask)8056 static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
8057 {
8058 TCC_CRITICAL_SECTION_ENTER();
8059 ((Tcc *)hw)->PATT.reg &= ~mask;
8060 TCC_CRITICAL_SECTION_LEAVE();
8061 }
8062
hri_tcc_toggle_PATT_reg(const void * const hw,hri_tcc_patt_reg_t mask)8063 static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask)
8064 {
8065 TCC_CRITICAL_SECTION_ENTER();
8066 ((Tcc *)hw)->PATT.reg ^= mask;
8067 TCC_CRITICAL_SECTION_LEAVE();
8068 }
8069
hri_tcc_read_PATT_reg(const void * const hw)8070 static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw)
8071 {
8072 return ((Tcc *)hw)->PATT.reg;
8073 }
8074
hri_tcc_set_WAVE_CIPEREN_bit(const void * const hw)8075 static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw)
8076 {
8077 TCC_CRITICAL_SECTION_ENTER();
8078 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8079 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN;
8080 TCC_CRITICAL_SECTION_LEAVE();
8081 }
8082
hri_tcc_get_WAVE_CIPEREN_bit(const void * const hw)8083 static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw)
8084 {
8085 uint32_t tmp;
8086 tmp = ((Tcc *)hw)->WAVE.reg;
8087 tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos;
8088 return (bool)tmp;
8089 }
8090
hri_tcc_write_WAVE_CIPEREN_bit(const void * const hw,bool value)8091 static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value)
8092 {
8093 uint32_t tmp;
8094 TCC_CRITICAL_SECTION_ENTER();
8095 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8096 tmp = ((Tcc *)hw)->WAVE.reg;
8097 tmp &= ~TCC_WAVE_CIPEREN;
8098 tmp |= value << TCC_WAVE_CIPEREN_Pos;
8099 ((Tcc *)hw)->WAVE.reg = tmp;
8100 TCC_CRITICAL_SECTION_LEAVE();
8101 }
8102
hri_tcc_clear_WAVE_CIPEREN_bit(const void * const hw)8103 static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw)
8104 {
8105 TCC_CRITICAL_SECTION_ENTER();
8106 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8107 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN;
8108 TCC_CRITICAL_SECTION_LEAVE();
8109 }
8110
hri_tcc_toggle_WAVE_CIPEREN_bit(const void * const hw)8111 static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw)
8112 {
8113 TCC_CRITICAL_SECTION_ENTER();
8114 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8115 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN;
8116 TCC_CRITICAL_SECTION_LEAVE();
8117 }
8118
hri_tcc_set_WAVE_CICCEN0_bit(const void * const hw)8119 static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw)
8120 {
8121 TCC_CRITICAL_SECTION_ENTER();
8122 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8123 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0;
8124 TCC_CRITICAL_SECTION_LEAVE();
8125 }
8126
hri_tcc_get_WAVE_CICCEN0_bit(const void * const hw)8127 static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw)
8128 {
8129 uint32_t tmp;
8130 tmp = ((Tcc *)hw)->WAVE.reg;
8131 tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos;
8132 return (bool)tmp;
8133 }
8134
hri_tcc_write_WAVE_CICCEN0_bit(const void * const hw,bool value)8135 static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value)
8136 {
8137 uint32_t tmp;
8138 TCC_CRITICAL_SECTION_ENTER();
8139 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8140 tmp = ((Tcc *)hw)->WAVE.reg;
8141 tmp &= ~TCC_WAVE_CICCEN0;
8142 tmp |= value << TCC_WAVE_CICCEN0_Pos;
8143 ((Tcc *)hw)->WAVE.reg = tmp;
8144 TCC_CRITICAL_SECTION_LEAVE();
8145 }
8146
hri_tcc_clear_WAVE_CICCEN0_bit(const void * const hw)8147 static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw)
8148 {
8149 TCC_CRITICAL_SECTION_ENTER();
8150 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8151 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0;
8152 TCC_CRITICAL_SECTION_LEAVE();
8153 }
8154
hri_tcc_toggle_WAVE_CICCEN0_bit(const void * const hw)8155 static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw)
8156 {
8157 TCC_CRITICAL_SECTION_ENTER();
8158 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8159 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0;
8160 TCC_CRITICAL_SECTION_LEAVE();
8161 }
8162
hri_tcc_set_WAVE_CICCEN1_bit(const void * const hw)8163 static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw)
8164 {
8165 TCC_CRITICAL_SECTION_ENTER();
8166 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8167 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1;
8168 TCC_CRITICAL_SECTION_LEAVE();
8169 }
8170
hri_tcc_get_WAVE_CICCEN1_bit(const void * const hw)8171 static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw)
8172 {
8173 uint32_t tmp;
8174 tmp = ((Tcc *)hw)->WAVE.reg;
8175 tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos;
8176 return (bool)tmp;
8177 }
8178
hri_tcc_write_WAVE_CICCEN1_bit(const void * const hw,bool value)8179 static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value)
8180 {
8181 uint32_t tmp;
8182 TCC_CRITICAL_SECTION_ENTER();
8183 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8184 tmp = ((Tcc *)hw)->WAVE.reg;
8185 tmp &= ~TCC_WAVE_CICCEN1;
8186 tmp |= value << TCC_WAVE_CICCEN1_Pos;
8187 ((Tcc *)hw)->WAVE.reg = tmp;
8188 TCC_CRITICAL_SECTION_LEAVE();
8189 }
8190
hri_tcc_clear_WAVE_CICCEN1_bit(const void * const hw)8191 static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw)
8192 {
8193 TCC_CRITICAL_SECTION_ENTER();
8194 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8195 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1;
8196 TCC_CRITICAL_SECTION_LEAVE();
8197 }
8198
hri_tcc_toggle_WAVE_CICCEN1_bit(const void * const hw)8199 static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw)
8200 {
8201 TCC_CRITICAL_SECTION_ENTER();
8202 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8203 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1;
8204 TCC_CRITICAL_SECTION_LEAVE();
8205 }
8206
hri_tcc_set_WAVE_CICCEN2_bit(const void * const hw)8207 static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw)
8208 {
8209 TCC_CRITICAL_SECTION_ENTER();
8210 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8211 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2;
8212 TCC_CRITICAL_SECTION_LEAVE();
8213 }
8214
hri_tcc_get_WAVE_CICCEN2_bit(const void * const hw)8215 static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw)
8216 {
8217 uint32_t tmp;
8218 tmp = ((Tcc *)hw)->WAVE.reg;
8219 tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos;
8220 return (bool)tmp;
8221 }
8222
hri_tcc_write_WAVE_CICCEN2_bit(const void * const hw,bool value)8223 static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value)
8224 {
8225 uint32_t tmp;
8226 TCC_CRITICAL_SECTION_ENTER();
8227 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8228 tmp = ((Tcc *)hw)->WAVE.reg;
8229 tmp &= ~TCC_WAVE_CICCEN2;
8230 tmp |= value << TCC_WAVE_CICCEN2_Pos;
8231 ((Tcc *)hw)->WAVE.reg = tmp;
8232 TCC_CRITICAL_SECTION_LEAVE();
8233 }
8234
hri_tcc_clear_WAVE_CICCEN2_bit(const void * const hw)8235 static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw)
8236 {
8237 TCC_CRITICAL_SECTION_ENTER();
8238 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8239 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2;
8240 TCC_CRITICAL_SECTION_LEAVE();
8241 }
8242
hri_tcc_toggle_WAVE_CICCEN2_bit(const void * const hw)8243 static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw)
8244 {
8245 TCC_CRITICAL_SECTION_ENTER();
8246 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8247 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2;
8248 TCC_CRITICAL_SECTION_LEAVE();
8249 }
8250
hri_tcc_set_WAVE_CICCEN3_bit(const void * const hw)8251 static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw)
8252 {
8253 TCC_CRITICAL_SECTION_ENTER();
8254 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8255 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3;
8256 TCC_CRITICAL_SECTION_LEAVE();
8257 }
8258
hri_tcc_get_WAVE_CICCEN3_bit(const void * const hw)8259 static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw)
8260 {
8261 uint32_t tmp;
8262 tmp = ((Tcc *)hw)->WAVE.reg;
8263 tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos;
8264 return (bool)tmp;
8265 }
8266
hri_tcc_write_WAVE_CICCEN3_bit(const void * const hw,bool value)8267 static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value)
8268 {
8269 uint32_t tmp;
8270 TCC_CRITICAL_SECTION_ENTER();
8271 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8272 tmp = ((Tcc *)hw)->WAVE.reg;
8273 tmp &= ~TCC_WAVE_CICCEN3;
8274 tmp |= value << TCC_WAVE_CICCEN3_Pos;
8275 ((Tcc *)hw)->WAVE.reg = tmp;
8276 TCC_CRITICAL_SECTION_LEAVE();
8277 }
8278
hri_tcc_clear_WAVE_CICCEN3_bit(const void * const hw)8279 static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw)
8280 {
8281 TCC_CRITICAL_SECTION_ENTER();
8282 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8283 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3;
8284 TCC_CRITICAL_SECTION_LEAVE();
8285 }
8286
hri_tcc_toggle_WAVE_CICCEN3_bit(const void * const hw)8287 static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw)
8288 {
8289 TCC_CRITICAL_SECTION_ENTER();
8290 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8291 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3;
8292 TCC_CRITICAL_SECTION_LEAVE();
8293 }
8294
hri_tcc_set_WAVE_POL0_bit(const void * const hw)8295 static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw)
8296 {
8297 TCC_CRITICAL_SECTION_ENTER();
8298 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8299 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0;
8300 TCC_CRITICAL_SECTION_LEAVE();
8301 }
8302
hri_tcc_get_WAVE_POL0_bit(const void * const hw)8303 static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw)
8304 {
8305 uint32_t tmp;
8306 tmp = ((Tcc *)hw)->WAVE.reg;
8307 tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos;
8308 return (bool)tmp;
8309 }
8310
hri_tcc_write_WAVE_POL0_bit(const void * const hw,bool value)8311 static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value)
8312 {
8313 uint32_t tmp;
8314 TCC_CRITICAL_SECTION_ENTER();
8315 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8316 tmp = ((Tcc *)hw)->WAVE.reg;
8317 tmp &= ~TCC_WAVE_POL0;
8318 tmp |= value << TCC_WAVE_POL0_Pos;
8319 ((Tcc *)hw)->WAVE.reg = tmp;
8320 TCC_CRITICAL_SECTION_LEAVE();
8321 }
8322
hri_tcc_clear_WAVE_POL0_bit(const void * const hw)8323 static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw)
8324 {
8325 TCC_CRITICAL_SECTION_ENTER();
8326 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8327 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0;
8328 TCC_CRITICAL_SECTION_LEAVE();
8329 }
8330
hri_tcc_toggle_WAVE_POL0_bit(const void * const hw)8331 static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw)
8332 {
8333 TCC_CRITICAL_SECTION_ENTER();
8334 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8335 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0;
8336 TCC_CRITICAL_SECTION_LEAVE();
8337 }
8338
hri_tcc_set_WAVE_POL1_bit(const void * const hw)8339 static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw)
8340 {
8341 TCC_CRITICAL_SECTION_ENTER();
8342 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8343 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1;
8344 TCC_CRITICAL_SECTION_LEAVE();
8345 }
8346
hri_tcc_get_WAVE_POL1_bit(const void * const hw)8347 static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw)
8348 {
8349 uint32_t tmp;
8350 tmp = ((Tcc *)hw)->WAVE.reg;
8351 tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos;
8352 return (bool)tmp;
8353 }
8354
hri_tcc_write_WAVE_POL1_bit(const void * const hw,bool value)8355 static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value)
8356 {
8357 uint32_t tmp;
8358 TCC_CRITICAL_SECTION_ENTER();
8359 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8360 tmp = ((Tcc *)hw)->WAVE.reg;
8361 tmp &= ~TCC_WAVE_POL1;
8362 tmp |= value << TCC_WAVE_POL1_Pos;
8363 ((Tcc *)hw)->WAVE.reg = tmp;
8364 TCC_CRITICAL_SECTION_LEAVE();
8365 }
8366
hri_tcc_clear_WAVE_POL1_bit(const void * const hw)8367 static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw)
8368 {
8369 TCC_CRITICAL_SECTION_ENTER();
8370 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8371 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1;
8372 TCC_CRITICAL_SECTION_LEAVE();
8373 }
8374
hri_tcc_toggle_WAVE_POL1_bit(const void * const hw)8375 static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw)
8376 {
8377 TCC_CRITICAL_SECTION_ENTER();
8378 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8379 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1;
8380 TCC_CRITICAL_SECTION_LEAVE();
8381 }
8382
hri_tcc_set_WAVE_POL2_bit(const void * const hw)8383 static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw)
8384 {
8385 TCC_CRITICAL_SECTION_ENTER();
8386 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8387 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2;
8388 TCC_CRITICAL_SECTION_LEAVE();
8389 }
8390
hri_tcc_get_WAVE_POL2_bit(const void * const hw)8391 static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw)
8392 {
8393 uint32_t tmp;
8394 tmp = ((Tcc *)hw)->WAVE.reg;
8395 tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos;
8396 return (bool)tmp;
8397 }
8398
hri_tcc_write_WAVE_POL2_bit(const void * const hw,bool value)8399 static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value)
8400 {
8401 uint32_t tmp;
8402 TCC_CRITICAL_SECTION_ENTER();
8403 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8404 tmp = ((Tcc *)hw)->WAVE.reg;
8405 tmp &= ~TCC_WAVE_POL2;
8406 tmp |= value << TCC_WAVE_POL2_Pos;
8407 ((Tcc *)hw)->WAVE.reg = tmp;
8408 TCC_CRITICAL_SECTION_LEAVE();
8409 }
8410
hri_tcc_clear_WAVE_POL2_bit(const void * const hw)8411 static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw)
8412 {
8413 TCC_CRITICAL_SECTION_ENTER();
8414 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8415 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2;
8416 TCC_CRITICAL_SECTION_LEAVE();
8417 }
8418
hri_tcc_toggle_WAVE_POL2_bit(const void * const hw)8419 static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw)
8420 {
8421 TCC_CRITICAL_SECTION_ENTER();
8422 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8423 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2;
8424 TCC_CRITICAL_SECTION_LEAVE();
8425 }
8426
hri_tcc_set_WAVE_POL3_bit(const void * const hw)8427 static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw)
8428 {
8429 TCC_CRITICAL_SECTION_ENTER();
8430 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8431 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3;
8432 TCC_CRITICAL_SECTION_LEAVE();
8433 }
8434
hri_tcc_get_WAVE_POL3_bit(const void * const hw)8435 static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw)
8436 {
8437 uint32_t tmp;
8438 tmp = ((Tcc *)hw)->WAVE.reg;
8439 tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos;
8440 return (bool)tmp;
8441 }
8442
hri_tcc_write_WAVE_POL3_bit(const void * const hw,bool value)8443 static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value)
8444 {
8445 uint32_t tmp;
8446 TCC_CRITICAL_SECTION_ENTER();
8447 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8448 tmp = ((Tcc *)hw)->WAVE.reg;
8449 tmp &= ~TCC_WAVE_POL3;
8450 tmp |= value << TCC_WAVE_POL3_Pos;
8451 ((Tcc *)hw)->WAVE.reg = tmp;
8452 TCC_CRITICAL_SECTION_LEAVE();
8453 }
8454
hri_tcc_clear_WAVE_POL3_bit(const void * const hw)8455 static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw)
8456 {
8457 TCC_CRITICAL_SECTION_ENTER();
8458 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8459 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3;
8460 TCC_CRITICAL_SECTION_LEAVE();
8461 }
8462
hri_tcc_toggle_WAVE_POL3_bit(const void * const hw)8463 static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw)
8464 {
8465 TCC_CRITICAL_SECTION_ENTER();
8466 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8467 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3;
8468 TCC_CRITICAL_SECTION_LEAVE();
8469 }
8470
hri_tcc_set_WAVE_SWAP0_bit(const void * const hw)8471 static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw)
8472 {
8473 TCC_CRITICAL_SECTION_ENTER();
8474 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8475 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0;
8476 TCC_CRITICAL_SECTION_LEAVE();
8477 }
8478
hri_tcc_get_WAVE_SWAP0_bit(const void * const hw)8479 static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw)
8480 {
8481 uint32_t tmp;
8482 tmp = ((Tcc *)hw)->WAVE.reg;
8483 tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos;
8484 return (bool)tmp;
8485 }
8486
hri_tcc_write_WAVE_SWAP0_bit(const void * const hw,bool value)8487 static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value)
8488 {
8489 uint32_t tmp;
8490 TCC_CRITICAL_SECTION_ENTER();
8491 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8492 tmp = ((Tcc *)hw)->WAVE.reg;
8493 tmp &= ~TCC_WAVE_SWAP0;
8494 tmp |= value << TCC_WAVE_SWAP0_Pos;
8495 ((Tcc *)hw)->WAVE.reg = tmp;
8496 TCC_CRITICAL_SECTION_LEAVE();
8497 }
8498
hri_tcc_clear_WAVE_SWAP0_bit(const void * const hw)8499 static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw)
8500 {
8501 TCC_CRITICAL_SECTION_ENTER();
8502 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8503 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0;
8504 TCC_CRITICAL_SECTION_LEAVE();
8505 }
8506
hri_tcc_toggle_WAVE_SWAP0_bit(const void * const hw)8507 static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw)
8508 {
8509 TCC_CRITICAL_SECTION_ENTER();
8510 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8511 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0;
8512 TCC_CRITICAL_SECTION_LEAVE();
8513 }
8514
hri_tcc_set_WAVE_SWAP1_bit(const void * const hw)8515 static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw)
8516 {
8517 TCC_CRITICAL_SECTION_ENTER();
8518 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8519 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1;
8520 TCC_CRITICAL_SECTION_LEAVE();
8521 }
8522
hri_tcc_get_WAVE_SWAP1_bit(const void * const hw)8523 static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw)
8524 {
8525 uint32_t tmp;
8526 tmp = ((Tcc *)hw)->WAVE.reg;
8527 tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos;
8528 return (bool)tmp;
8529 }
8530
hri_tcc_write_WAVE_SWAP1_bit(const void * const hw,bool value)8531 static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value)
8532 {
8533 uint32_t tmp;
8534 TCC_CRITICAL_SECTION_ENTER();
8535 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8536 tmp = ((Tcc *)hw)->WAVE.reg;
8537 tmp &= ~TCC_WAVE_SWAP1;
8538 tmp |= value << TCC_WAVE_SWAP1_Pos;
8539 ((Tcc *)hw)->WAVE.reg = tmp;
8540 TCC_CRITICAL_SECTION_LEAVE();
8541 }
8542
hri_tcc_clear_WAVE_SWAP1_bit(const void * const hw)8543 static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw)
8544 {
8545 TCC_CRITICAL_SECTION_ENTER();
8546 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8547 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1;
8548 TCC_CRITICAL_SECTION_LEAVE();
8549 }
8550
hri_tcc_toggle_WAVE_SWAP1_bit(const void * const hw)8551 static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw)
8552 {
8553 TCC_CRITICAL_SECTION_ENTER();
8554 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8555 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1;
8556 TCC_CRITICAL_SECTION_LEAVE();
8557 }
8558
hri_tcc_set_WAVE_SWAP2_bit(const void * const hw)8559 static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw)
8560 {
8561 TCC_CRITICAL_SECTION_ENTER();
8562 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8563 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2;
8564 TCC_CRITICAL_SECTION_LEAVE();
8565 }
8566
hri_tcc_get_WAVE_SWAP2_bit(const void * const hw)8567 static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw)
8568 {
8569 uint32_t tmp;
8570 tmp = ((Tcc *)hw)->WAVE.reg;
8571 tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos;
8572 return (bool)tmp;
8573 }
8574
hri_tcc_write_WAVE_SWAP2_bit(const void * const hw,bool value)8575 static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value)
8576 {
8577 uint32_t tmp;
8578 TCC_CRITICAL_SECTION_ENTER();
8579 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8580 tmp = ((Tcc *)hw)->WAVE.reg;
8581 tmp &= ~TCC_WAVE_SWAP2;
8582 tmp |= value << TCC_WAVE_SWAP2_Pos;
8583 ((Tcc *)hw)->WAVE.reg = tmp;
8584 TCC_CRITICAL_SECTION_LEAVE();
8585 }
8586
hri_tcc_clear_WAVE_SWAP2_bit(const void * const hw)8587 static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw)
8588 {
8589 TCC_CRITICAL_SECTION_ENTER();
8590 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8591 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2;
8592 TCC_CRITICAL_SECTION_LEAVE();
8593 }
8594
hri_tcc_toggle_WAVE_SWAP2_bit(const void * const hw)8595 static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw)
8596 {
8597 TCC_CRITICAL_SECTION_ENTER();
8598 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8599 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2;
8600 TCC_CRITICAL_SECTION_LEAVE();
8601 }
8602
hri_tcc_set_WAVE_SWAP3_bit(const void * const hw)8603 static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw)
8604 {
8605 TCC_CRITICAL_SECTION_ENTER();
8606 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8607 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3;
8608 TCC_CRITICAL_SECTION_LEAVE();
8609 }
8610
hri_tcc_get_WAVE_SWAP3_bit(const void * const hw)8611 static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw)
8612 {
8613 uint32_t tmp;
8614 tmp = ((Tcc *)hw)->WAVE.reg;
8615 tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos;
8616 return (bool)tmp;
8617 }
8618
hri_tcc_write_WAVE_SWAP3_bit(const void * const hw,bool value)8619 static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value)
8620 {
8621 uint32_t tmp;
8622 TCC_CRITICAL_SECTION_ENTER();
8623 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8624 tmp = ((Tcc *)hw)->WAVE.reg;
8625 tmp &= ~TCC_WAVE_SWAP3;
8626 tmp |= value << TCC_WAVE_SWAP3_Pos;
8627 ((Tcc *)hw)->WAVE.reg = tmp;
8628 TCC_CRITICAL_SECTION_LEAVE();
8629 }
8630
hri_tcc_clear_WAVE_SWAP3_bit(const void * const hw)8631 static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw)
8632 {
8633 TCC_CRITICAL_SECTION_ENTER();
8634 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8635 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3;
8636 TCC_CRITICAL_SECTION_LEAVE();
8637 }
8638
hri_tcc_toggle_WAVE_SWAP3_bit(const void * const hw)8639 static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw)
8640 {
8641 TCC_CRITICAL_SECTION_ENTER();
8642 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8643 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3;
8644 TCC_CRITICAL_SECTION_LEAVE();
8645 }
8646
hri_tcc_set_WAVE_WAVEGEN_bf(const void * const hw,hri_tcc_wave_reg_t mask)8647 static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
8648 {
8649 TCC_CRITICAL_SECTION_ENTER();
8650 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8651 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask);
8652 TCC_CRITICAL_SECTION_LEAVE();
8653 }
8654
hri_tcc_get_WAVE_WAVEGEN_bf(const void * const hw,hri_tcc_wave_reg_t mask)8655 static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
8656 {
8657 uint32_t tmp;
8658 tmp = ((Tcc *)hw)->WAVE.reg;
8659 tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos;
8660 return tmp;
8661 }
8662
hri_tcc_write_WAVE_WAVEGEN_bf(const void * const hw,hri_tcc_wave_reg_t data)8663 static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data)
8664 {
8665 uint32_t tmp;
8666 TCC_CRITICAL_SECTION_ENTER();
8667 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8668 tmp = ((Tcc *)hw)->WAVE.reg;
8669 tmp &= ~TCC_WAVE_WAVEGEN_Msk;
8670 tmp |= TCC_WAVE_WAVEGEN(data);
8671 ((Tcc *)hw)->WAVE.reg = tmp;
8672 TCC_CRITICAL_SECTION_LEAVE();
8673 }
8674
hri_tcc_clear_WAVE_WAVEGEN_bf(const void * const hw,hri_tcc_wave_reg_t mask)8675 static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
8676 {
8677 TCC_CRITICAL_SECTION_ENTER();
8678 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8679 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask);
8680 TCC_CRITICAL_SECTION_LEAVE();
8681 }
8682
hri_tcc_toggle_WAVE_WAVEGEN_bf(const void * const hw,hri_tcc_wave_reg_t mask)8683 static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask)
8684 {
8685 TCC_CRITICAL_SECTION_ENTER();
8686 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8687 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask);
8688 TCC_CRITICAL_SECTION_LEAVE();
8689 }
8690
hri_tcc_read_WAVE_WAVEGEN_bf(const void * const hw)8691 static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw)
8692 {
8693 uint32_t tmp;
8694 tmp = ((Tcc *)hw)->WAVE.reg;
8695 tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos;
8696 return tmp;
8697 }
8698
hri_tcc_set_WAVE_RAMP_bf(const void * const hw,hri_tcc_wave_reg_t mask)8699 static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
8700 {
8701 TCC_CRITICAL_SECTION_ENTER();
8702 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8703 ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask);
8704 TCC_CRITICAL_SECTION_LEAVE();
8705 }
8706
hri_tcc_get_WAVE_RAMP_bf(const void * const hw,hri_tcc_wave_reg_t mask)8707 static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
8708 {
8709 uint32_t tmp;
8710 tmp = ((Tcc *)hw)->WAVE.reg;
8711 tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos;
8712 return tmp;
8713 }
8714
hri_tcc_write_WAVE_RAMP_bf(const void * const hw,hri_tcc_wave_reg_t data)8715 static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data)
8716 {
8717 uint32_t tmp;
8718 TCC_CRITICAL_SECTION_ENTER();
8719 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8720 tmp = ((Tcc *)hw)->WAVE.reg;
8721 tmp &= ~TCC_WAVE_RAMP_Msk;
8722 tmp |= TCC_WAVE_RAMP(data);
8723 ((Tcc *)hw)->WAVE.reg = tmp;
8724 TCC_CRITICAL_SECTION_LEAVE();
8725 }
8726
hri_tcc_clear_WAVE_RAMP_bf(const void * const hw,hri_tcc_wave_reg_t mask)8727 static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
8728 {
8729 TCC_CRITICAL_SECTION_ENTER();
8730 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8731 ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask);
8732 TCC_CRITICAL_SECTION_LEAVE();
8733 }
8734
hri_tcc_toggle_WAVE_RAMP_bf(const void * const hw,hri_tcc_wave_reg_t mask)8735 static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask)
8736 {
8737 TCC_CRITICAL_SECTION_ENTER();
8738 hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK);
8739 ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask);
8740 TCC_CRITICAL_SECTION_LEAVE();
8741 }
8742
hri_tcc_read_WAVE_RAMP_bf(const void * const hw)8743 static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw)
8744 {
8745 uint32_t tmp;
8746 tmp = ((Tcc *)hw)->WAVE.reg;
8747 tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos;
8748 return tmp;
8749 }
8750
hri_tcc_set_WAVE_reg(const void * const hw,hri_tcc_wave_reg_t mask)8751 static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
8752 {
8753 TCC_CRITICAL_SECTION_ENTER();
8754 ((Tcc *)hw)->WAVE.reg |= mask;
8755 TCC_CRITICAL_SECTION_LEAVE();
8756 }
8757
hri_tcc_get_WAVE_reg(const void * const hw,hri_tcc_wave_reg_t mask)8758 static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
8759 {
8760 uint32_t tmp;
8761 tmp = ((Tcc *)hw)->WAVE.reg;
8762 tmp &= mask;
8763 return tmp;
8764 }
8765
hri_tcc_write_WAVE_reg(const void * const hw,hri_tcc_wave_reg_t data)8766 static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data)
8767 {
8768 TCC_CRITICAL_SECTION_ENTER();
8769 ((Tcc *)hw)->WAVE.reg = data;
8770 TCC_CRITICAL_SECTION_LEAVE();
8771 }
8772
hri_tcc_clear_WAVE_reg(const void * const hw,hri_tcc_wave_reg_t mask)8773 static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
8774 {
8775 TCC_CRITICAL_SECTION_ENTER();
8776 ((Tcc *)hw)->WAVE.reg &= ~mask;
8777 TCC_CRITICAL_SECTION_LEAVE();
8778 }
8779
hri_tcc_toggle_WAVE_reg(const void * const hw,hri_tcc_wave_reg_t mask)8780 static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask)
8781 {
8782 TCC_CRITICAL_SECTION_ENTER();
8783 ((Tcc *)hw)->WAVE.reg ^= mask;
8784 TCC_CRITICAL_SECTION_LEAVE();
8785 }
8786
hri_tcc_read_WAVE_reg(const void * const hw)8787 static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw)
8788 {
8789 return ((Tcc *)hw)->WAVE.reg;
8790 }
8791
hri_tcc_set_PATTBUF_PGEB0_bit(const void * const hw)8792 static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw)
8793 {
8794 TCC_CRITICAL_SECTION_ENTER();
8795 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0;
8796 TCC_CRITICAL_SECTION_LEAVE();
8797 }
8798
hri_tcc_get_PATTBUF_PGEB0_bit(const void * const hw)8799 static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw)
8800 {
8801 uint16_t tmp;
8802 tmp = ((Tcc *)hw)->PATTBUF.reg;
8803 tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos;
8804 return (bool)tmp;
8805 }
8806
hri_tcc_write_PATTBUF_PGEB0_bit(const void * const hw,bool value)8807 static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value)
8808 {
8809 uint16_t tmp;
8810 TCC_CRITICAL_SECTION_ENTER();
8811 tmp = ((Tcc *)hw)->PATTBUF.reg;
8812 tmp &= ~TCC_PATTBUF_PGEB0;
8813 tmp |= value << TCC_PATTBUF_PGEB0_Pos;
8814 ((Tcc *)hw)->PATTBUF.reg = tmp;
8815 TCC_CRITICAL_SECTION_LEAVE();
8816 }
8817
hri_tcc_clear_PATTBUF_PGEB0_bit(const void * const hw)8818 static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw)
8819 {
8820 TCC_CRITICAL_SECTION_ENTER();
8821 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0;
8822 TCC_CRITICAL_SECTION_LEAVE();
8823 }
8824
hri_tcc_toggle_PATTBUF_PGEB0_bit(const void * const hw)8825 static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw)
8826 {
8827 TCC_CRITICAL_SECTION_ENTER();
8828 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0;
8829 TCC_CRITICAL_SECTION_LEAVE();
8830 }
8831
hri_tcc_set_PATTBUF_PGEB1_bit(const void * const hw)8832 static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw)
8833 {
8834 TCC_CRITICAL_SECTION_ENTER();
8835 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1;
8836 TCC_CRITICAL_SECTION_LEAVE();
8837 }
8838
hri_tcc_get_PATTBUF_PGEB1_bit(const void * const hw)8839 static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw)
8840 {
8841 uint16_t tmp;
8842 tmp = ((Tcc *)hw)->PATTBUF.reg;
8843 tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos;
8844 return (bool)tmp;
8845 }
8846
hri_tcc_write_PATTBUF_PGEB1_bit(const void * const hw,bool value)8847 static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value)
8848 {
8849 uint16_t tmp;
8850 TCC_CRITICAL_SECTION_ENTER();
8851 tmp = ((Tcc *)hw)->PATTBUF.reg;
8852 tmp &= ~TCC_PATTBUF_PGEB1;
8853 tmp |= value << TCC_PATTBUF_PGEB1_Pos;
8854 ((Tcc *)hw)->PATTBUF.reg = tmp;
8855 TCC_CRITICAL_SECTION_LEAVE();
8856 }
8857
hri_tcc_clear_PATTBUF_PGEB1_bit(const void * const hw)8858 static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw)
8859 {
8860 TCC_CRITICAL_SECTION_ENTER();
8861 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1;
8862 TCC_CRITICAL_SECTION_LEAVE();
8863 }
8864
hri_tcc_toggle_PATTBUF_PGEB1_bit(const void * const hw)8865 static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw)
8866 {
8867 TCC_CRITICAL_SECTION_ENTER();
8868 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1;
8869 TCC_CRITICAL_SECTION_LEAVE();
8870 }
8871
hri_tcc_set_PATTBUF_PGEB2_bit(const void * const hw)8872 static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw)
8873 {
8874 TCC_CRITICAL_SECTION_ENTER();
8875 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2;
8876 TCC_CRITICAL_SECTION_LEAVE();
8877 }
8878
hri_tcc_get_PATTBUF_PGEB2_bit(const void * const hw)8879 static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw)
8880 {
8881 uint16_t tmp;
8882 tmp = ((Tcc *)hw)->PATTBUF.reg;
8883 tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos;
8884 return (bool)tmp;
8885 }
8886
hri_tcc_write_PATTBUF_PGEB2_bit(const void * const hw,bool value)8887 static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value)
8888 {
8889 uint16_t tmp;
8890 TCC_CRITICAL_SECTION_ENTER();
8891 tmp = ((Tcc *)hw)->PATTBUF.reg;
8892 tmp &= ~TCC_PATTBUF_PGEB2;
8893 tmp |= value << TCC_PATTBUF_PGEB2_Pos;
8894 ((Tcc *)hw)->PATTBUF.reg = tmp;
8895 TCC_CRITICAL_SECTION_LEAVE();
8896 }
8897
hri_tcc_clear_PATTBUF_PGEB2_bit(const void * const hw)8898 static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw)
8899 {
8900 TCC_CRITICAL_SECTION_ENTER();
8901 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2;
8902 TCC_CRITICAL_SECTION_LEAVE();
8903 }
8904
hri_tcc_toggle_PATTBUF_PGEB2_bit(const void * const hw)8905 static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw)
8906 {
8907 TCC_CRITICAL_SECTION_ENTER();
8908 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2;
8909 TCC_CRITICAL_SECTION_LEAVE();
8910 }
8911
hri_tcc_set_PATTBUF_PGEB3_bit(const void * const hw)8912 static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw)
8913 {
8914 TCC_CRITICAL_SECTION_ENTER();
8915 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3;
8916 TCC_CRITICAL_SECTION_LEAVE();
8917 }
8918
hri_tcc_get_PATTBUF_PGEB3_bit(const void * const hw)8919 static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw)
8920 {
8921 uint16_t tmp;
8922 tmp = ((Tcc *)hw)->PATTBUF.reg;
8923 tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos;
8924 return (bool)tmp;
8925 }
8926
hri_tcc_write_PATTBUF_PGEB3_bit(const void * const hw,bool value)8927 static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value)
8928 {
8929 uint16_t tmp;
8930 TCC_CRITICAL_SECTION_ENTER();
8931 tmp = ((Tcc *)hw)->PATTBUF.reg;
8932 tmp &= ~TCC_PATTBUF_PGEB3;
8933 tmp |= value << TCC_PATTBUF_PGEB3_Pos;
8934 ((Tcc *)hw)->PATTBUF.reg = tmp;
8935 TCC_CRITICAL_SECTION_LEAVE();
8936 }
8937
hri_tcc_clear_PATTBUF_PGEB3_bit(const void * const hw)8938 static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw)
8939 {
8940 TCC_CRITICAL_SECTION_ENTER();
8941 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3;
8942 TCC_CRITICAL_SECTION_LEAVE();
8943 }
8944
hri_tcc_toggle_PATTBUF_PGEB3_bit(const void * const hw)8945 static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw)
8946 {
8947 TCC_CRITICAL_SECTION_ENTER();
8948 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3;
8949 TCC_CRITICAL_SECTION_LEAVE();
8950 }
8951
hri_tcc_set_PATTBUF_PGEB4_bit(const void * const hw)8952 static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw)
8953 {
8954 TCC_CRITICAL_SECTION_ENTER();
8955 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4;
8956 TCC_CRITICAL_SECTION_LEAVE();
8957 }
8958
hri_tcc_get_PATTBUF_PGEB4_bit(const void * const hw)8959 static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw)
8960 {
8961 uint16_t tmp;
8962 tmp = ((Tcc *)hw)->PATTBUF.reg;
8963 tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos;
8964 return (bool)tmp;
8965 }
8966
hri_tcc_write_PATTBUF_PGEB4_bit(const void * const hw,bool value)8967 static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value)
8968 {
8969 uint16_t tmp;
8970 TCC_CRITICAL_SECTION_ENTER();
8971 tmp = ((Tcc *)hw)->PATTBUF.reg;
8972 tmp &= ~TCC_PATTBUF_PGEB4;
8973 tmp |= value << TCC_PATTBUF_PGEB4_Pos;
8974 ((Tcc *)hw)->PATTBUF.reg = tmp;
8975 TCC_CRITICAL_SECTION_LEAVE();
8976 }
8977
hri_tcc_clear_PATTBUF_PGEB4_bit(const void * const hw)8978 static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw)
8979 {
8980 TCC_CRITICAL_SECTION_ENTER();
8981 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4;
8982 TCC_CRITICAL_SECTION_LEAVE();
8983 }
8984
hri_tcc_toggle_PATTBUF_PGEB4_bit(const void * const hw)8985 static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw)
8986 {
8987 TCC_CRITICAL_SECTION_ENTER();
8988 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4;
8989 TCC_CRITICAL_SECTION_LEAVE();
8990 }
8991
hri_tcc_set_PATTBUF_PGEB5_bit(const void * const hw)8992 static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw)
8993 {
8994 TCC_CRITICAL_SECTION_ENTER();
8995 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5;
8996 TCC_CRITICAL_SECTION_LEAVE();
8997 }
8998
hri_tcc_get_PATTBUF_PGEB5_bit(const void * const hw)8999 static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw)
9000 {
9001 uint16_t tmp;
9002 tmp = ((Tcc *)hw)->PATTBUF.reg;
9003 tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos;
9004 return (bool)tmp;
9005 }
9006
hri_tcc_write_PATTBUF_PGEB5_bit(const void * const hw,bool value)9007 static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value)
9008 {
9009 uint16_t tmp;
9010 TCC_CRITICAL_SECTION_ENTER();
9011 tmp = ((Tcc *)hw)->PATTBUF.reg;
9012 tmp &= ~TCC_PATTBUF_PGEB5;
9013 tmp |= value << TCC_PATTBUF_PGEB5_Pos;
9014 ((Tcc *)hw)->PATTBUF.reg = tmp;
9015 TCC_CRITICAL_SECTION_LEAVE();
9016 }
9017
hri_tcc_clear_PATTBUF_PGEB5_bit(const void * const hw)9018 static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw)
9019 {
9020 TCC_CRITICAL_SECTION_ENTER();
9021 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5;
9022 TCC_CRITICAL_SECTION_LEAVE();
9023 }
9024
hri_tcc_toggle_PATTBUF_PGEB5_bit(const void * const hw)9025 static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw)
9026 {
9027 TCC_CRITICAL_SECTION_ENTER();
9028 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5;
9029 TCC_CRITICAL_SECTION_LEAVE();
9030 }
9031
hri_tcc_set_PATTBUF_PGEB6_bit(const void * const hw)9032 static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw)
9033 {
9034 TCC_CRITICAL_SECTION_ENTER();
9035 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6;
9036 TCC_CRITICAL_SECTION_LEAVE();
9037 }
9038
hri_tcc_get_PATTBUF_PGEB6_bit(const void * const hw)9039 static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw)
9040 {
9041 uint16_t tmp;
9042 tmp = ((Tcc *)hw)->PATTBUF.reg;
9043 tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos;
9044 return (bool)tmp;
9045 }
9046
hri_tcc_write_PATTBUF_PGEB6_bit(const void * const hw,bool value)9047 static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value)
9048 {
9049 uint16_t tmp;
9050 TCC_CRITICAL_SECTION_ENTER();
9051 tmp = ((Tcc *)hw)->PATTBUF.reg;
9052 tmp &= ~TCC_PATTBUF_PGEB6;
9053 tmp |= value << TCC_PATTBUF_PGEB6_Pos;
9054 ((Tcc *)hw)->PATTBUF.reg = tmp;
9055 TCC_CRITICAL_SECTION_LEAVE();
9056 }
9057
hri_tcc_clear_PATTBUF_PGEB6_bit(const void * const hw)9058 static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw)
9059 {
9060 TCC_CRITICAL_SECTION_ENTER();
9061 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6;
9062 TCC_CRITICAL_SECTION_LEAVE();
9063 }
9064
hri_tcc_toggle_PATTBUF_PGEB6_bit(const void * const hw)9065 static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw)
9066 {
9067 TCC_CRITICAL_SECTION_ENTER();
9068 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6;
9069 TCC_CRITICAL_SECTION_LEAVE();
9070 }
9071
hri_tcc_set_PATTBUF_PGEB7_bit(const void * const hw)9072 static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw)
9073 {
9074 TCC_CRITICAL_SECTION_ENTER();
9075 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7;
9076 TCC_CRITICAL_SECTION_LEAVE();
9077 }
9078
hri_tcc_get_PATTBUF_PGEB7_bit(const void * const hw)9079 static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw)
9080 {
9081 uint16_t tmp;
9082 tmp = ((Tcc *)hw)->PATTBUF.reg;
9083 tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos;
9084 return (bool)tmp;
9085 }
9086
hri_tcc_write_PATTBUF_PGEB7_bit(const void * const hw,bool value)9087 static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value)
9088 {
9089 uint16_t tmp;
9090 TCC_CRITICAL_SECTION_ENTER();
9091 tmp = ((Tcc *)hw)->PATTBUF.reg;
9092 tmp &= ~TCC_PATTBUF_PGEB7;
9093 tmp |= value << TCC_PATTBUF_PGEB7_Pos;
9094 ((Tcc *)hw)->PATTBUF.reg = tmp;
9095 TCC_CRITICAL_SECTION_LEAVE();
9096 }
9097
hri_tcc_clear_PATTBUF_PGEB7_bit(const void * const hw)9098 static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw)
9099 {
9100 TCC_CRITICAL_SECTION_ENTER();
9101 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7;
9102 TCC_CRITICAL_SECTION_LEAVE();
9103 }
9104
hri_tcc_toggle_PATTBUF_PGEB7_bit(const void * const hw)9105 static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw)
9106 {
9107 TCC_CRITICAL_SECTION_ENTER();
9108 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7;
9109 TCC_CRITICAL_SECTION_LEAVE();
9110 }
9111
hri_tcc_set_PATTBUF_PGVB0_bit(const void * const hw)9112 static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw)
9113 {
9114 TCC_CRITICAL_SECTION_ENTER();
9115 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0;
9116 TCC_CRITICAL_SECTION_LEAVE();
9117 }
9118
hri_tcc_get_PATTBUF_PGVB0_bit(const void * const hw)9119 static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw)
9120 {
9121 uint16_t tmp;
9122 tmp = ((Tcc *)hw)->PATTBUF.reg;
9123 tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos;
9124 return (bool)tmp;
9125 }
9126
hri_tcc_write_PATTBUF_PGVB0_bit(const void * const hw,bool value)9127 static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value)
9128 {
9129 uint16_t tmp;
9130 TCC_CRITICAL_SECTION_ENTER();
9131 tmp = ((Tcc *)hw)->PATTBUF.reg;
9132 tmp &= ~TCC_PATTBUF_PGVB0;
9133 tmp |= value << TCC_PATTBUF_PGVB0_Pos;
9134 ((Tcc *)hw)->PATTBUF.reg = tmp;
9135 TCC_CRITICAL_SECTION_LEAVE();
9136 }
9137
hri_tcc_clear_PATTBUF_PGVB0_bit(const void * const hw)9138 static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw)
9139 {
9140 TCC_CRITICAL_SECTION_ENTER();
9141 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0;
9142 TCC_CRITICAL_SECTION_LEAVE();
9143 }
9144
hri_tcc_toggle_PATTBUF_PGVB0_bit(const void * const hw)9145 static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw)
9146 {
9147 TCC_CRITICAL_SECTION_ENTER();
9148 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0;
9149 TCC_CRITICAL_SECTION_LEAVE();
9150 }
9151
hri_tcc_set_PATTBUF_PGVB1_bit(const void * const hw)9152 static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw)
9153 {
9154 TCC_CRITICAL_SECTION_ENTER();
9155 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1;
9156 TCC_CRITICAL_SECTION_LEAVE();
9157 }
9158
hri_tcc_get_PATTBUF_PGVB1_bit(const void * const hw)9159 static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw)
9160 {
9161 uint16_t tmp;
9162 tmp = ((Tcc *)hw)->PATTBUF.reg;
9163 tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos;
9164 return (bool)tmp;
9165 }
9166
hri_tcc_write_PATTBUF_PGVB1_bit(const void * const hw,bool value)9167 static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value)
9168 {
9169 uint16_t tmp;
9170 TCC_CRITICAL_SECTION_ENTER();
9171 tmp = ((Tcc *)hw)->PATTBUF.reg;
9172 tmp &= ~TCC_PATTBUF_PGVB1;
9173 tmp |= value << TCC_PATTBUF_PGVB1_Pos;
9174 ((Tcc *)hw)->PATTBUF.reg = tmp;
9175 TCC_CRITICAL_SECTION_LEAVE();
9176 }
9177
hri_tcc_clear_PATTBUF_PGVB1_bit(const void * const hw)9178 static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw)
9179 {
9180 TCC_CRITICAL_SECTION_ENTER();
9181 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1;
9182 TCC_CRITICAL_SECTION_LEAVE();
9183 }
9184
hri_tcc_toggle_PATTBUF_PGVB1_bit(const void * const hw)9185 static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw)
9186 {
9187 TCC_CRITICAL_SECTION_ENTER();
9188 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1;
9189 TCC_CRITICAL_SECTION_LEAVE();
9190 }
9191
hri_tcc_set_PATTBUF_PGVB2_bit(const void * const hw)9192 static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw)
9193 {
9194 TCC_CRITICAL_SECTION_ENTER();
9195 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2;
9196 TCC_CRITICAL_SECTION_LEAVE();
9197 }
9198
hri_tcc_get_PATTBUF_PGVB2_bit(const void * const hw)9199 static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw)
9200 {
9201 uint16_t tmp;
9202 tmp = ((Tcc *)hw)->PATTBUF.reg;
9203 tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos;
9204 return (bool)tmp;
9205 }
9206
hri_tcc_write_PATTBUF_PGVB2_bit(const void * const hw,bool value)9207 static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value)
9208 {
9209 uint16_t tmp;
9210 TCC_CRITICAL_SECTION_ENTER();
9211 tmp = ((Tcc *)hw)->PATTBUF.reg;
9212 tmp &= ~TCC_PATTBUF_PGVB2;
9213 tmp |= value << TCC_PATTBUF_PGVB2_Pos;
9214 ((Tcc *)hw)->PATTBUF.reg = tmp;
9215 TCC_CRITICAL_SECTION_LEAVE();
9216 }
9217
hri_tcc_clear_PATTBUF_PGVB2_bit(const void * const hw)9218 static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw)
9219 {
9220 TCC_CRITICAL_SECTION_ENTER();
9221 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2;
9222 TCC_CRITICAL_SECTION_LEAVE();
9223 }
9224
hri_tcc_toggle_PATTBUF_PGVB2_bit(const void * const hw)9225 static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw)
9226 {
9227 TCC_CRITICAL_SECTION_ENTER();
9228 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2;
9229 TCC_CRITICAL_SECTION_LEAVE();
9230 }
9231
hri_tcc_set_PATTBUF_PGVB3_bit(const void * const hw)9232 static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw)
9233 {
9234 TCC_CRITICAL_SECTION_ENTER();
9235 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3;
9236 TCC_CRITICAL_SECTION_LEAVE();
9237 }
9238
hri_tcc_get_PATTBUF_PGVB3_bit(const void * const hw)9239 static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw)
9240 {
9241 uint16_t tmp;
9242 tmp = ((Tcc *)hw)->PATTBUF.reg;
9243 tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos;
9244 return (bool)tmp;
9245 }
9246
hri_tcc_write_PATTBUF_PGVB3_bit(const void * const hw,bool value)9247 static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value)
9248 {
9249 uint16_t tmp;
9250 TCC_CRITICAL_SECTION_ENTER();
9251 tmp = ((Tcc *)hw)->PATTBUF.reg;
9252 tmp &= ~TCC_PATTBUF_PGVB3;
9253 tmp |= value << TCC_PATTBUF_PGVB3_Pos;
9254 ((Tcc *)hw)->PATTBUF.reg = tmp;
9255 TCC_CRITICAL_SECTION_LEAVE();
9256 }
9257
hri_tcc_clear_PATTBUF_PGVB3_bit(const void * const hw)9258 static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw)
9259 {
9260 TCC_CRITICAL_SECTION_ENTER();
9261 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3;
9262 TCC_CRITICAL_SECTION_LEAVE();
9263 }
9264
hri_tcc_toggle_PATTBUF_PGVB3_bit(const void * const hw)9265 static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw)
9266 {
9267 TCC_CRITICAL_SECTION_ENTER();
9268 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3;
9269 TCC_CRITICAL_SECTION_LEAVE();
9270 }
9271
hri_tcc_set_PATTBUF_PGVB4_bit(const void * const hw)9272 static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw)
9273 {
9274 TCC_CRITICAL_SECTION_ENTER();
9275 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4;
9276 TCC_CRITICAL_SECTION_LEAVE();
9277 }
9278
hri_tcc_get_PATTBUF_PGVB4_bit(const void * const hw)9279 static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw)
9280 {
9281 uint16_t tmp;
9282 tmp = ((Tcc *)hw)->PATTBUF.reg;
9283 tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos;
9284 return (bool)tmp;
9285 }
9286
hri_tcc_write_PATTBUF_PGVB4_bit(const void * const hw,bool value)9287 static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value)
9288 {
9289 uint16_t tmp;
9290 TCC_CRITICAL_SECTION_ENTER();
9291 tmp = ((Tcc *)hw)->PATTBUF.reg;
9292 tmp &= ~TCC_PATTBUF_PGVB4;
9293 tmp |= value << TCC_PATTBUF_PGVB4_Pos;
9294 ((Tcc *)hw)->PATTBUF.reg = tmp;
9295 TCC_CRITICAL_SECTION_LEAVE();
9296 }
9297
hri_tcc_clear_PATTBUF_PGVB4_bit(const void * const hw)9298 static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw)
9299 {
9300 TCC_CRITICAL_SECTION_ENTER();
9301 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4;
9302 TCC_CRITICAL_SECTION_LEAVE();
9303 }
9304
hri_tcc_toggle_PATTBUF_PGVB4_bit(const void * const hw)9305 static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw)
9306 {
9307 TCC_CRITICAL_SECTION_ENTER();
9308 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4;
9309 TCC_CRITICAL_SECTION_LEAVE();
9310 }
9311
hri_tcc_set_PATTBUF_PGVB5_bit(const void * const hw)9312 static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw)
9313 {
9314 TCC_CRITICAL_SECTION_ENTER();
9315 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5;
9316 TCC_CRITICAL_SECTION_LEAVE();
9317 }
9318
hri_tcc_get_PATTBUF_PGVB5_bit(const void * const hw)9319 static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw)
9320 {
9321 uint16_t tmp;
9322 tmp = ((Tcc *)hw)->PATTBUF.reg;
9323 tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos;
9324 return (bool)tmp;
9325 }
9326
hri_tcc_write_PATTBUF_PGVB5_bit(const void * const hw,bool value)9327 static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value)
9328 {
9329 uint16_t tmp;
9330 TCC_CRITICAL_SECTION_ENTER();
9331 tmp = ((Tcc *)hw)->PATTBUF.reg;
9332 tmp &= ~TCC_PATTBUF_PGVB5;
9333 tmp |= value << TCC_PATTBUF_PGVB5_Pos;
9334 ((Tcc *)hw)->PATTBUF.reg = tmp;
9335 TCC_CRITICAL_SECTION_LEAVE();
9336 }
9337
hri_tcc_clear_PATTBUF_PGVB5_bit(const void * const hw)9338 static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw)
9339 {
9340 TCC_CRITICAL_SECTION_ENTER();
9341 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5;
9342 TCC_CRITICAL_SECTION_LEAVE();
9343 }
9344
hri_tcc_toggle_PATTBUF_PGVB5_bit(const void * const hw)9345 static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw)
9346 {
9347 TCC_CRITICAL_SECTION_ENTER();
9348 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5;
9349 TCC_CRITICAL_SECTION_LEAVE();
9350 }
9351
hri_tcc_set_PATTBUF_PGVB6_bit(const void * const hw)9352 static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw)
9353 {
9354 TCC_CRITICAL_SECTION_ENTER();
9355 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6;
9356 TCC_CRITICAL_SECTION_LEAVE();
9357 }
9358
hri_tcc_get_PATTBUF_PGVB6_bit(const void * const hw)9359 static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw)
9360 {
9361 uint16_t tmp;
9362 tmp = ((Tcc *)hw)->PATTBUF.reg;
9363 tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos;
9364 return (bool)tmp;
9365 }
9366
hri_tcc_write_PATTBUF_PGVB6_bit(const void * const hw,bool value)9367 static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value)
9368 {
9369 uint16_t tmp;
9370 TCC_CRITICAL_SECTION_ENTER();
9371 tmp = ((Tcc *)hw)->PATTBUF.reg;
9372 tmp &= ~TCC_PATTBUF_PGVB6;
9373 tmp |= value << TCC_PATTBUF_PGVB6_Pos;
9374 ((Tcc *)hw)->PATTBUF.reg = tmp;
9375 TCC_CRITICAL_SECTION_LEAVE();
9376 }
9377
hri_tcc_clear_PATTBUF_PGVB6_bit(const void * const hw)9378 static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw)
9379 {
9380 TCC_CRITICAL_SECTION_ENTER();
9381 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6;
9382 TCC_CRITICAL_SECTION_LEAVE();
9383 }
9384
hri_tcc_toggle_PATTBUF_PGVB6_bit(const void * const hw)9385 static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw)
9386 {
9387 TCC_CRITICAL_SECTION_ENTER();
9388 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6;
9389 TCC_CRITICAL_SECTION_LEAVE();
9390 }
9391
hri_tcc_set_PATTBUF_PGVB7_bit(const void * const hw)9392 static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw)
9393 {
9394 TCC_CRITICAL_SECTION_ENTER();
9395 ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7;
9396 TCC_CRITICAL_SECTION_LEAVE();
9397 }
9398
hri_tcc_get_PATTBUF_PGVB7_bit(const void * const hw)9399 static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw)
9400 {
9401 uint16_t tmp;
9402 tmp = ((Tcc *)hw)->PATTBUF.reg;
9403 tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos;
9404 return (bool)tmp;
9405 }
9406
hri_tcc_write_PATTBUF_PGVB7_bit(const void * const hw,bool value)9407 static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value)
9408 {
9409 uint16_t tmp;
9410 TCC_CRITICAL_SECTION_ENTER();
9411 tmp = ((Tcc *)hw)->PATTBUF.reg;
9412 tmp &= ~TCC_PATTBUF_PGVB7;
9413 tmp |= value << TCC_PATTBUF_PGVB7_Pos;
9414 ((Tcc *)hw)->PATTBUF.reg = tmp;
9415 TCC_CRITICAL_SECTION_LEAVE();
9416 }
9417
hri_tcc_clear_PATTBUF_PGVB7_bit(const void * const hw)9418 static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw)
9419 {
9420 TCC_CRITICAL_SECTION_ENTER();
9421 ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7;
9422 TCC_CRITICAL_SECTION_LEAVE();
9423 }
9424
hri_tcc_toggle_PATTBUF_PGVB7_bit(const void * const hw)9425 static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw)
9426 {
9427 TCC_CRITICAL_SECTION_ENTER();
9428 ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7;
9429 TCC_CRITICAL_SECTION_LEAVE();
9430 }
9431
hri_tcc_set_PATTBUF_reg(const void * const hw,hri_tcc_pattbuf_reg_t mask)9432 static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
9433 {
9434 TCC_CRITICAL_SECTION_ENTER();
9435 ((Tcc *)hw)->PATTBUF.reg |= mask;
9436 TCC_CRITICAL_SECTION_LEAVE();
9437 }
9438
hri_tcc_get_PATTBUF_reg(const void * const hw,hri_tcc_pattbuf_reg_t mask)9439 static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
9440 {
9441 uint16_t tmp;
9442 tmp = ((Tcc *)hw)->PATTBUF.reg;
9443 tmp &= mask;
9444 return tmp;
9445 }
9446
hri_tcc_write_PATTBUF_reg(const void * const hw,hri_tcc_pattbuf_reg_t data)9447 static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data)
9448 {
9449 TCC_CRITICAL_SECTION_ENTER();
9450 ((Tcc *)hw)->PATTBUF.reg = data;
9451 TCC_CRITICAL_SECTION_LEAVE();
9452 }
9453
hri_tcc_clear_PATTBUF_reg(const void * const hw,hri_tcc_pattbuf_reg_t mask)9454 static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
9455 {
9456 TCC_CRITICAL_SECTION_ENTER();
9457 ((Tcc *)hw)->PATTBUF.reg &= ~mask;
9458 TCC_CRITICAL_SECTION_LEAVE();
9459 }
9460
hri_tcc_toggle_PATTBUF_reg(const void * const hw,hri_tcc_pattbuf_reg_t mask)9461 static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask)
9462 {
9463 TCC_CRITICAL_SECTION_ENTER();
9464 ((Tcc *)hw)->PATTBUF.reg ^= mask;
9465 TCC_CRITICAL_SECTION_LEAVE();
9466 }
9467
hri_tcc_read_PATTBUF_reg(const void * const hw)9468 static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw)
9469 {
9470 return ((Tcc *)hw)->PATTBUF.reg;
9471 }
9472
hri_tcc_get_SYNCBUSY_SWRST_bit(const void * const hw)9473 static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw)
9474 {
9475 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos;
9476 }
9477
hri_tcc_get_SYNCBUSY_ENABLE_bit(const void * const hw)9478 static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw)
9479 {
9480 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos;
9481 }
9482
hri_tcc_get_SYNCBUSY_CTRLB_bit(const void * const hw)9483 static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw)
9484 {
9485 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos;
9486 }
9487
hri_tcc_get_SYNCBUSY_STATUS_bit(const void * const hw)9488 static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw)
9489 {
9490 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos;
9491 }
9492
hri_tcc_get_SYNCBUSY_COUNT_bit(const void * const hw)9493 static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw)
9494 {
9495 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos;
9496 }
9497
hri_tcc_get_SYNCBUSY_PATT_bit(const void * const hw)9498 static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw)
9499 {
9500 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos;
9501 }
9502
hri_tcc_get_SYNCBUSY_WAVE_bit(const void * const hw)9503 static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw)
9504 {
9505 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos;
9506 }
9507
hri_tcc_get_SYNCBUSY_PER_bit(const void * const hw)9508 static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw)
9509 {
9510 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos;
9511 }
9512
hri_tcc_get_SYNCBUSY_CC0_bit(const void * const hw)9513 static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw)
9514 {
9515 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos;
9516 }
9517
hri_tcc_get_SYNCBUSY_CC1_bit(const void * const hw)9518 static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw)
9519 {
9520 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos;
9521 }
9522
hri_tcc_get_SYNCBUSY_CC2_bit(const void * const hw)9523 static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw)
9524 {
9525 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos;
9526 }
9527
hri_tcc_get_SYNCBUSY_CC3_bit(const void * const hw)9528 static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw)
9529 {
9530 return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos;
9531 }
9532
hri_tcc_get_SYNCBUSY_reg(const void * const hw,hri_tcc_syncbusy_reg_t mask)9533 static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask)
9534 {
9535 uint32_t tmp;
9536 tmp = ((Tcc *)hw)->SYNCBUSY.reg;
9537 tmp &= mask;
9538 return tmp;
9539 }
9540
hri_tcc_read_SYNCBUSY_reg(const void * const hw)9541 static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw)
9542 {
9543 return ((Tcc *)hw)->SYNCBUSY.reg;
9544 }
9545
hri_tcc_get_STATUS_STOP_bit(const void * const hw)9546 static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw)
9547 {
9548 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos;
9549 }
9550
hri_tcc_clear_STATUS_STOP_bit(const void * const hw)9551 static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw)
9552 {
9553 TCC_CRITICAL_SECTION_ENTER();
9554 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP;
9555 TCC_CRITICAL_SECTION_LEAVE();
9556 }
9557
hri_tcc_get_STATUS_IDX_bit(const void * const hw)9558 static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw)
9559 {
9560 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos;
9561 }
9562
hri_tcc_clear_STATUS_IDX_bit(const void * const hw)9563 static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw)
9564 {
9565 TCC_CRITICAL_SECTION_ENTER();
9566 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX;
9567 TCC_CRITICAL_SECTION_LEAVE();
9568 }
9569
hri_tcc_get_STATUS_UFS_bit(const void * const hw)9570 static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw)
9571 {
9572 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos;
9573 }
9574
hri_tcc_clear_STATUS_UFS_bit(const void * const hw)9575 static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw)
9576 {
9577 TCC_CRITICAL_SECTION_ENTER();
9578 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS;
9579 TCC_CRITICAL_SECTION_LEAVE();
9580 }
9581
hri_tcc_get_STATUS_DFS_bit(const void * const hw)9582 static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw)
9583 {
9584 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos;
9585 }
9586
hri_tcc_clear_STATUS_DFS_bit(const void * const hw)9587 static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw)
9588 {
9589 TCC_CRITICAL_SECTION_ENTER();
9590 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS;
9591 TCC_CRITICAL_SECTION_LEAVE();
9592 }
9593
hri_tcc_get_STATUS_SLAVE_bit(const void * const hw)9594 static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw)
9595 {
9596 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos;
9597 }
9598
hri_tcc_clear_STATUS_SLAVE_bit(const void * const hw)9599 static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw)
9600 {
9601 TCC_CRITICAL_SECTION_ENTER();
9602 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE;
9603 TCC_CRITICAL_SECTION_LEAVE();
9604 }
9605
hri_tcc_get_STATUS_PATTBUFV_bit(const void * const hw)9606 static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw)
9607 {
9608 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos;
9609 }
9610
hri_tcc_clear_STATUS_PATTBUFV_bit(const void * const hw)9611 static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw)
9612 {
9613 TCC_CRITICAL_SECTION_ENTER();
9614 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV;
9615 TCC_CRITICAL_SECTION_LEAVE();
9616 }
9617
hri_tcc_get_STATUS_PERBUFV_bit(const void * const hw)9618 static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw)
9619 {
9620 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos;
9621 }
9622
hri_tcc_clear_STATUS_PERBUFV_bit(const void * const hw)9623 static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw)
9624 {
9625 TCC_CRITICAL_SECTION_ENTER();
9626 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV;
9627 TCC_CRITICAL_SECTION_LEAVE();
9628 }
9629
hri_tcc_get_STATUS_FAULTAIN_bit(const void * const hw)9630 static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw)
9631 {
9632 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos;
9633 }
9634
hri_tcc_clear_STATUS_FAULTAIN_bit(const void * const hw)9635 static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw)
9636 {
9637 TCC_CRITICAL_SECTION_ENTER();
9638 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN;
9639 TCC_CRITICAL_SECTION_LEAVE();
9640 }
9641
hri_tcc_get_STATUS_FAULTBIN_bit(const void * const hw)9642 static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw)
9643 {
9644 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos;
9645 }
9646
hri_tcc_clear_STATUS_FAULTBIN_bit(const void * const hw)9647 static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw)
9648 {
9649 TCC_CRITICAL_SECTION_ENTER();
9650 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN;
9651 TCC_CRITICAL_SECTION_LEAVE();
9652 }
9653
hri_tcc_get_STATUS_FAULT0IN_bit(const void * const hw)9654 static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw)
9655 {
9656 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos;
9657 }
9658
hri_tcc_clear_STATUS_FAULT0IN_bit(const void * const hw)9659 static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw)
9660 {
9661 TCC_CRITICAL_SECTION_ENTER();
9662 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN;
9663 TCC_CRITICAL_SECTION_LEAVE();
9664 }
9665
hri_tcc_get_STATUS_FAULT1IN_bit(const void * const hw)9666 static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw)
9667 {
9668 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos;
9669 }
9670
hri_tcc_clear_STATUS_FAULT1IN_bit(const void * const hw)9671 static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw)
9672 {
9673 TCC_CRITICAL_SECTION_ENTER();
9674 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN;
9675 TCC_CRITICAL_SECTION_LEAVE();
9676 }
9677
hri_tcc_get_STATUS_FAULTA_bit(const void * const hw)9678 static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw)
9679 {
9680 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos;
9681 }
9682
hri_tcc_clear_STATUS_FAULTA_bit(const void * const hw)9683 static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw)
9684 {
9685 TCC_CRITICAL_SECTION_ENTER();
9686 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA;
9687 TCC_CRITICAL_SECTION_LEAVE();
9688 }
9689
hri_tcc_get_STATUS_FAULTB_bit(const void * const hw)9690 static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw)
9691 {
9692 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos;
9693 }
9694
hri_tcc_clear_STATUS_FAULTB_bit(const void * const hw)9695 static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw)
9696 {
9697 TCC_CRITICAL_SECTION_ENTER();
9698 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB;
9699 TCC_CRITICAL_SECTION_LEAVE();
9700 }
9701
hri_tcc_get_STATUS_FAULT0_bit(const void * const hw)9702 static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw)
9703 {
9704 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos;
9705 }
9706
hri_tcc_clear_STATUS_FAULT0_bit(const void * const hw)9707 static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw)
9708 {
9709 TCC_CRITICAL_SECTION_ENTER();
9710 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0;
9711 TCC_CRITICAL_SECTION_LEAVE();
9712 }
9713
hri_tcc_get_STATUS_FAULT1_bit(const void * const hw)9714 static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw)
9715 {
9716 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos;
9717 }
9718
hri_tcc_clear_STATUS_FAULT1_bit(const void * const hw)9719 static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw)
9720 {
9721 TCC_CRITICAL_SECTION_ENTER();
9722 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1;
9723 TCC_CRITICAL_SECTION_LEAVE();
9724 }
9725
hri_tcc_get_STATUS_CCBUFV0_bit(const void * const hw)9726 static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw)
9727 {
9728 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos;
9729 }
9730
hri_tcc_clear_STATUS_CCBUFV0_bit(const void * const hw)9731 static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw)
9732 {
9733 TCC_CRITICAL_SECTION_ENTER();
9734 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0;
9735 TCC_CRITICAL_SECTION_LEAVE();
9736 }
9737
hri_tcc_get_STATUS_CCBUFV1_bit(const void * const hw)9738 static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw)
9739 {
9740 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos;
9741 }
9742
hri_tcc_clear_STATUS_CCBUFV1_bit(const void * const hw)9743 static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw)
9744 {
9745 TCC_CRITICAL_SECTION_ENTER();
9746 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1;
9747 TCC_CRITICAL_SECTION_LEAVE();
9748 }
9749
hri_tcc_get_STATUS_CCBUFV2_bit(const void * const hw)9750 static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw)
9751 {
9752 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos;
9753 }
9754
hri_tcc_clear_STATUS_CCBUFV2_bit(const void * const hw)9755 static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw)
9756 {
9757 TCC_CRITICAL_SECTION_ENTER();
9758 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2;
9759 TCC_CRITICAL_SECTION_LEAVE();
9760 }
9761
hri_tcc_get_STATUS_CCBUFV3_bit(const void * const hw)9762 static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw)
9763 {
9764 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos;
9765 }
9766
hri_tcc_clear_STATUS_CCBUFV3_bit(const void * const hw)9767 static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw)
9768 {
9769 TCC_CRITICAL_SECTION_ENTER();
9770 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3;
9771 TCC_CRITICAL_SECTION_LEAVE();
9772 }
9773
hri_tcc_get_STATUS_CMP0_bit(const void * const hw)9774 static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw)
9775 {
9776 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos;
9777 }
9778
hri_tcc_clear_STATUS_CMP0_bit(const void * const hw)9779 static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw)
9780 {
9781 TCC_CRITICAL_SECTION_ENTER();
9782 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0;
9783 TCC_CRITICAL_SECTION_LEAVE();
9784 }
9785
hri_tcc_get_STATUS_CMP1_bit(const void * const hw)9786 static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw)
9787 {
9788 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos;
9789 }
9790
hri_tcc_clear_STATUS_CMP1_bit(const void * const hw)9791 static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw)
9792 {
9793 TCC_CRITICAL_SECTION_ENTER();
9794 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1;
9795 TCC_CRITICAL_SECTION_LEAVE();
9796 }
9797
hri_tcc_get_STATUS_CMP2_bit(const void * const hw)9798 static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw)
9799 {
9800 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos;
9801 }
9802
hri_tcc_clear_STATUS_CMP2_bit(const void * const hw)9803 static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw)
9804 {
9805 TCC_CRITICAL_SECTION_ENTER();
9806 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2;
9807 TCC_CRITICAL_SECTION_LEAVE();
9808 }
9809
hri_tcc_get_STATUS_CMP3_bit(const void * const hw)9810 static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw)
9811 {
9812 return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos;
9813 }
9814
hri_tcc_clear_STATUS_CMP3_bit(const void * const hw)9815 static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw)
9816 {
9817 TCC_CRITICAL_SECTION_ENTER();
9818 ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3;
9819 TCC_CRITICAL_SECTION_LEAVE();
9820 }
9821
hri_tcc_get_STATUS_reg(const void * const hw,hri_tcc_status_reg_t mask)9822 static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
9823 {
9824 uint32_t tmp;
9825 tmp = ((Tcc *)hw)->STATUS.reg;
9826 tmp &= mask;
9827 return tmp;
9828 }
9829
hri_tcc_clear_STATUS_reg(const void * const hw,hri_tcc_status_reg_t mask)9830 static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask)
9831 {
9832 TCC_CRITICAL_SECTION_ENTER();
9833 ((Tcc *)hw)->STATUS.reg = mask;
9834 TCC_CRITICAL_SECTION_LEAVE();
9835 }
9836
hri_tcc_read_STATUS_reg(const void * const hw)9837 static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw)
9838 {
9839 return ((Tcc *)hw)->STATUS.reg;
9840 }
9841
9842 #ifdef __cplusplus
9843 }
9844 #endif
9845
9846 #endif /* _HRI_TCC_L21_H_INCLUDED */
9847 #endif /* _SAML21_TCC_COMPONENT_ */
9848
