1 /**
2 * \file
3 *
4 * \brief SAM TAL
5 *
6 * Copyright (C) 2016 Atmel Corporation. All rights reserved.
7 *
8 * \asf_license_start
9 *
10 * \page License
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 *
18 * 2. Redistributions in binary form must reproduce the above copyright notice,
19 * this list of conditions and the following disclaimer in the documentation
20 * and/or other materials provided with the distribution.
21 *
22 * 3. The name of Atmel may not be used to endorse or promote products derived
23 * from this software without specific prior written permission.
24 *
25 * 4. This software may only be redistributed and used in connection with an
26 * Atmel microcontroller product.
27 *
28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGE.
39 *
40 * \asf_license_stop
41 */
42
43 #ifdef _SAML21_TAL_COMPONENT_
44 #ifndef _HRI_TAL_L21_H_INCLUDED_
45 #define _HRI_TAL_L21_H_INCLUDED_
46
47 #ifdef __cplusplus
48 extern "C" {
49 #endif
50
51 #include <stdbool.h>
52 #include <hal_atomic.h>
53
54 #if defined(ENABLE_TAL_CRITICAL_SECTIONS)
55 #define TAL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
56 #define TAL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
57 #else
58 #define TAL_CRITICAL_SECTION_ENTER()
59 #define TAL_CRITICAL_SECTION_LEAVE()
60 #endif
61
62 typedef uint16_t hri_tal_brkstatus_reg_t;
63 typedef uint16_t hri_tal_irqtrig_reg_t;
64 typedef uint32_t hri_tal_cpuirqs_reg_t;
65 typedef uint32_t hri_tal_dmacpusel0_reg_t;
66 typedef uint32_t hri_tal_eiccpusel0_reg_t;
67 typedef uint32_t hri_tal_evcpusel0_reg_t;
68 typedef uint32_t hri_tal_intcpusel0_reg_t;
69 typedef uint32_t hri_tal_intcpusel1_reg_t;
70 typedef uint8_t hri_tal_ctictrla_reg_t;
71 typedef uint8_t hri_tal_ctimask_reg_t;
72 typedef uint8_t hri_tal_ctrla_reg_t;
73 typedef uint8_t hri_tal_evctrl_reg_t;
74 typedef uint8_t hri_tal_extctrl_reg_t;
75 typedef uint8_t hri_tal_globmask_reg_t;
76 typedef uint8_t hri_tal_halt_reg_t;
77 typedef uint8_t hri_tal_intenset_reg_t;
78 typedef uint8_t hri_tal_intflag_reg_t;
79 typedef uint8_t hri_tal_intstatus_reg_t;
80 typedef uint8_t hri_tal_restart_reg_t;
81 typedef uint8_t hri_tal_rstctrl_reg_t;
82 typedef uint8_t hri_talctis_ctictrla_reg_t;
83 typedef uint8_t hri_talctis_ctimask_reg_t;
84
hri_tal_set_INTEN_BRK_bit(const void * const hw)85 static inline void hri_tal_set_INTEN_BRK_bit(const void *const hw)
86 {
87 ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_BRK;
88 }
89
hri_tal_get_INTEN_BRK_bit(const void * const hw)90 static inline bool hri_tal_get_INTEN_BRK_bit(const void *const hw)
91 {
92 return (((Tal *)hw)->INTENSET.reg & TAL_INTENSET_BRK) >> TAL_INTENSET_BRK_Pos;
93 }
94
hri_tal_write_INTEN_BRK_bit(const void * const hw,bool value)95 static inline void hri_tal_write_INTEN_BRK_bit(const void *const hw, bool value)
96 {
97 if (value == 0x0) {
98 ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_BRK;
99 } else {
100 ((Tal *)hw)->INTENSET.reg = TAL_INTENSET_BRK;
101 }
102 }
103
hri_tal_clear_INTEN_BRK_bit(const void * const hw)104 static inline void hri_tal_clear_INTEN_BRK_bit(const void *const hw)
105 {
106 ((Tal *)hw)->INTENCLR.reg = TAL_INTENSET_BRK;
107 }
108
hri_tal_set_INTEN_reg(const void * const hw,hri_tal_intenset_reg_t mask)109 static inline void hri_tal_set_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t mask)
110 {
111 ((Tal *)hw)->INTENSET.reg = mask;
112 }
113
hri_tal_get_INTEN_reg(const void * const hw,hri_tal_intenset_reg_t mask)114 static inline hri_tal_intenset_reg_t hri_tal_get_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t mask)
115 {
116 uint8_t tmp;
117 tmp = ((Tal *)hw)->INTENSET.reg;
118 tmp &= mask;
119 return tmp;
120 }
121
hri_tal_read_INTEN_reg(const void * const hw)122 static inline hri_tal_intenset_reg_t hri_tal_read_INTEN_reg(const void *const hw)
123 {
124 return ((Tal *)hw)->INTENSET.reg;
125 }
126
hri_tal_write_INTEN_reg(const void * const hw,hri_tal_intenset_reg_t data)127 static inline void hri_tal_write_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t data)
128 {
129 ((Tal *)hw)->INTENSET.reg = data;
130 ((Tal *)hw)->INTENCLR.reg = ~data;
131 }
132
hri_tal_clear_INTEN_reg(const void * const hw,hri_tal_intenset_reg_t mask)133 static inline void hri_tal_clear_INTEN_reg(const void *const hw, hri_tal_intenset_reg_t mask)
134 {
135 ((Tal *)hw)->INTENCLR.reg = mask;
136 }
137
hri_tal_get_INTFLAG_BRK_bit(const void * const hw)138 static inline bool hri_tal_get_INTFLAG_BRK_bit(const void *const hw)
139 {
140 return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_BRK) >> TAL_INTFLAG_BRK_Pos;
141 }
142
hri_tal_clear_INTFLAG_BRK_bit(const void * const hw)143 static inline void hri_tal_clear_INTFLAG_BRK_bit(const void *const hw)
144 {
145 ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_BRK;
146 }
147
hri_tal_get_interrupt_BRK_bit(const void * const hw)148 static inline bool hri_tal_get_interrupt_BRK_bit(const void *const hw)
149 {
150 return (((Tal *)hw)->INTFLAG.reg & TAL_INTFLAG_BRK) >> TAL_INTFLAG_BRK_Pos;
151 }
152
hri_tal_clear_interrupt_BRK_bit(const void * const hw)153 static inline void hri_tal_clear_interrupt_BRK_bit(const void *const hw)
154 {
155 ((Tal *)hw)->INTFLAG.reg = TAL_INTFLAG_BRK;
156 }
157
hri_tal_get_INTFLAG_reg(const void * const hw,hri_tal_intflag_reg_t mask)158 static inline hri_tal_intflag_reg_t hri_tal_get_INTFLAG_reg(const void *const hw, hri_tal_intflag_reg_t mask)
159 {
160 uint8_t tmp;
161 tmp = ((Tal *)hw)->INTFLAG.reg;
162 tmp &= mask;
163 return tmp;
164 }
165
hri_tal_read_INTFLAG_reg(const void * const hw)166 static inline hri_tal_intflag_reg_t hri_tal_read_INTFLAG_reg(const void *const hw)
167 {
168 return ((Tal *)hw)->INTFLAG.reg;
169 }
170
hri_tal_clear_INTFLAG_reg(const void * const hw,hri_tal_intflag_reg_t mask)171 static inline void hri_tal_clear_INTFLAG_reg(const void *const hw, hri_tal_intflag_reg_t mask)
172 {
173 ((Tal *)hw)->INTFLAG.reg = mask;
174 }
175
hri_tal_write_HALT_reg(const void * const hw,hri_tal_halt_reg_t data)176 static inline void hri_tal_write_HALT_reg(const void *const hw, hri_tal_halt_reg_t data)
177 {
178 TAL_CRITICAL_SECTION_ENTER();
179 ((Tal *)hw)->HALT.reg = data;
180 TAL_CRITICAL_SECTION_LEAVE();
181 }
182
hri_tal_write_RESTART_reg(const void * const hw,hri_tal_restart_reg_t data)183 static inline void hri_tal_write_RESTART_reg(const void *const hw, hri_tal_restart_reg_t data)
184 {
185 TAL_CRITICAL_SECTION_ENTER();
186 ((Tal *)hw)->RESTART.reg = data;
187 TAL_CRITICAL_SECTION_LEAVE();
188 }
189
hri_tal_set_CTRLA_SWRST_bit(const void * const hw)190 static inline void hri_tal_set_CTRLA_SWRST_bit(const void *const hw)
191 {
192 TAL_CRITICAL_SECTION_ENTER();
193 ((Tal *)hw)->CTRLA.reg |= TAL_CTRLA_SWRST;
194 TAL_CRITICAL_SECTION_LEAVE();
195 }
196
hri_tal_get_CTRLA_SWRST_bit(const void * const hw)197 static inline bool hri_tal_get_CTRLA_SWRST_bit(const void *const hw)
198 {
199 uint8_t tmp;
200 tmp = ((Tal *)hw)->CTRLA.reg;
201 tmp = (tmp & TAL_CTRLA_SWRST) >> TAL_CTRLA_SWRST_Pos;
202 return (bool)tmp;
203 }
204
hri_tal_set_CTRLA_ENABLE_bit(const void * const hw)205 static inline void hri_tal_set_CTRLA_ENABLE_bit(const void *const hw)
206 {
207 TAL_CRITICAL_SECTION_ENTER();
208 ((Tal *)hw)->CTRLA.reg |= TAL_CTRLA_ENABLE;
209 TAL_CRITICAL_SECTION_LEAVE();
210 }
211
hri_tal_get_CTRLA_ENABLE_bit(const void * const hw)212 static inline bool hri_tal_get_CTRLA_ENABLE_bit(const void *const hw)
213 {
214 uint8_t tmp;
215 tmp = ((Tal *)hw)->CTRLA.reg;
216 tmp = (tmp & TAL_CTRLA_ENABLE) >> TAL_CTRLA_ENABLE_Pos;
217 return (bool)tmp;
218 }
219
hri_tal_write_CTRLA_ENABLE_bit(const void * const hw,bool value)220 static inline void hri_tal_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
221 {
222 uint8_t tmp;
223 TAL_CRITICAL_SECTION_ENTER();
224 tmp = ((Tal *)hw)->CTRLA.reg;
225 tmp &= ~TAL_CTRLA_ENABLE;
226 tmp |= value << TAL_CTRLA_ENABLE_Pos;
227 ((Tal *)hw)->CTRLA.reg = tmp;
228 TAL_CRITICAL_SECTION_LEAVE();
229 }
230
hri_tal_clear_CTRLA_ENABLE_bit(const void * const hw)231 static inline void hri_tal_clear_CTRLA_ENABLE_bit(const void *const hw)
232 {
233 TAL_CRITICAL_SECTION_ENTER();
234 ((Tal *)hw)->CTRLA.reg &= ~TAL_CTRLA_ENABLE;
235 TAL_CRITICAL_SECTION_LEAVE();
236 }
237
hri_tal_toggle_CTRLA_ENABLE_bit(const void * const hw)238 static inline void hri_tal_toggle_CTRLA_ENABLE_bit(const void *const hw)
239 {
240 TAL_CRITICAL_SECTION_ENTER();
241 ((Tal *)hw)->CTRLA.reg ^= TAL_CTRLA_ENABLE;
242 TAL_CRITICAL_SECTION_LEAVE();
243 }
244
hri_tal_set_CTRLA_reg(const void * const hw,hri_tal_ctrla_reg_t mask)245 static inline void hri_tal_set_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask)
246 {
247 TAL_CRITICAL_SECTION_ENTER();
248 ((Tal *)hw)->CTRLA.reg |= mask;
249 TAL_CRITICAL_SECTION_LEAVE();
250 }
251
hri_tal_get_CTRLA_reg(const void * const hw,hri_tal_ctrla_reg_t mask)252 static inline hri_tal_ctrla_reg_t hri_tal_get_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask)
253 {
254 uint8_t tmp;
255 tmp = ((Tal *)hw)->CTRLA.reg;
256 tmp &= mask;
257 return tmp;
258 }
259
hri_tal_write_CTRLA_reg(const void * const hw,hri_tal_ctrla_reg_t data)260 static inline void hri_tal_write_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t data)
261 {
262 TAL_CRITICAL_SECTION_ENTER();
263 ((Tal *)hw)->CTRLA.reg = data;
264 TAL_CRITICAL_SECTION_LEAVE();
265 }
266
hri_tal_clear_CTRLA_reg(const void * const hw,hri_tal_ctrla_reg_t mask)267 static inline void hri_tal_clear_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask)
268 {
269 TAL_CRITICAL_SECTION_ENTER();
270 ((Tal *)hw)->CTRLA.reg &= ~mask;
271 TAL_CRITICAL_SECTION_LEAVE();
272 }
273
hri_tal_toggle_CTRLA_reg(const void * const hw,hri_tal_ctrla_reg_t mask)274 static inline void hri_tal_toggle_CTRLA_reg(const void *const hw, hri_tal_ctrla_reg_t mask)
275 {
276 TAL_CRITICAL_SECTION_ENTER();
277 ((Tal *)hw)->CTRLA.reg ^= mask;
278 TAL_CRITICAL_SECTION_LEAVE();
279 }
280
hri_tal_read_CTRLA_reg(const void * const hw)281 static inline hri_tal_ctrla_reg_t hri_tal_read_CTRLA_reg(const void *const hw)
282 {
283 return ((Tal *)hw)->CTRLA.reg;
284 }
285
hri_tal_set_RSTCTRL_reg(const void * const hw,hri_tal_rstctrl_reg_t mask)286 static inline void hri_tal_set_RSTCTRL_reg(const void *const hw, hri_tal_rstctrl_reg_t mask)
287 {
288 TAL_CRITICAL_SECTION_ENTER();
289 ((Tal *)hw)->RSTCTRL.reg |= mask;
290 TAL_CRITICAL_SECTION_LEAVE();
291 }
292
hri_tal_get_RSTCTRL_reg(const void * const hw,hri_tal_rstctrl_reg_t mask)293 static inline hri_tal_rstctrl_reg_t hri_tal_get_RSTCTRL_reg(const void *const hw, hri_tal_rstctrl_reg_t mask)
294 {
295 uint8_t tmp;
296 tmp = ((Tal *)hw)->RSTCTRL.reg;
297 tmp &= mask;
298 return tmp;
299 }
300
hri_tal_write_RSTCTRL_reg(const void * const hw,hri_tal_rstctrl_reg_t data)301 static inline void hri_tal_write_RSTCTRL_reg(const void *const hw, hri_tal_rstctrl_reg_t data)
302 {
303 TAL_CRITICAL_SECTION_ENTER();
304 ((Tal *)hw)->RSTCTRL.reg = data;
305 TAL_CRITICAL_SECTION_LEAVE();
306 }
307
hri_tal_clear_RSTCTRL_reg(const void * const hw,hri_tal_rstctrl_reg_t mask)308 static inline void hri_tal_clear_RSTCTRL_reg(const void *const hw, hri_tal_rstctrl_reg_t mask)
309 {
310 TAL_CRITICAL_SECTION_ENTER();
311 ((Tal *)hw)->RSTCTRL.reg &= ~mask;
312 TAL_CRITICAL_SECTION_LEAVE();
313 }
314
hri_tal_toggle_RSTCTRL_reg(const void * const hw,hri_tal_rstctrl_reg_t mask)315 static inline void hri_tal_toggle_RSTCTRL_reg(const void *const hw, hri_tal_rstctrl_reg_t mask)
316 {
317 TAL_CRITICAL_SECTION_ENTER();
318 ((Tal *)hw)->RSTCTRL.reg ^= mask;
319 TAL_CRITICAL_SECTION_LEAVE();
320 }
321
hri_tal_read_RSTCTRL_reg(const void * const hw)322 static inline hri_tal_rstctrl_reg_t hri_tal_read_RSTCTRL_reg(const void *const hw)
323 {
324 return ((Tal *)hw)->RSTCTRL.reg;
325 }
326
hri_tal_set_EXTCTRL_ENABLE_bit(const void * const hw)327 static inline void hri_tal_set_EXTCTRL_ENABLE_bit(const void *const hw)
328 {
329 TAL_CRITICAL_SECTION_ENTER();
330 ((Tal *)hw)->EXTCTRL.reg |= TAL_EXTCTRL_ENABLE;
331 TAL_CRITICAL_SECTION_LEAVE();
332 }
333
hri_tal_get_EXTCTRL_ENABLE_bit(const void * const hw)334 static inline bool hri_tal_get_EXTCTRL_ENABLE_bit(const void *const hw)
335 {
336 uint8_t tmp;
337 tmp = ((Tal *)hw)->EXTCTRL.reg;
338 tmp = (tmp & TAL_EXTCTRL_ENABLE) >> TAL_EXTCTRL_ENABLE_Pos;
339 return (bool)tmp;
340 }
341
hri_tal_write_EXTCTRL_ENABLE_bit(const void * const hw,bool value)342 static inline void hri_tal_write_EXTCTRL_ENABLE_bit(const void *const hw, bool value)
343 {
344 uint8_t tmp;
345 TAL_CRITICAL_SECTION_ENTER();
346 tmp = ((Tal *)hw)->EXTCTRL.reg;
347 tmp &= ~TAL_EXTCTRL_ENABLE;
348 tmp |= value << TAL_EXTCTRL_ENABLE_Pos;
349 ((Tal *)hw)->EXTCTRL.reg = tmp;
350 TAL_CRITICAL_SECTION_LEAVE();
351 }
352
hri_tal_clear_EXTCTRL_ENABLE_bit(const void * const hw)353 static inline void hri_tal_clear_EXTCTRL_ENABLE_bit(const void *const hw)
354 {
355 TAL_CRITICAL_SECTION_ENTER();
356 ((Tal *)hw)->EXTCTRL.reg &= ~TAL_EXTCTRL_ENABLE;
357 TAL_CRITICAL_SECTION_LEAVE();
358 }
359
hri_tal_toggle_EXTCTRL_ENABLE_bit(const void * const hw)360 static inline void hri_tal_toggle_EXTCTRL_ENABLE_bit(const void *const hw)
361 {
362 TAL_CRITICAL_SECTION_ENTER();
363 ((Tal *)hw)->EXTCTRL.reg ^= TAL_EXTCTRL_ENABLE;
364 TAL_CRITICAL_SECTION_LEAVE();
365 }
366
hri_tal_set_EXTCTRL_INV_bit(const void * const hw)367 static inline void hri_tal_set_EXTCTRL_INV_bit(const void *const hw)
368 {
369 TAL_CRITICAL_SECTION_ENTER();
370 ((Tal *)hw)->EXTCTRL.reg |= TAL_EXTCTRL_INV;
371 TAL_CRITICAL_SECTION_LEAVE();
372 }
373
hri_tal_get_EXTCTRL_INV_bit(const void * const hw)374 static inline bool hri_tal_get_EXTCTRL_INV_bit(const void *const hw)
375 {
376 uint8_t tmp;
377 tmp = ((Tal *)hw)->EXTCTRL.reg;
378 tmp = (tmp & TAL_EXTCTRL_INV) >> TAL_EXTCTRL_INV_Pos;
379 return (bool)tmp;
380 }
381
hri_tal_write_EXTCTRL_INV_bit(const void * const hw,bool value)382 static inline void hri_tal_write_EXTCTRL_INV_bit(const void *const hw, bool value)
383 {
384 uint8_t tmp;
385 TAL_CRITICAL_SECTION_ENTER();
386 tmp = ((Tal *)hw)->EXTCTRL.reg;
387 tmp &= ~TAL_EXTCTRL_INV;
388 tmp |= value << TAL_EXTCTRL_INV_Pos;
389 ((Tal *)hw)->EXTCTRL.reg = tmp;
390 TAL_CRITICAL_SECTION_LEAVE();
391 }
392
hri_tal_clear_EXTCTRL_INV_bit(const void * const hw)393 static inline void hri_tal_clear_EXTCTRL_INV_bit(const void *const hw)
394 {
395 TAL_CRITICAL_SECTION_ENTER();
396 ((Tal *)hw)->EXTCTRL.reg &= ~TAL_EXTCTRL_INV;
397 TAL_CRITICAL_SECTION_LEAVE();
398 }
399
hri_tal_toggle_EXTCTRL_INV_bit(const void * const hw)400 static inline void hri_tal_toggle_EXTCTRL_INV_bit(const void *const hw)
401 {
402 TAL_CRITICAL_SECTION_ENTER();
403 ((Tal *)hw)->EXTCTRL.reg ^= TAL_EXTCTRL_INV;
404 TAL_CRITICAL_SECTION_LEAVE();
405 }
406
hri_tal_set_EXTCTRL_reg(const void * const hw,hri_tal_extctrl_reg_t mask)407 static inline void hri_tal_set_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask)
408 {
409 TAL_CRITICAL_SECTION_ENTER();
410 ((Tal *)hw)->EXTCTRL.reg |= mask;
411 TAL_CRITICAL_SECTION_LEAVE();
412 }
413
hri_tal_get_EXTCTRL_reg(const void * const hw,hri_tal_extctrl_reg_t mask)414 static inline hri_tal_extctrl_reg_t hri_tal_get_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask)
415 {
416 uint8_t tmp;
417 tmp = ((Tal *)hw)->EXTCTRL.reg;
418 tmp &= mask;
419 return tmp;
420 }
421
hri_tal_write_EXTCTRL_reg(const void * const hw,hri_tal_extctrl_reg_t data)422 static inline void hri_tal_write_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t data)
423 {
424 TAL_CRITICAL_SECTION_ENTER();
425 ((Tal *)hw)->EXTCTRL.reg = data;
426 TAL_CRITICAL_SECTION_LEAVE();
427 }
428
hri_tal_clear_EXTCTRL_reg(const void * const hw,hri_tal_extctrl_reg_t mask)429 static inline void hri_tal_clear_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask)
430 {
431 TAL_CRITICAL_SECTION_ENTER();
432 ((Tal *)hw)->EXTCTRL.reg &= ~mask;
433 TAL_CRITICAL_SECTION_LEAVE();
434 }
435
hri_tal_toggle_EXTCTRL_reg(const void * const hw,hri_tal_extctrl_reg_t mask)436 static inline void hri_tal_toggle_EXTCTRL_reg(const void *const hw, hri_tal_extctrl_reg_t mask)
437 {
438 TAL_CRITICAL_SECTION_ENTER();
439 ((Tal *)hw)->EXTCTRL.reg ^= mask;
440 TAL_CRITICAL_SECTION_LEAVE();
441 }
442
hri_tal_read_EXTCTRL_reg(const void * const hw)443 static inline hri_tal_extctrl_reg_t hri_tal_read_EXTCTRL_reg(const void *const hw)
444 {
445 return ((Tal *)hw)->EXTCTRL.reg;
446 }
447
hri_tal_set_EVCTRL_BRKEI_bit(const void * const hw)448 static inline void hri_tal_set_EVCTRL_BRKEI_bit(const void *const hw)
449 {
450 TAL_CRITICAL_SECTION_ENTER();
451 ((Tal *)hw)->EVCTRL.reg |= TAL_EVCTRL_BRKEI;
452 TAL_CRITICAL_SECTION_LEAVE();
453 }
454
hri_tal_get_EVCTRL_BRKEI_bit(const void * const hw)455 static inline bool hri_tal_get_EVCTRL_BRKEI_bit(const void *const hw)
456 {
457 uint8_t tmp;
458 tmp = ((Tal *)hw)->EVCTRL.reg;
459 tmp = (tmp & TAL_EVCTRL_BRKEI) >> TAL_EVCTRL_BRKEI_Pos;
460 return (bool)tmp;
461 }
462
hri_tal_write_EVCTRL_BRKEI_bit(const void * const hw,bool value)463 static inline void hri_tal_write_EVCTRL_BRKEI_bit(const void *const hw, bool value)
464 {
465 uint8_t tmp;
466 TAL_CRITICAL_SECTION_ENTER();
467 tmp = ((Tal *)hw)->EVCTRL.reg;
468 tmp &= ~TAL_EVCTRL_BRKEI;
469 tmp |= value << TAL_EVCTRL_BRKEI_Pos;
470 ((Tal *)hw)->EVCTRL.reg = tmp;
471 TAL_CRITICAL_SECTION_LEAVE();
472 }
473
hri_tal_clear_EVCTRL_BRKEI_bit(const void * const hw)474 static inline void hri_tal_clear_EVCTRL_BRKEI_bit(const void *const hw)
475 {
476 TAL_CRITICAL_SECTION_ENTER();
477 ((Tal *)hw)->EVCTRL.reg &= ~TAL_EVCTRL_BRKEI;
478 TAL_CRITICAL_SECTION_LEAVE();
479 }
480
hri_tal_toggle_EVCTRL_BRKEI_bit(const void * const hw)481 static inline void hri_tal_toggle_EVCTRL_BRKEI_bit(const void *const hw)
482 {
483 TAL_CRITICAL_SECTION_ENTER();
484 ((Tal *)hw)->EVCTRL.reg ^= TAL_EVCTRL_BRKEI;
485 TAL_CRITICAL_SECTION_LEAVE();
486 }
487
hri_tal_set_EVCTRL_BRKEO_bit(const void * const hw)488 static inline void hri_tal_set_EVCTRL_BRKEO_bit(const void *const hw)
489 {
490 TAL_CRITICAL_SECTION_ENTER();
491 ((Tal *)hw)->EVCTRL.reg |= TAL_EVCTRL_BRKEO;
492 TAL_CRITICAL_SECTION_LEAVE();
493 }
494
hri_tal_get_EVCTRL_BRKEO_bit(const void * const hw)495 static inline bool hri_tal_get_EVCTRL_BRKEO_bit(const void *const hw)
496 {
497 uint8_t tmp;
498 tmp = ((Tal *)hw)->EVCTRL.reg;
499 tmp = (tmp & TAL_EVCTRL_BRKEO) >> TAL_EVCTRL_BRKEO_Pos;
500 return (bool)tmp;
501 }
502
hri_tal_write_EVCTRL_BRKEO_bit(const void * const hw,bool value)503 static inline void hri_tal_write_EVCTRL_BRKEO_bit(const void *const hw, bool value)
504 {
505 uint8_t tmp;
506 TAL_CRITICAL_SECTION_ENTER();
507 tmp = ((Tal *)hw)->EVCTRL.reg;
508 tmp &= ~TAL_EVCTRL_BRKEO;
509 tmp |= value << TAL_EVCTRL_BRKEO_Pos;
510 ((Tal *)hw)->EVCTRL.reg = tmp;
511 TAL_CRITICAL_SECTION_LEAVE();
512 }
513
hri_tal_clear_EVCTRL_BRKEO_bit(const void * const hw)514 static inline void hri_tal_clear_EVCTRL_BRKEO_bit(const void *const hw)
515 {
516 TAL_CRITICAL_SECTION_ENTER();
517 ((Tal *)hw)->EVCTRL.reg &= ~TAL_EVCTRL_BRKEO;
518 TAL_CRITICAL_SECTION_LEAVE();
519 }
520
hri_tal_toggle_EVCTRL_BRKEO_bit(const void * const hw)521 static inline void hri_tal_toggle_EVCTRL_BRKEO_bit(const void *const hw)
522 {
523 TAL_CRITICAL_SECTION_ENTER();
524 ((Tal *)hw)->EVCTRL.reg ^= TAL_EVCTRL_BRKEO;
525 TAL_CRITICAL_SECTION_LEAVE();
526 }
527
hri_tal_set_EVCTRL_reg(const void * const hw,hri_tal_evctrl_reg_t mask)528 static inline void hri_tal_set_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask)
529 {
530 TAL_CRITICAL_SECTION_ENTER();
531 ((Tal *)hw)->EVCTRL.reg |= mask;
532 TAL_CRITICAL_SECTION_LEAVE();
533 }
534
hri_tal_get_EVCTRL_reg(const void * const hw,hri_tal_evctrl_reg_t mask)535 static inline hri_tal_evctrl_reg_t hri_tal_get_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask)
536 {
537 uint8_t tmp;
538 tmp = ((Tal *)hw)->EVCTRL.reg;
539 tmp &= mask;
540 return tmp;
541 }
542
hri_tal_write_EVCTRL_reg(const void * const hw,hri_tal_evctrl_reg_t data)543 static inline void hri_tal_write_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t data)
544 {
545 TAL_CRITICAL_SECTION_ENTER();
546 ((Tal *)hw)->EVCTRL.reg = data;
547 TAL_CRITICAL_SECTION_LEAVE();
548 }
549
hri_tal_clear_EVCTRL_reg(const void * const hw,hri_tal_evctrl_reg_t mask)550 static inline void hri_tal_clear_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask)
551 {
552 TAL_CRITICAL_SECTION_ENTER();
553 ((Tal *)hw)->EVCTRL.reg &= ~mask;
554 TAL_CRITICAL_SECTION_LEAVE();
555 }
556
hri_tal_toggle_EVCTRL_reg(const void * const hw,hri_tal_evctrl_reg_t mask)557 static inline void hri_tal_toggle_EVCTRL_reg(const void *const hw, hri_tal_evctrl_reg_t mask)
558 {
559 TAL_CRITICAL_SECTION_ENTER();
560 ((Tal *)hw)->EVCTRL.reg ^= mask;
561 TAL_CRITICAL_SECTION_LEAVE();
562 }
563
hri_tal_read_EVCTRL_reg(const void * const hw)564 static inline hri_tal_evctrl_reg_t hri_tal_read_EVCTRL_reg(const void *const hw)
565 {
566 return ((Tal *)hw)->EVCTRL.reg;
567 }
568
hri_tal_set_GLOBMASK_CM0P_bit(const void * const hw)569 static inline void hri_tal_set_GLOBMASK_CM0P_bit(const void *const hw)
570 {
571 TAL_CRITICAL_SECTION_ENTER();
572 ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_CM0P;
573 TAL_CRITICAL_SECTION_LEAVE();
574 }
575
hri_tal_get_GLOBMASK_CM0P_bit(const void * const hw)576 static inline bool hri_tal_get_GLOBMASK_CM0P_bit(const void *const hw)
577 {
578 uint8_t tmp;
579 tmp = ((Tal *)hw)->GLOBMASK.reg;
580 tmp = (tmp & TAL_GLOBMASK_CM0P) >> TAL_GLOBMASK_CM0P_Pos;
581 return (bool)tmp;
582 }
583
hri_tal_write_GLOBMASK_CM0P_bit(const void * const hw,bool value)584 static inline void hri_tal_write_GLOBMASK_CM0P_bit(const void *const hw, bool value)
585 {
586 uint8_t tmp;
587 TAL_CRITICAL_SECTION_ENTER();
588 tmp = ((Tal *)hw)->GLOBMASK.reg;
589 tmp &= ~TAL_GLOBMASK_CM0P;
590 tmp |= value << TAL_GLOBMASK_CM0P_Pos;
591 ((Tal *)hw)->GLOBMASK.reg = tmp;
592 TAL_CRITICAL_SECTION_LEAVE();
593 }
594
hri_tal_clear_GLOBMASK_CM0P_bit(const void * const hw)595 static inline void hri_tal_clear_GLOBMASK_CM0P_bit(const void *const hw)
596 {
597 TAL_CRITICAL_SECTION_ENTER();
598 ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_CM0P;
599 TAL_CRITICAL_SECTION_LEAVE();
600 }
601
hri_tal_toggle_GLOBMASK_CM0P_bit(const void * const hw)602 static inline void hri_tal_toggle_GLOBMASK_CM0P_bit(const void *const hw)
603 {
604 TAL_CRITICAL_SECTION_ENTER();
605 ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_CM0P;
606 TAL_CRITICAL_SECTION_LEAVE();
607 }
608
hri_tal_set_GLOBMASK_PPP_bit(const void * const hw)609 static inline void hri_tal_set_GLOBMASK_PPP_bit(const void *const hw)
610 {
611 TAL_CRITICAL_SECTION_ENTER();
612 ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_PPP;
613 TAL_CRITICAL_SECTION_LEAVE();
614 }
615
hri_tal_get_GLOBMASK_PPP_bit(const void * const hw)616 static inline bool hri_tal_get_GLOBMASK_PPP_bit(const void *const hw)
617 {
618 uint8_t tmp;
619 tmp = ((Tal *)hw)->GLOBMASK.reg;
620 tmp = (tmp & TAL_GLOBMASK_PPP) >> TAL_GLOBMASK_PPP_Pos;
621 return (bool)tmp;
622 }
623
hri_tal_write_GLOBMASK_PPP_bit(const void * const hw,bool value)624 static inline void hri_tal_write_GLOBMASK_PPP_bit(const void *const hw, bool value)
625 {
626 uint8_t tmp;
627 TAL_CRITICAL_SECTION_ENTER();
628 tmp = ((Tal *)hw)->GLOBMASK.reg;
629 tmp &= ~TAL_GLOBMASK_PPP;
630 tmp |= value << TAL_GLOBMASK_PPP_Pos;
631 ((Tal *)hw)->GLOBMASK.reg = tmp;
632 TAL_CRITICAL_SECTION_LEAVE();
633 }
634
hri_tal_clear_GLOBMASK_PPP_bit(const void * const hw)635 static inline void hri_tal_clear_GLOBMASK_PPP_bit(const void *const hw)
636 {
637 TAL_CRITICAL_SECTION_ENTER();
638 ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_PPP;
639 TAL_CRITICAL_SECTION_LEAVE();
640 }
641
hri_tal_toggle_GLOBMASK_PPP_bit(const void * const hw)642 static inline void hri_tal_toggle_GLOBMASK_PPP_bit(const void *const hw)
643 {
644 TAL_CRITICAL_SECTION_ENTER();
645 ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_PPP;
646 TAL_CRITICAL_SECTION_LEAVE();
647 }
648
hri_tal_set_GLOBMASK_EVBRK_bit(const void * const hw)649 static inline void hri_tal_set_GLOBMASK_EVBRK_bit(const void *const hw)
650 {
651 TAL_CRITICAL_SECTION_ENTER();
652 ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_EVBRK;
653 TAL_CRITICAL_SECTION_LEAVE();
654 }
655
hri_tal_get_GLOBMASK_EVBRK_bit(const void * const hw)656 static inline bool hri_tal_get_GLOBMASK_EVBRK_bit(const void *const hw)
657 {
658 uint8_t tmp;
659 tmp = ((Tal *)hw)->GLOBMASK.reg;
660 tmp = (tmp & TAL_GLOBMASK_EVBRK) >> TAL_GLOBMASK_EVBRK_Pos;
661 return (bool)tmp;
662 }
663
hri_tal_write_GLOBMASK_EVBRK_bit(const void * const hw,bool value)664 static inline void hri_tal_write_GLOBMASK_EVBRK_bit(const void *const hw, bool value)
665 {
666 uint8_t tmp;
667 TAL_CRITICAL_SECTION_ENTER();
668 tmp = ((Tal *)hw)->GLOBMASK.reg;
669 tmp &= ~TAL_GLOBMASK_EVBRK;
670 tmp |= value << TAL_GLOBMASK_EVBRK_Pos;
671 ((Tal *)hw)->GLOBMASK.reg = tmp;
672 TAL_CRITICAL_SECTION_LEAVE();
673 }
674
hri_tal_clear_GLOBMASK_EVBRK_bit(const void * const hw)675 static inline void hri_tal_clear_GLOBMASK_EVBRK_bit(const void *const hw)
676 {
677 TAL_CRITICAL_SECTION_ENTER();
678 ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_EVBRK;
679 TAL_CRITICAL_SECTION_LEAVE();
680 }
681
hri_tal_toggle_GLOBMASK_EVBRK_bit(const void * const hw)682 static inline void hri_tal_toggle_GLOBMASK_EVBRK_bit(const void *const hw)
683 {
684 TAL_CRITICAL_SECTION_ENTER();
685 ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_EVBRK;
686 TAL_CRITICAL_SECTION_LEAVE();
687 }
688
hri_tal_set_GLOBMASK_EXTBRK_bit(const void * const hw)689 static inline void hri_tal_set_GLOBMASK_EXTBRK_bit(const void *const hw)
690 {
691 TAL_CRITICAL_SECTION_ENTER();
692 ((Tal *)hw)->GLOBMASK.reg |= TAL_GLOBMASK_EXTBRK;
693 TAL_CRITICAL_SECTION_LEAVE();
694 }
695
hri_tal_get_GLOBMASK_EXTBRK_bit(const void * const hw)696 static inline bool hri_tal_get_GLOBMASK_EXTBRK_bit(const void *const hw)
697 {
698 uint8_t tmp;
699 tmp = ((Tal *)hw)->GLOBMASK.reg;
700 tmp = (tmp & TAL_GLOBMASK_EXTBRK) >> TAL_GLOBMASK_EXTBRK_Pos;
701 return (bool)tmp;
702 }
703
hri_tal_write_GLOBMASK_EXTBRK_bit(const void * const hw,bool value)704 static inline void hri_tal_write_GLOBMASK_EXTBRK_bit(const void *const hw, bool value)
705 {
706 uint8_t tmp;
707 TAL_CRITICAL_SECTION_ENTER();
708 tmp = ((Tal *)hw)->GLOBMASK.reg;
709 tmp &= ~TAL_GLOBMASK_EXTBRK;
710 tmp |= value << TAL_GLOBMASK_EXTBRK_Pos;
711 ((Tal *)hw)->GLOBMASK.reg = tmp;
712 TAL_CRITICAL_SECTION_LEAVE();
713 }
714
hri_tal_clear_GLOBMASK_EXTBRK_bit(const void * const hw)715 static inline void hri_tal_clear_GLOBMASK_EXTBRK_bit(const void *const hw)
716 {
717 TAL_CRITICAL_SECTION_ENTER();
718 ((Tal *)hw)->GLOBMASK.reg &= ~TAL_GLOBMASK_EXTBRK;
719 TAL_CRITICAL_SECTION_LEAVE();
720 }
721
hri_tal_toggle_GLOBMASK_EXTBRK_bit(const void * const hw)722 static inline void hri_tal_toggle_GLOBMASK_EXTBRK_bit(const void *const hw)
723 {
724 TAL_CRITICAL_SECTION_ENTER();
725 ((Tal *)hw)->GLOBMASK.reg ^= TAL_GLOBMASK_EXTBRK;
726 TAL_CRITICAL_SECTION_LEAVE();
727 }
728
hri_tal_set_GLOBMASK_reg(const void * const hw,hri_tal_globmask_reg_t mask)729 static inline void hri_tal_set_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask)
730 {
731 TAL_CRITICAL_SECTION_ENTER();
732 ((Tal *)hw)->GLOBMASK.reg |= mask;
733 TAL_CRITICAL_SECTION_LEAVE();
734 }
735
hri_tal_get_GLOBMASK_reg(const void * const hw,hri_tal_globmask_reg_t mask)736 static inline hri_tal_globmask_reg_t hri_tal_get_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask)
737 {
738 uint8_t tmp;
739 tmp = ((Tal *)hw)->GLOBMASK.reg;
740 tmp &= mask;
741 return tmp;
742 }
743
hri_tal_write_GLOBMASK_reg(const void * const hw,hri_tal_globmask_reg_t data)744 static inline void hri_tal_write_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t data)
745 {
746 TAL_CRITICAL_SECTION_ENTER();
747 ((Tal *)hw)->GLOBMASK.reg = data;
748 TAL_CRITICAL_SECTION_LEAVE();
749 }
750
hri_tal_clear_GLOBMASK_reg(const void * const hw,hri_tal_globmask_reg_t mask)751 static inline void hri_tal_clear_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask)
752 {
753 TAL_CRITICAL_SECTION_ENTER();
754 ((Tal *)hw)->GLOBMASK.reg &= ~mask;
755 TAL_CRITICAL_SECTION_LEAVE();
756 }
757
hri_tal_toggle_GLOBMASK_reg(const void * const hw,hri_tal_globmask_reg_t mask)758 static inline void hri_tal_toggle_GLOBMASK_reg(const void *const hw, hri_tal_globmask_reg_t mask)
759 {
760 TAL_CRITICAL_SECTION_ENTER();
761 ((Tal *)hw)->GLOBMASK.reg ^= mask;
762 TAL_CRITICAL_SECTION_LEAVE();
763 }
764
hri_tal_read_GLOBMASK_reg(const void * const hw)765 static inline hri_tal_globmask_reg_t hri_tal_read_GLOBMASK_reg(const void *const hw)
766 {
767 return ((Tal *)hw)->GLOBMASK.reg;
768 }
769
hri_tal_set_DMACPUSEL0_CH0_bit(const void * const hw)770 static inline void hri_tal_set_DMACPUSEL0_CH0_bit(const void *const hw)
771 {
772 TAL_CRITICAL_SECTION_ENTER();
773 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH0_Msk;
774 TAL_CRITICAL_SECTION_LEAVE();
775 }
776
hri_tal_get_DMACPUSEL0_CH0_bit(const void * const hw)777 static inline bool hri_tal_get_DMACPUSEL0_CH0_bit(const void *const hw)
778 {
779 uint32_t tmp;
780 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
781 tmp = (tmp & TAL_DMACPUSEL0_CH0_Msk) >> TAL_DMACPUSEL0_CH0_Pos;
782 return (bool)tmp;
783 }
784
hri_tal_write_DMACPUSEL0_CH0_bit(const void * const hw,bool value)785 static inline void hri_tal_write_DMACPUSEL0_CH0_bit(const void *const hw, bool value)
786 {
787 uint32_t tmp;
788 TAL_CRITICAL_SECTION_ENTER();
789 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
790 tmp &= ~TAL_DMACPUSEL0_CH0_Msk;
791 tmp |= value << TAL_DMACPUSEL0_CH0_Pos;
792 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
793 TAL_CRITICAL_SECTION_LEAVE();
794 }
795
hri_tal_clear_DMACPUSEL0_CH0_bit(const void * const hw)796 static inline void hri_tal_clear_DMACPUSEL0_CH0_bit(const void *const hw)
797 {
798 TAL_CRITICAL_SECTION_ENTER();
799 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH0_Msk;
800 TAL_CRITICAL_SECTION_LEAVE();
801 }
802
hri_tal_toggle_DMACPUSEL0_CH0_bit(const void * const hw)803 static inline void hri_tal_toggle_DMACPUSEL0_CH0_bit(const void *const hw)
804 {
805 TAL_CRITICAL_SECTION_ENTER();
806 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH0_Msk;
807 TAL_CRITICAL_SECTION_LEAVE();
808 }
809
hri_tal_set_DMACPUSEL0_CH1_bit(const void * const hw)810 static inline void hri_tal_set_DMACPUSEL0_CH1_bit(const void *const hw)
811 {
812 TAL_CRITICAL_SECTION_ENTER();
813 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH1_Msk;
814 TAL_CRITICAL_SECTION_LEAVE();
815 }
816
hri_tal_get_DMACPUSEL0_CH1_bit(const void * const hw)817 static inline bool hri_tal_get_DMACPUSEL0_CH1_bit(const void *const hw)
818 {
819 uint32_t tmp;
820 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
821 tmp = (tmp & TAL_DMACPUSEL0_CH1_Msk) >> TAL_DMACPUSEL0_CH1_Pos;
822 return (bool)tmp;
823 }
824
hri_tal_write_DMACPUSEL0_CH1_bit(const void * const hw,bool value)825 static inline void hri_tal_write_DMACPUSEL0_CH1_bit(const void *const hw, bool value)
826 {
827 uint32_t tmp;
828 TAL_CRITICAL_SECTION_ENTER();
829 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
830 tmp &= ~TAL_DMACPUSEL0_CH1_Msk;
831 tmp |= value << TAL_DMACPUSEL0_CH1_Pos;
832 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
833 TAL_CRITICAL_SECTION_LEAVE();
834 }
835
hri_tal_clear_DMACPUSEL0_CH1_bit(const void * const hw)836 static inline void hri_tal_clear_DMACPUSEL0_CH1_bit(const void *const hw)
837 {
838 TAL_CRITICAL_SECTION_ENTER();
839 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH1_Msk;
840 TAL_CRITICAL_SECTION_LEAVE();
841 }
842
hri_tal_toggle_DMACPUSEL0_CH1_bit(const void * const hw)843 static inline void hri_tal_toggle_DMACPUSEL0_CH1_bit(const void *const hw)
844 {
845 TAL_CRITICAL_SECTION_ENTER();
846 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH1_Msk;
847 TAL_CRITICAL_SECTION_LEAVE();
848 }
849
hri_tal_set_DMACPUSEL0_CH2_bit(const void * const hw)850 static inline void hri_tal_set_DMACPUSEL0_CH2_bit(const void *const hw)
851 {
852 TAL_CRITICAL_SECTION_ENTER();
853 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH2_Msk;
854 TAL_CRITICAL_SECTION_LEAVE();
855 }
856
hri_tal_get_DMACPUSEL0_CH2_bit(const void * const hw)857 static inline bool hri_tal_get_DMACPUSEL0_CH2_bit(const void *const hw)
858 {
859 uint32_t tmp;
860 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
861 tmp = (tmp & TAL_DMACPUSEL0_CH2_Msk) >> TAL_DMACPUSEL0_CH2_Pos;
862 return (bool)tmp;
863 }
864
hri_tal_write_DMACPUSEL0_CH2_bit(const void * const hw,bool value)865 static inline void hri_tal_write_DMACPUSEL0_CH2_bit(const void *const hw, bool value)
866 {
867 uint32_t tmp;
868 TAL_CRITICAL_SECTION_ENTER();
869 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
870 tmp &= ~TAL_DMACPUSEL0_CH2_Msk;
871 tmp |= value << TAL_DMACPUSEL0_CH2_Pos;
872 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
873 TAL_CRITICAL_SECTION_LEAVE();
874 }
875
hri_tal_clear_DMACPUSEL0_CH2_bit(const void * const hw)876 static inline void hri_tal_clear_DMACPUSEL0_CH2_bit(const void *const hw)
877 {
878 TAL_CRITICAL_SECTION_ENTER();
879 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH2_Msk;
880 TAL_CRITICAL_SECTION_LEAVE();
881 }
882
hri_tal_toggle_DMACPUSEL0_CH2_bit(const void * const hw)883 static inline void hri_tal_toggle_DMACPUSEL0_CH2_bit(const void *const hw)
884 {
885 TAL_CRITICAL_SECTION_ENTER();
886 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH2_Msk;
887 TAL_CRITICAL_SECTION_LEAVE();
888 }
889
hri_tal_set_DMACPUSEL0_CH3_bit(const void * const hw)890 static inline void hri_tal_set_DMACPUSEL0_CH3_bit(const void *const hw)
891 {
892 TAL_CRITICAL_SECTION_ENTER();
893 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH3_Msk;
894 TAL_CRITICAL_SECTION_LEAVE();
895 }
896
hri_tal_get_DMACPUSEL0_CH3_bit(const void * const hw)897 static inline bool hri_tal_get_DMACPUSEL0_CH3_bit(const void *const hw)
898 {
899 uint32_t tmp;
900 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
901 tmp = (tmp & TAL_DMACPUSEL0_CH3_Msk) >> TAL_DMACPUSEL0_CH3_Pos;
902 return (bool)tmp;
903 }
904
hri_tal_write_DMACPUSEL0_CH3_bit(const void * const hw,bool value)905 static inline void hri_tal_write_DMACPUSEL0_CH3_bit(const void *const hw, bool value)
906 {
907 uint32_t tmp;
908 TAL_CRITICAL_SECTION_ENTER();
909 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
910 tmp &= ~TAL_DMACPUSEL0_CH3_Msk;
911 tmp |= value << TAL_DMACPUSEL0_CH3_Pos;
912 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
913 TAL_CRITICAL_SECTION_LEAVE();
914 }
915
hri_tal_clear_DMACPUSEL0_CH3_bit(const void * const hw)916 static inline void hri_tal_clear_DMACPUSEL0_CH3_bit(const void *const hw)
917 {
918 TAL_CRITICAL_SECTION_ENTER();
919 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH3_Msk;
920 TAL_CRITICAL_SECTION_LEAVE();
921 }
922
hri_tal_toggle_DMACPUSEL0_CH3_bit(const void * const hw)923 static inline void hri_tal_toggle_DMACPUSEL0_CH3_bit(const void *const hw)
924 {
925 TAL_CRITICAL_SECTION_ENTER();
926 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH3_Msk;
927 TAL_CRITICAL_SECTION_LEAVE();
928 }
929
hri_tal_set_DMACPUSEL0_CH4_bit(const void * const hw)930 static inline void hri_tal_set_DMACPUSEL0_CH4_bit(const void *const hw)
931 {
932 TAL_CRITICAL_SECTION_ENTER();
933 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH4_Msk;
934 TAL_CRITICAL_SECTION_LEAVE();
935 }
936
hri_tal_get_DMACPUSEL0_CH4_bit(const void * const hw)937 static inline bool hri_tal_get_DMACPUSEL0_CH4_bit(const void *const hw)
938 {
939 uint32_t tmp;
940 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
941 tmp = (tmp & TAL_DMACPUSEL0_CH4_Msk) >> TAL_DMACPUSEL0_CH4_Pos;
942 return (bool)tmp;
943 }
944
hri_tal_write_DMACPUSEL0_CH4_bit(const void * const hw,bool value)945 static inline void hri_tal_write_DMACPUSEL0_CH4_bit(const void *const hw, bool value)
946 {
947 uint32_t tmp;
948 TAL_CRITICAL_SECTION_ENTER();
949 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
950 tmp &= ~TAL_DMACPUSEL0_CH4_Msk;
951 tmp |= value << TAL_DMACPUSEL0_CH4_Pos;
952 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
953 TAL_CRITICAL_SECTION_LEAVE();
954 }
955
hri_tal_clear_DMACPUSEL0_CH4_bit(const void * const hw)956 static inline void hri_tal_clear_DMACPUSEL0_CH4_bit(const void *const hw)
957 {
958 TAL_CRITICAL_SECTION_ENTER();
959 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH4_Msk;
960 TAL_CRITICAL_SECTION_LEAVE();
961 }
962
hri_tal_toggle_DMACPUSEL0_CH4_bit(const void * const hw)963 static inline void hri_tal_toggle_DMACPUSEL0_CH4_bit(const void *const hw)
964 {
965 TAL_CRITICAL_SECTION_ENTER();
966 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH4_Msk;
967 TAL_CRITICAL_SECTION_LEAVE();
968 }
969
hri_tal_set_DMACPUSEL0_CH5_bit(const void * const hw)970 static inline void hri_tal_set_DMACPUSEL0_CH5_bit(const void *const hw)
971 {
972 TAL_CRITICAL_SECTION_ENTER();
973 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH5_Msk;
974 TAL_CRITICAL_SECTION_LEAVE();
975 }
976
hri_tal_get_DMACPUSEL0_CH5_bit(const void * const hw)977 static inline bool hri_tal_get_DMACPUSEL0_CH5_bit(const void *const hw)
978 {
979 uint32_t tmp;
980 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
981 tmp = (tmp & TAL_DMACPUSEL0_CH5_Msk) >> TAL_DMACPUSEL0_CH5_Pos;
982 return (bool)tmp;
983 }
984
hri_tal_write_DMACPUSEL0_CH5_bit(const void * const hw,bool value)985 static inline void hri_tal_write_DMACPUSEL0_CH5_bit(const void *const hw, bool value)
986 {
987 uint32_t tmp;
988 TAL_CRITICAL_SECTION_ENTER();
989 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
990 tmp &= ~TAL_DMACPUSEL0_CH5_Msk;
991 tmp |= value << TAL_DMACPUSEL0_CH5_Pos;
992 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
993 TAL_CRITICAL_SECTION_LEAVE();
994 }
995
hri_tal_clear_DMACPUSEL0_CH5_bit(const void * const hw)996 static inline void hri_tal_clear_DMACPUSEL0_CH5_bit(const void *const hw)
997 {
998 TAL_CRITICAL_SECTION_ENTER();
999 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH5_Msk;
1000 TAL_CRITICAL_SECTION_LEAVE();
1001 }
1002
hri_tal_toggle_DMACPUSEL0_CH5_bit(const void * const hw)1003 static inline void hri_tal_toggle_DMACPUSEL0_CH5_bit(const void *const hw)
1004 {
1005 TAL_CRITICAL_SECTION_ENTER();
1006 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH5_Msk;
1007 TAL_CRITICAL_SECTION_LEAVE();
1008 }
1009
hri_tal_set_DMACPUSEL0_CH6_bit(const void * const hw)1010 static inline void hri_tal_set_DMACPUSEL0_CH6_bit(const void *const hw)
1011 {
1012 TAL_CRITICAL_SECTION_ENTER();
1013 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH6_Msk;
1014 TAL_CRITICAL_SECTION_LEAVE();
1015 }
1016
hri_tal_get_DMACPUSEL0_CH6_bit(const void * const hw)1017 static inline bool hri_tal_get_DMACPUSEL0_CH6_bit(const void *const hw)
1018 {
1019 uint32_t tmp;
1020 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1021 tmp = (tmp & TAL_DMACPUSEL0_CH6_Msk) >> TAL_DMACPUSEL0_CH6_Pos;
1022 return (bool)tmp;
1023 }
1024
hri_tal_write_DMACPUSEL0_CH6_bit(const void * const hw,bool value)1025 static inline void hri_tal_write_DMACPUSEL0_CH6_bit(const void *const hw, bool value)
1026 {
1027 uint32_t tmp;
1028 TAL_CRITICAL_SECTION_ENTER();
1029 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1030 tmp &= ~TAL_DMACPUSEL0_CH6_Msk;
1031 tmp |= value << TAL_DMACPUSEL0_CH6_Pos;
1032 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
1033 TAL_CRITICAL_SECTION_LEAVE();
1034 }
1035
hri_tal_clear_DMACPUSEL0_CH6_bit(const void * const hw)1036 static inline void hri_tal_clear_DMACPUSEL0_CH6_bit(const void *const hw)
1037 {
1038 TAL_CRITICAL_SECTION_ENTER();
1039 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH6_Msk;
1040 TAL_CRITICAL_SECTION_LEAVE();
1041 }
1042
hri_tal_toggle_DMACPUSEL0_CH6_bit(const void * const hw)1043 static inline void hri_tal_toggle_DMACPUSEL0_CH6_bit(const void *const hw)
1044 {
1045 TAL_CRITICAL_SECTION_ENTER();
1046 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH6_Msk;
1047 TAL_CRITICAL_SECTION_LEAVE();
1048 }
1049
hri_tal_set_DMACPUSEL0_CH7_bit(const void * const hw)1050 static inline void hri_tal_set_DMACPUSEL0_CH7_bit(const void *const hw)
1051 {
1052 TAL_CRITICAL_SECTION_ENTER();
1053 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH7_Msk;
1054 TAL_CRITICAL_SECTION_LEAVE();
1055 }
1056
hri_tal_get_DMACPUSEL0_CH7_bit(const void * const hw)1057 static inline bool hri_tal_get_DMACPUSEL0_CH7_bit(const void *const hw)
1058 {
1059 uint32_t tmp;
1060 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1061 tmp = (tmp & TAL_DMACPUSEL0_CH7_Msk) >> TAL_DMACPUSEL0_CH7_Pos;
1062 return (bool)tmp;
1063 }
1064
hri_tal_write_DMACPUSEL0_CH7_bit(const void * const hw,bool value)1065 static inline void hri_tal_write_DMACPUSEL0_CH7_bit(const void *const hw, bool value)
1066 {
1067 uint32_t tmp;
1068 TAL_CRITICAL_SECTION_ENTER();
1069 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1070 tmp &= ~TAL_DMACPUSEL0_CH7_Msk;
1071 tmp |= value << TAL_DMACPUSEL0_CH7_Pos;
1072 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
1073 TAL_CRITICAL_SECTION_LEAVE();
1074 }
1075
hri_tal_clear_DMACPUSEL0_CH7_bit(const void * const hw)1076 static inline void hri_tal_clear_DMACPUSEL0_CH7_bit(const void *const hw)
1077 {
1078 TAL_CRITICAL_SECTION_ENTER();
1079 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH7_Msk;
1080 TAL_CRITICAL_SECTION_LEAVE();
1081 }
1082
hri_tal_toggle_DMACPUSEL0_CH7_bit(const void * const hw)1083 static inline void hri_tal_toggle_DMACPUSEL0_CH7_bit(const void *const hw)
1084 {
1085 TAL_CRITICAL_SECTION_ENTER();
1086 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH7_Msk;
1087 TAL_CRITICAL_SECTION_LEAVE();
1088 }
1089
hri_tal_set_DMACPUSEL0_CH8_bit(const void * const hw)1090 static inline void hri_tal_set_DMACPUSEL0_CH8_bit(const void *const hw)
1091 {
1092 TAL_CRITICAL_SECTION_ENTER();
1093 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH8_Msk;
1094 TAL_CRITICAL_SECTION_LEAVE();
1095 }
1096
hri_tal_get_DMACPUSEL0_CH8_bit(const void * const hw)1097 static inline bool hri_tal_get_DMACPUSEL0_CH8_bit(const void *const hw)
1098 {
1099 uint32_t tmp;
1100 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1101 tmp = (tmp & TAL_DMACPUSEL0_CH8_Msk) >> TAL_DMACPUSEL0_CH8_Pos;
1102 return (bool)tmp;
1103 }
1104
hri_tal_write_DMACPUSEL0_CH8_bit(const void * const hw,bool value)1105 static inline void hri_tal_write_DMACPUSEL0_CH8_bit(const void *const hw, bool value)
1106 {
1107 uint32_t tmp;
1108 TAL_CRITICAL_SECTION_ENTER();
1109 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1110 tmp &= ~TAL_DMACPUSEL0_CH8_Msk;
1111 tmp |= value << TAL_DMACPUSEL0_CH8_Pos;
1112 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
1113 TAL_CRITICAL_SECTION_LEAVE();
1114 }
1115
hri_tal_clear_DMACPUSEL0_CH8_bit(const void * const hw)1116 static inline void hri_tal_clear_DMACPUSEL0_CH8_bit(const void *const hw)
1117 {
1118 TAL_CRITICAL_SECTION_ENTER();
1119 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH8_Msk;
1120 TAL_CRITICAL_SECTION_LEAVE();
1121 }
1122
hri_tal_toggle_DMACPUSEL0_CH8_bit(const void * const hw)1123 static inline void hri_tal_toggle_DMACPUSEL0_CH8_bit(const void *const hw)
1124 {
1125 TAL_CRITICAL_SECTION_ENTER();
1126 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH8_Msk;
1127 TAL_CRITICAL_SECTION_LEAVE();
1128 }
1129
hri_tal_set_DMACPUSEL0_CH9_bit(const void * const hw)1130 static inline void hri_tal_set_DMACPUSEL0_CH9_bit(const void *const hw)
1131 {
1132 TAL_CRITICAL_SECTION_ENTER();
1133 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH9_Msk;
1134 TAL_CRITICAL_SECTION_LEAVE();
1135 }
1136
hri_tal_get_DMACPUSEL0_CH9_bit(const void * const hw)1137 static inline bool hri_tal_get_DMACPUSEL0_CH9_bit(const void *const hw)
1138 {
1139 uint32_t tmp;
1140 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1141 tmp = (tmp & TAL_DMACPUSEL0_CH9_Msk) >> TAL_DMACPUSEL0_CH9_Pos;
1142 return (bool)tmp;
1143 }
1144
hri_tal_write_DMACPUSEL0_CH9_bit(const void * const hw,bool value)1145 static inline void hri_tal_write_DMACPUSEL0_CH9_bit(const void *const hw, bool value)
1146 {
1147 uint32_t tmp;
1148 TAL_CRITICAL_SECTION_ENTER();
1149 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1150 tmp &= ~TAL_DMACPUSEL0_CH9_Msk;
1151 tmp |= value << TAL_DMACPUSEL0_CH9_Pos;
1152 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
1153 TAL_CRITICAL_SECTION_LEAVE();
1154 }
1155
hri_tal_clear_DMACPUSEL0_CH9_bit(const void * const hw)1156 static inline void hri_tal_clear_DMACPUSEL0_CH9_bit(const void *const hw)
1157 {
1158 TAL_CRITICAL_SECTION_ENTER();
1159 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH9_Msk;
1160 TAL_CRITICAL_SECTION_LEAVE();
1161 }
1162
hri_tal_toggle_DMACPUSEL0_CH9_bit(const void * const hw)1163 static inline void hri_tal_toggle_DMACPUSEL0_CH9_bit(const void *const hw)
1164 {
1165 TAL_CRITICAL_SECTION_ENTER();
1166 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH9_Msk;
1167 TAL_CRITICAL_SECTION_LEAVE();
1168 }
1169
hri_tal_set_DMACPUSEL0_CH10_bit(const void * const hw)1170 static inline void hri_tal_set_DMACPUSEL0_CH10_bit(const void *const hw)
1171 {
1172 TAL_CRITICAL_SECTION_ENTER();
1173 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH10_Msk;
1174 TAL_CRITICAL_SECTION_LEAVE();
1175 }
1176
hri_tal_get_DMACPUSEL0_CH10_bit(const void * const hw)1177 static inline bool hri_tal_get_DMACPUSEL0_CH10_bit(const void *const hw)
1178 {
1179 uint32_t tmp;
1180 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1181 tmp = (tmp & TAL_DMACPUSEL0_CH10_Msk) >> TAL_DMACPUSEL0_CH10_Pos;
1182 return (bool)tmp;
1183 }
1184
hri_tal_write_DMACPUSEL0_CH10_bit(const void * const hw,bool value)1185 static inline void hri_tal_write_DMACPUSEL0_CH10_bit(const void *const hw, bool value)
1186 {
1187 uint32_t tmp;
1188 TAL_CRITICAL_SECTION_ENTER();
1189 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1190 tmp &= ~TAL_DMACPUSEL0_CH10_Msk;
1191 tmp |= value << TAL_DMACPUSEL0_CH10_Pos;
1192 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
1193 TAL_CRITICAL_SECTION_LEAVE();
1194 }
1195
hri_tal_clear_DMACPUSEL0_CH10_bit(const void * const hw)1196 static inline void hri_tal_clear_DMACPUSEL0_CH10_bit(const void *const hw)
1197 {
1198 TAL_CRITICAL_SECTION_ENTER();
1199 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH10_Msk;
1200 TAL_CRITICAL_SECTION_LEAVE();
1201 }
1202
hri_tal_toggle_DMACPUSEL0_CH10_bit(const void * const hw)1203 static inline void hri_tal_toggle_DMACPUSEL0_CH10_bit(const void *const hw)
1204 {
1205 TAL_CRITICAL_SECTION_ENTER();
1206 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH10_Msk;
1207 TAL_CRITICAL_SECTION_LEAVE();
1208 }
1209
hri_tal_set_DMACPUSEL0_CH11_bit(const void * const hw)1210 static inline void hri_tal_set_DMACPUSEL0_CH11_bit(const void *const hw)
1211 {
1212 TAL_CRITICAL_SECTION_ENTER();
1213 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH11_Msk;
1214 TAL_CRITICAL_SECTION_LEAVE();
1215 }
1216
hri_tal_get_DMACPUSEL0_CH11_bit(const void * const hw)1217 static inline bool hri_tal_get_DMACPUSEL0_CH11_bit(const void *const hw)
1218 {
1219 uint32_t tmp;
1220 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1221 tmp = (tmp & TAL_DMACPUSEL0_CH11_Msk) >> TAL_DMACPUSEL0_CH11_Pos;
1222 return (bool)tmp;
1223 }
1224
hri_tal_write_DMACPUSEL0_CH11_bit(const void * const hw,bool value)1225 static inline void hri_tal_write_DMACPUSEL0_CH11_bit(const void *const hw, bool value)
1226 {
1227 uint32_t tmp;
1228 TAL_CRITICAL_SECTION_ENTER();
1229 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1230 tmp &= ~TAL_DMACPUSEL0_CH11_Msk;
1231 tmp |= value << TAL_DMACPUSEL0_CH11_Pos;
1232 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
1233 TAL_CRITICAL_SECTION_LEAVE();
1234 }
1235
hri_tal_clear_DMACPUSEL0_CH11_bit(const void * const hw)1236 static inline void hri_tal_clear_DMACPUSEL0_CH11_bit(const void *const hw)
1237 {
1238 TAL_CRITICAL_SECTION_ENTER();
1239 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH11_Msk;
1240 TAL_CRITICAL_SECTION_LEAVE();
1241 }
1242
hri_tal_toggle_DMACPUSEL0_CH11_bit(const void * const hw)1243 static inline void hri_tal_toggle_DMACPUSEL0_CH11_bit(const void *const hw)
1244 {
1245 TAL_CRITICAL_SECTION_ENTER();
1246 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH11_Msk;
1247 TAL_CRITICAL_SECTION_LEAVE();
1248 }
1249
hri_tal_set_DMACPUSEL0_CH12_bit(const void * const hw)1250 static inline void hri_tal_set_DMACPUSEL0_CH12_bit(const void *const hw)
1251 {
1252 TAL_CRITICAL_SECTION_ENTER();
1253 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH12_Msk;
1254 TAL_CRITICAL_SECTION_LEAVE();
1255 }
1256
hri_tal_get_DMACPUSEL0_CH12_bit(const void * const hw)1257 static inline bool hri_tal_get_DMACPUSEL0_CH12_bit(const void *const hw)
1258 {
1259 uint32_t tmp;
1260 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1261 tmp = (tmp & TAL_DMACPUSEL0_CH12_Msk) >> TAL_DMACPUSEL0_CH12_Pos;
1262 return (bool)tmp;
1263 }
1264
hri_tal_write_DMACPUSEL0_CH12_bit(const void * const hw,bool value)1265 static inline void hri_tal_write_DMACPUSEL0_CH12_bit(const void *const hw, bool value)
1266 {
1267 uint32_t tmp;
1268 TAL_CRITICAL_SECTION_ENTER();
1269 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1270 tmp &= ~TAL_DMACPUSEL0_CH12_Msk;
1271 tmp |= value << TAL_DMACPUSEL0_CH12_Pos;
1272 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
1273 TAL_CRITICAL_SECTION_LEAVE();
1274 }
1275
hri_tal_clear_DMACPUSEL0_CH12_bit(const void * const hw)1276 static inline void hri_tal_clear_DMACPUSEL0_CH12_bit(const void *const hw)
1277 {
1278 TAL_CRITICAL_SECTION_ENTER();
1279 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH12_Msk;
1280 TAL_CRITICAL_SECTION_LEAVE();
1281 }
1282
hri_tal_toggle_DMACPUSEL0_CH12_bit(const void * const hw)1283 static inline void hri_tal_toggle_DMACPUSEL0_CH12_bit(const void *const hw)
1284 {
1285 TAL_CRITICAL_SECTION_ENTER();
1286 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH12_Msk;
1287 TAL_CRITICAL_SECTION_LEAVE();
1288 }
1289
hri_tal_set_DMACPUSEL0_CH13_bit(const void * const hw)1290 static inline void hri_tal_set_DMACPUSEL0_CH13_bit(const void *const hw)
1291 {
1292 TAL_CRITICAL_SECTION_ENTER();
1293 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH13_Msk;
1294 TAL_CRITICAL_SECTION_LEAVE();
1295 }
1296
hri_tal_get_DMACPUSEL0_CH13_bit(const void * const hw)1297 static inline bool hri_tal_get_DMACPUSEL0_CH13_bit(const void *const hw)
1298 {
1299 uint32_t tmp;
1300 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1301 tmp = (tmp & TAL_DMACPUSEL0_CH13_Msk) >> TAL_DMACPUSEL0_CH13_Pos;
1302 return (bool)tmp;
1303 }
1304
hri_tal_write_DMACPUSEL0_CH13_bit(const void * const hw,bool value)1305 static inline void hri_tal_write_DMACPUSEL0_CH13_bit(const void *const hw, bool value)
1306 {
1307 uint32_t tmp;
1308 TAL_CRITICAL_SECTION_ENTER();
1309 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1310 tmp &= ~TAL_DMACPUSEL0_CH13_Msk;
1311 tmp |= value << TAL_DMACPUSEL0_CH13_Pos;
1312 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
1313 TAL_CRITICAL_SECTION_LEAVE();
1314 }
1315
hri_tal_clear_DMACPUSEL0_CH13_bit(const void * const hw)1316 static inline void hri_tal_clear_DMACPUSEL0_CH13_bit(const void *const hw)
1317 {
1318 TAL_CRITICAL_SECTION_ENTER();
1319 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH13_Msk;
1320 TAL_CRITICAL_SECTION_LEAVE();
1321 }
1322
hri_tal_toggle_DMACPUSEL0_CH13_bit(const void * const hw)1323 static inline void hri_tal_toggle_DMACPUSEL0_CH13_bit(const void *const hw)
1324 {
1325 TAL_CRITICAL_SECTION_ENTER();
1326 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH13_Msk;
1327 TAL_CRITICAL_SECTION_LEAVE();
1328 }
1329
hri_tal_set_DMACPUSEL0_CH14_bit(const void * const hw)1330 static inline void hri_tal_set_DMACPUSEL0_CH14_bit(const void *const hw)
1331 {
1332 TAL_CRITICAL_SECTION_ENTER();
1333 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH14_Msk;
1334 TAL_CRITICAL_SECTION_LEAVE();
1335 }
1336
hri_tal_get_DMACPUSEL0_CH14_bit(const void * const hw)1337 static inline bool hri_tal_get_DMACPUSEL0_CH14_bit(const void *const hw)
1338 {
1339 uint32_t tmp;
1340 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1341 tmp = (tmp & TAL_DMACPUSEL0_CH14_Msk) >> TAL_DMACPUSEL0_CH14_Pos;
1342 return (bool)tmp;
1343 }
1344
hri_tal_write_DMACPUSEL0_CH14_bit(const void * const hw,bool value)1345 static inline void hri_tal_write_DMACPUSEL0_CH14_bit(const void *const hw, bool value)
1346 {
1347 uint32_t tmp;
1348 TAL_CRITICAL_SECTION_ENTER();
1349 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1350 tmp &= ~TAL_DMACPUSEL0_CH14_Msk;
1351 tmp |= value << TAL_DMACPUSEL0_CH14_Pos;
1352 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
1353 TAL_CRITICAL_SECTION_LEAVE();
1354 }
1355
hri_tal_clear_DMACPUSEL0_CH14_bit(const void * const hw)1356 static inline void hri_tal_clear_DMACPUSEL0_CH14_bit(const void *const hw)
1357 {
1358 TAL_CRITICAL_SECTION_ENTER();
1359 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH14_Msk;
1360 TAL_CRITICAL_SECTION_LEAVE();
1361 }
1362
hri_tal_toggle_DMACPUSEL0_CH14_bit(const void * const hw)1363 static inline void hri_tal_toggle_DMACPUSEL0_CH14_bit(const void *const hw)
1364 {
1365 TAL_CRITICAL_SECTION_ENTER();
1366 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH14_Msk;
1367 TAL_CRITICAL_SECTION_LEAVE();
1368 }
1369
hri_tal_set_DMACPUSEL0_CH15_bit(const void * const hw)1370 static inline void hri_tal_set_DMACPUSEL0_CH15_bit(const void *const hw)
1371 {
1372 TAL_CRITICAL_SECTION_ENTER();
1373 ((Tal *)hw)->DMACPUSEL0.reg |= TAL_DMACPUSEL0_CH15_Msk;
1374 TAL_CRITICAL_SECTION_LEAVE();
1375 }
1376
hri_tal_get_DMACPUSEL0_CH15_bit(const void * const hw)1377 static inline bool hri_tal_get_DMACPUSEL0_CH15_bit(const void *const hw)
1378 {
1379 uint32_t tmp;
1380 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1381 tmp = (tmp & TAL_DMACPUSEL0_CH15_Msk) >> TAL_DMACPUSEL0_CH15_Pos;
1382 return (bool)tmp;
1383 }
1384
hri_tal_write_DMACPUSEL0_CH15_bit(const void * const hw,bool value)1385 static inline void hri_tal_write_DMACPUSEL0_CH15_bit(const void *const hw, bool value)
1386 {
1387 uint32_t tmp;
1388 TAL_CRITICAL_SECTION_ENTER();
1389 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1390 tmp &= ~TAL_DMACPUSEL0_CH15_Msk;
1391 tmp |= value << TAL_DMACPUSEL0_CH15_Pos;
1392 ((Tal *)hw)->DMACPUSEL0.reg = tmp;
1393 TAL_CRITICAL_SECTION_LEAVE();
1394 }
1395
hri_tal_clear_DMACPUSEL0_CH15_bit(const void * const hw)1396 static inline void hri_tal_clear_DMACPUSEL0_CH15_bit(const void *const hw)
1397 {
1398 TAL_CRITICAL_SECTION_ENTER();
1399 ((Tal *)hw)->DMACPUSEL0.reg &= ~TAL_DMACPUSEL0_CH15_Msk;
1400 TAL_CRITICAL_SECTION_LEAVE();
1401 }
1402
hri_tal_toggle_DMACPUSEL0_CH15_bit(const void * const hw)1403 static inline void hri_tal_toggle_DMACPUSEL0_CH15_bit(const void *const hw)
1404 {
1405 TAL_CRITICAL_SECTION_ENTER();
1406 ((Tal *)hw)->DMACPUSEL0.reg ^= TAL_DMACPUSEL0_CH15_Msk;
1407 TAL_CRITICAL_SECTION_LEAVE();
1408 }
1409
hri_tal_set_DMACPUSEL0_reg(const void * const hw,hri_tal_dmacpusel0_reg_t mask)1410 static inline void hri_tal_set_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask)
1411 {
1412 TAL_CRITICAL_SECTION_ENTER();
1413 ((Tal *)hw)->DMACPUSEL0.reg |= mask;
1414 TAL_CRITICAL_SECTION_LEAVE();
1415 }
1416
hri_tal_get_DMACPUSEL0_reg(const void * const hw,hri_tal_dmacpusel0_reg_t mask)1417 static inline hri_tal_dmacpusel0_reg_t hri_tal_get_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask)
1418 {
1419 uint32_t tmp;
1420 tmp = ((Tal *)hw)->DMACPUSEL0.reg;
1421 tmp &= mask;
1422 return tmp;
1423 }
1424
hri_tal_write_DMACPUSEL0_reg(const void * const hw,hri_tal_dmacpusel0_reg_t data)1425 static inline void hri_tal_write_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t data)
1426 {
1427 TAL_CRITICAL_SECTION_ENTER();
1428 ((Tal *)hw)->DMACPUSEL0.reg = data;
1429 TAL_CRITICAL_SECTION_LEAVE();
1430 }
1431
hri_tal_clear_DMACPUSEL0_reg(const void * const hw,hri_tal_dmacpusel0_reg_t mask)1432 static inline void hri_tal_clear_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask)
1433 {
1434 TAL_CRITICAL_SECTION_ENTER();
1435 ((Tal *)hw)->DMACPUSEL0.reg &= ~mask;
1436 TAL_CRITICAL_SECTION_LEAVE();
1437 }
1438
hri_tal_toggle_DMACPUSEL0_reg(const void * const hw,hri_tal_dmacpusel0_reg_t mask)1439 static inline void hri_tal_toggle_DMACPUSEL0_reg(const void *const hw, hri_tal_dmacpusel0_reg_t mask)
1440 {
1441 TAL_CRITICAL_SECTION_ENTER();
1442 ((Tal *)hw)->DMACPUSEL0.reg ^= mask;
1443 TAL_CRITICAL_SECTION_LEAVE();
1444 }
1445
hri_tal_read_DMACPUSEL0_reg(const void * const hw)1446 static inline hri_tal_dmacpusel0_reg_t hri_tal_read_DMACPUSEL0_reg(const void *const hw)
1447 {
1448 return ((Tal *)hw)->DMACPUSEL0.reg;
1449 }
1450
hri_tal_set_EVCPUSEL0_CH0_bit(const void * const hw)1451 static inline void hri_tal_set_EVCPUSEL0_CH0_bit(const void *const hw)
1452 {
1453 TAL_CRITICAL_SECTION_ENTER();
1454 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH0_Msk;
1455 TAL_CRITICAL_SECTION_LEAVE();
1456 }
1457
hri_tal_get_EVCPUSEL0_CH0_bit(const void * const hw)1458 static inline bool hri_tal_get_EVCPUSEL0_CH0_bit(const void *const hw)
1459 {
1460 uint32_t tmp;
1461 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1462 tmp = (tmp & TAL_EVCPUSEL0_CH0_Msk) >> TAL_EVCPUSEL0_CH0_Pos;
1463 return (bool)tmp;
1464 }
1465
hri_tal_write_EVCPUSEL0_CH0_bit(const void * const hw,bool value)1466 static inline void hri_tal_write_EVCPUSEL0_CH0_bit(const void *const hw, bool value)
1467 {
1468 uint32_t tmp;
1469 TAL_CRITICAL_SECTION_ENTER();
1470 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1471 tmp &= ~TAL_EVCPUSEL0_CH0_Msk;
1472 tmp |= value << TAL_EVCPUSEL0_CH0_Pos;
1473 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1474 TAL_CRITICAL_SECTION_LEAVE();
1475 }
1476
hri_tal_clear_EVCPUSEL0_CH0_bit(const void * const hw)1477 static inline void hri_tal_clear_EVCPUSEL0_CH0_bit(const void *const hw)
1478 {
1479 TAL_CRITICAL_SECTION_ENTER();
1480 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH0_Msk;
1481 TAL_CRITICAL_SECTION_LEAVE();
1482 }
1483
hri_tal_toggle_EVCPUSEL0_CH0_bit(const void * const hw)1484 static inline void hri_tal_toggle_EVCPUSEL0_CH0_bit(const void *const hw)
1485 {
1486 TAL_CRITICAL_SECTION_ENTER();
1487 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH0_Msk;
1488 TAL_CRITICAL_SECTION_LEAVE();
1489 }
1490
hri_tal_set_EVCPUSEL0_CH1_bit(const void * const hw)1491 static inline void hri_tal_set_EVCPUSEL0_CH1_bit(const void *const hw)
1492 {
1493 TAL_CRITICAL_SECTION_ENTER();
1494 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH1_Msk;
1495 TAL_CRITICAL_SECTION_LEAVE();
1496 }
1497
hri_tal_get_EVCPUSEL0_CH1_bit(const void * const hw)1498 static inline bool hri_tal_get_EVCPUSEL0_CH1_bit(const void *const hw)
1499 {
1500 uint32_t tmp;
1501 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1502 tmp = (tmp & TAL_EVCPUSEL0_CH1_Msk) >> TAL_EVCPUSEL0_CH1_Pos;
1503 return (bool)tmp;
1504 }
1505
hri_tal_write_EVCPUSEL0_CH1_bit(const void * const hw,bool value)1506 static inline void hri_tal_write_EVCPUSEL0_CH1_bit(const void *const hw, bool value)
1507 {
1508 uint32_t tmp;
1509 TAL_CRITICAL_SECTION_ENTER();
1510 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1511 tmp &= ~TAL_EVCPUSEL0_CH1_Msk;
1512 tmp |= value << TAL_EVCPUSEL0_CH1_Pos;
1513 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1514 TAL_CRITICAL_SECTION_LEAVE();
1515 }
1516
hri_tal_clear_EVCPUSEL0_CH1_bit(const void * const hw)1517 static inline void hri_tal_clear_EVCPUSEL0_CH1_bit(const void *const hw)
1518 {
1519 TAL_CRITICAL_SECTION_ENTER();
1520 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH1_Msk;
1521 TAL_CRITICAL_SECTION_LEAVE();
1522 }
1523
hri_tal_toggle_EVCPUSEL0_CH1_bit(const void * const hw)1524 static inline void hri_tal_toggle_EVCPUSEL0_CH1_bit(const void *const hw)
1525 {
1526 TAL_CRITICAL_SECTION_ENTER();
1527 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH1_Msk;
1528 TAL_CRITICAL_SECTION_LEAVE();
1529 }
1530
hri_tal_set_EVCPUSEL0_CH2_bit(const void * const hw)1531 static inline void hri_tal_set_EVCPUSEL0_CH2_bit(const void *const hw)
1532 {
1533 TAL_CRITICAL_SECTION_ENTER();
1534 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH2_Msk;
1535 TAL_CRITICAL_SECTION_LEAVE();
1536 }
1537
hri_tal_get_EVCPUSEL0_CH2_bit(const void * const hw)1538 static inline bool hri_tal_get_EVCPUSEL0_CH2_bit(const void *const hw)
1539 {
1540 uint32_t tmp;
1541 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1542 tmp = (tmp & TAL_EVCPUSEL0_CH2_Msk) >> TAL_EVCPUSEL0_CH2_Pos;
1543 return (bool)tmp;
1544 }
1545
hri_tal_write_EVCPUSEL0_CH2_bit(const void * const hw,bool value)1546 static inline void hri_tal_write_EVCPUSEL0_CH2_bit(const void *const hw, bool value)
1547 {
1548 uint32_t tmp;
1549 TAL_CRITICAL_SECTION_ENTER();
1550 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1551 tmp &= ~TAL_EVCPUSEL0_CH2_Msk;
1552 tmp |= value << TAL_EVCPUSEL0_CH2_Pos;
1553 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1554 TAL_CRITICAL_SECTION_LEAVE();
1555 }
1556
hri_tal_clear_EVCPUSEL0_CH2_bit(const void * const hw)1557 static inline void hri_tal_clear_EVCPUSEL0_CH2_bit(const void *const hw)
1558 {
1559 TAL_CRITICAL_SECTION_ENTER();
1560 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH2_Msk;
1561 TAL_CRITICAL_SECTION_LEAVE();
1562 }
1563
hri_tal_toggle_EVCPUSEL0_CH2_bit(const void * const hw)1564 static inline void hri_tal_toggle_EVCPUSEL0_CH2_bit(const void *const hw)
1565 {
1566 TAL_CRITICAL_SECTION_ENTER();
1567 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH2_Msk;
1568 TAL_CRITICAL_SECTION_LEAVE();
1569 }
1570
hri_tal_set_EVCPUSEL0_CH3_bit(const void * const hw)1571 static inline void hri_tal_set_EVCPUSEL0_CH3_bit(const void *const hw)
1572 {
1573 TAL_CRITICAL_SECTION_ENTER();
1574 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH3_Msk;
1575 TAL_CRITICAL_SECTION_LEAVE();
1576 }
1577
hri_tal_get_EVCPUSEL0_CH3_bit(const void * const hw)1578 static inline bool hri_tal_get_EVCPUSEL0_CH3_bit(const void *const hw)
1579 {
1580 uint32_t tmp;
1581 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1582 tmp = (tmp & TAL_EVCPUSEL0_CH3_Msk) >> TAL_EVCPUSEL0_CH3_Pos;
1583 return (bool)tmp;
1584 }
1585
hri_tal_write_EVCPUSEL0_CH3_bit(const void * const hw,bool value)1586 static inline void hri_tal_write_EVCPUSEL0_CH3_bit(const void *const hw, bool value)
1587 {
1588 uint32_t tmp;
1589 TAL_CRITICAL_SECTION_ENTER();
1590 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1591 tmp &= ~TAL_EVCPUSEL0_CH3_Msk;
1592 tmp |= value << TAL_EVCPUSEL0_CH3_Pos;
1593 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1594 TAL_CRITICAL_SECTION_LEAVE();
1595 }
1596
hri_tal_clear_EVCPUSEL0_CH3_bit(const void * const hw)1597 static inline void hri_tal_clear_EVCPUSEL0_CH3_bit(const void *const hw)
1598 {
1599 TAL_CRITICAL_SECTION_ENTER();
1600 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH3_Msk;
1601 TAL_CRITICAL_SECTION_LEAVE();
1602 }
1603
hri_tal_toggle_EVCPUSEL0_CH3_bit(const void * const hw)1604 static inline void hri_tal_toggle_EVCPUSEL0_CH3_bit(const void *const hw)
1605 {
1606 TAL_CRITICAL_SECTION_ENTER();
1607 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH3_Msk;
1608 TAL_CRITICAL_SECTION_LEAVE();
1609 }
1610
hri_tal_set_EVCPUSEL0_CH4_bit(const void * const hw)1611 static inline void hri_tal_set_EVCPUSEL0_CH4_bit(const void *const hw)
1612 {
1613 TAL_CRITICAL_SECTION_ENTER();
1614 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH4_Msk;
1615 TAL_CRITICAL_SECTION_LEAVE();
1616 }
1617
hri_tal_get_EVCPUSEL0_CH4_bit(const void * const hw)1618 static inline bool hri_tal_get_EVCPUSEL0_CH4_bit(const void *const hw)
1619 {
1620 uint32_t tmp;
1621 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1622 tmp = (tmp & TAL_EVCPUSEL0_CH4_Msk) >> TAL_EVCPUSEL0_CH4_Pos;
1623 return (bool)tmp;
1624 }
1625
hri_tal_write_EVCPUSEL0_CH4_bit(const void * const hw,bool value)1626 static inline void hri_tal_write_EVCPUSEL0_CH4_bit(const void *const hw, bool value)
1627 {
1628 uint32_t tmp;
1629 TAL_CRITICAL_SECTION_ENTER();
1630 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1631 tmp &= ~TAL_EVCPUSEL0_CH4_Msk;
1632 tmp |= value << TAL_EVCPUSEL0_CH4_Pos;
1633 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1634 TAL_CRITICAL_SECTION_LEAVE();
1635 }
1636
hri_tal_clear_EVCPUSEL0_CH4_bit(const void * const hw)1637 static inline void hri_tal_clear_EVCPUSEL0_CH4_bit(const void *const hw)
1638 {
1639 TAL_CRITICAL_SECTION_ENTER();
1640 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH4_Msk;
1641 TAL_CRITICAL_SECTION_LEAVE();
1642 }
1643
hri_tal_toggle_EVCPUSEL0_CH4_bit(const void * const hw)1644 static inline void hri_tal_toggle_EVCPUSEL0_CH4_bit(const void *const hw)
1645 {
1646 TAL_CRITICAL_SECTION_ENTER();
1647 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH4_Msk;
1648 TAL_CRITICAL_SECTION_LEAVE();
1649 }
1650
hri_tal_set_EVCPUSEL0_CH5_bit(const void * const hw)1651 static inline void hri_tal_set_EVCPUSEL0_CH5_bit(const void *const hw)
1652 {
1653 TAL_CRITICAL_SECTION_ENTER();
1654 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH5_Msk;
1655 TAL_CRITICAL_SECTION_LEAVE();
1656 }
1657
hri_tal_get_EVCPUSEL0_CH5_bit(const void * const hw)1658 static inline bool hri_tal_get_EVCPUSEL0_CH5_bit(const void *const hw)
1659 {
1660 uint32_t tmp;
1661 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1662 tmp = (tmp & TAL_EVCPUSEL0_CH5_Msk) >> TAL_EVCPUSEL0_CH5_Pos;
1663 return (bool)tmp;
1664 }
1665
hri_tal_write_EVCPUSEL0_CH5_bit(const void * const hw,bool value)1666 static inline void hri_tal_write_EVCPUSEL0_CH5_bit(const void *const hw, bool value)
1667 {
1668 uint32_t tmp;
1669 TAL_CRITICAL_SECTION_ENTER();
1670 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1671 tmp &= ~TAL_EVCPUSEL0_CH5_Msk;
1672 tmp |= value << TAL_EVCPUSEL0_CH5_Pos;
1673 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1674 TAL_CRITICAL_SECTION_LEAVE();
1675 }
1676
hri_tal_clear_EVCPUSEL0_CH5_bit(const void * const hw)1677 static inline void hri_tal_clear_EVCPUSEL0_CH5_bit(const void *const hw)
1678 {
1679 TAL_CRITICAL_SECTION_ENTER();
1680 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH5_Msk;
1681 TAL_CRITICAL_SECTION_LEAVE();
1682 }
1683
hri_tal_toggle_EVCPUSEL0_CH5_bit(const void * const hw)1684 static inline void hri_tal_toggle_EVCPUSEL0_CH5_bit(const void *const hw)
1685 {
1686 TAL_CRITICAL_SECTION_ENTER();
1687 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH5_Msk;
1688 TAL_CRITICAL_SECTION_LEAVE();
1689 }
1690
hri_tal_set_EVCPUSEL0_CH6_bit(const void * const hw)1691 static inline void hri_tal_set_EVCPUSEL0_CH6_bit(const void *const hw)
1692 {
1693 TAL_CRITICAL_SECTION_ENTER();
1694 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH6_Msk;
1695 TAL_CRITICAL_SECTION_LEAVE();
1696 }
1697
hri_tal_get_EVCPUSEL0_CH6_bit(const void * const hw)1698 static inline bool hri_tal_get_EVCPUSEL0_CH6_bit(const void *const hw)
1699 {
1700 uint32_t tmp;
1701 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1702 tmp = (tmp & TAL_EVCPUSEL0_CH6_Msk) >> TAL_EVCPUSEL0_CH6_Pos;
1703 return (bool)tmp;
1704 }
1705
hri_tal_write_EVCPUSEL0_CH6_bit(const void * const hw,bool value)1706 static inline void hri_tal_write_EVCPUSEL0_CH6_bit(const void *const hw, bool value)
1707 {
1708 uint32_t tmp;
1709 TAL_CRITICAL_SECTION_ENTER();
1710 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1711 tmp &= ~TAL_EVCPUSEL0_CH6_Msk;
1712 tmp |= value << TAL_EVCPUSEL0_CH6_Pos;
1713 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1714 TAL_CRITICAL_SECTION_LEAVE();
1715 }
1716
hri_tal_clear_EVCPUSEL0_CH6_bit(const void * const hw)1717 static inline void hri_tal_clear_EVCPUSEL0_CH6_bit(const void *const hw)
1718 {
1719 TAL_CRITICAL_SECTION_ENTER();
1720 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH6_Msk;
1721 TAL_CRITICAL_SECTION_LEAVE();
1722 }
1723
hri_tal_toggle_EVCPUSEL0_CH6_bit(const void * const hw)1724 static inline void hri_tal_toggle_EVCPUSEL0_CH6_bit(const void *const hw)
1725 {
1726 TAL_CRITICAL_SECTION_ENTER();
1727 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH6_Msk;
1728 TAL_CRITICAL_SECTION_LEAVE();
1729 }
1730
hri_tal_set_EVCPUSEL0_CH7_bit(const void * const hw)1731 static inline void hri_tal_set_EVCPUSEL0_CH7_bit(const void *const hw)
1732 {
1733 TAL_CRITICAL_SECTION_ENTER();
1734 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH7_Msk;
1735 TAL_CRITICAL_SECTION_LEAVE();
1736 }
1737
hri_tal_get_EVCPUSEL0_CH7_bit(const void * const hw)1738 static inline bool hri_tal_get_EVCPUSEL0_CH7_bit(const void *const hw)
1739 {
1740 uint32_t tmp;
1741 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1742 tmp = (tmp & TAL_EVCPUSEL0_CH7_Msk) >> TAL_EVCPUSEL0_CH7_Pos;
1743 return (bool)tmp;
1744 }
1745
hri_tal_write_EVCPUSEL0_CH7_bit(const void * const hw,bool value)1746 static inline void hri_tal_write_EVCPUSEL0_CH7_bit(const void *const hw, bool value)
1747 {
1748 uint32_t tmp;
1749 TAL_CRITICAL_SECTION_ENTER();
1750 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1751 tmp &= ~TAL_EVCPUSEL0_CH7_Msk;
1752 tmp |= value << TAL_EVCPUSEL0_CH7_Pos;
1753 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1754 TAL_CRITICAL_SECTION_LEAVE();
1755 }
1756
hri_tal_clear_EVCPUSEL0_CH7_bit(const void * const hw)1757 static inline void hri_tal_clear_EVCPUSEL0_CH7_bit(const void *const hw)
1758 {
1759 TAL_CRITICAL_SECTION_ENTER();
1760 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH7_Msk;
1761 TAL_CRITICAL_SECTION_LEAVE();
1762 }
1763
hri_tal_toggle_EVCPUSEL0_CH7_bit(const void * const hw)1764 static inline void hri_tal_toggle_EVCPUSEL0_CH7_bit(const void *const hw)
1765 {
1766 TAL_CRITICAL_SECTION_ENTER();
1767 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH7_Msk;
1768 TAL_CRITICAL_SECTION_LEAVE();
1769 }
1770
hri_tal_set_EVCPUSEL0_CH8_bit(const void * const hw)1771 static inline void hri_tal_set_EVCPUSEL0_CH8_bit(const void *const hw)
1772 {
1773 TAL_CRITICAL_SECTION_ENTER();
1774 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH8_Msk;
1775 TAL_CRITICAL_SECTION_LEAVE();
1776 }
1777
hri_tal_get_EVCPUSEL0_CH8_bit(const void * const hw)1778 static inline bool hri_tal_get_EVCPUSEL0_CH8_bit(const void *const hw)
1779 {
1780 uint32_t tmp;
1781 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1782 tmp = (tmp & TAL_EVCPUSEL0_CH8_Msk) >> TAL_EVCPUSEL0_CH8_Pos;
1783 return (bool)tmp;
1784 }
1785
hri_tal_write_EVCPUSEL0_CH8_bit(const void * const hw,bool value)1786 static inline void hri_tal_write_EVCPUSEL0_CH8_bit(const void *const hw, bool value)
1787 {
1788 uint32_t tmp;
1789 TAL_CRITICAL_SECTION_ENTER();
1790 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1791 tmp &= ~TAL_EVCPUSEL0_CH8_Msk;
1792 tmp |= value << TAL_EVCPUSEL0_CH8_Pos;
1793 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1794 TAL_CRITICAL_SECTION_LEAVE();
1795 }
1796
hri_tal_clear_EVCPUSEL0_CH8_bit(const void * const hw)1797 static inline void hri_tal_clear_EVCPUSEL0_CH8_bit(const void *const hw)
1798 {
1799 TAL_CRITICAL_SECTION_ENTER();
1800 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH8_Msk;
1801 TAL_CRITICAL_SECTION_LEAVE();
1802 }
1803
hri_tal_toggle_EVCPUSEL0_CH8_bit(const void * const hw)1804 static inline void hri_tal_toggle_EVCPUSEL0_CH8_bit(const void *const hw)
1805 {
1806 TAL_CRITICAL_SECTION_ENTER();
1807 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH8_Msk;
1808 TAL_CRITICAL_SECTION_LEAVE();
1809 }
1810
hri_tal_set_EVCPUSEL0_CH9_bit(const void * const hw)1811 static inline void hri_tal_set_EVCPUSEL0_CH9_bit(const void *const hw)
1812 {
1813 TAL_CRITICAL_SECTION_ENTER();
1814 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH9_Msk;
1815 TAL_CRITICAL_SECTION_LEAVE();
1816 }
1817
hri_tal_get_EVCPUSEL0_CH9_bit(const void * const hw)1818 static inline bool hri_tal_get_EVCPUSEL0_CH9_bit(const void *const hw)
1819 {
1820 uint32_t tmp;
1821 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1822 tmp = (tmp & TAL_EVCPUSEL0_CH9_Msk) >> TAL_EVCPUSEL0_CH9_Pos;
1823 return (bool)tmp;
1824 }
1825
hri_tal_write_EVCPUSEL0_CH9_bit(const void * const hw,bool value)1826 static inline void hri_tal_write_EVCPUSEL0_CH9_bit(const void *const hw, bool value)
1827 {
1828 uint32_t tmp;
1829 TAL_CRITICAL_SECTION_ENTER();
1830 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1831 tmp &= ~TAL_EVCPUSEL0_CH9_Msk;
1832 tmp |= value << TAL_EVCPUSEL0_CH9_Pos;
1833 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1834 TAL_CRITICAL_SECTION_LEAVE();
1835 }
1836
hri_tal_clear_EVCPUSEL0_CH9_bit(const void * const hw)1837 static inline void hri_tal_clear_EVCPUSEL0_CH9_bit(const void *const hw)
1838 {
1839 TAL_CRITICAL_SECTION_ENTER();
1840 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH9_Msk;
1841 TAL_CRITICAL_SECTION_LEAVE();
1842 }
1843
hri_tal_toggle_EVCPUSEL0_CH9_bit(const void * const hw)1844 static inline void hri_tal_toggle_EVCPUSEL0_CH9_bit(const void *const hw)
1845 {
1846 TAL_CRITICAL_SECTION_ENTER();
1847 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH9_Msk;
1848 TAL_CRITICAL_SECTION_LEAVE();
1849 }
1850
hri_tal_set_EVCPUSEL0_CH10_bit(const void * const hw)1851 static inline void hri_tal_set_EVCPUSEL0_CH10_bit(const void *const hw)
1852 {
1853 TAL_CRITICAL_SECTION_ENTER();
1854 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH10_Msk;
1855 TAL_CRITICAL_SECTION_LEAVE();
1856 }
1857
hri_tal_get_EVCPUSEL0_CH10_bit(const void * const hw)1858 static inline bool hri_tal_get_EVCPUSEL0_CH10_bit(const void *const hw)
1859 {
1860 uint32_t tmp;
1861 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1862 tmp = (tmp & TAL_EVCPUSEL0_CH10_Msk) >> TAL_EVCPUSEL0_CH10_Pos;
1863 return (bool)tmp;
1864 }
1865
hri_tal_write_EVCPUSEL0_CH10_bit(const void * const hw,bool value)1866 static inline void hri_tal_write_EVCPUSEL0_CH10_bit(const void *const hw, bool value)
1867 {
1868 uint32_t tmp;
1869 TAL_CRITICAL_SECTION_ENTER();
1870 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1871 tmp &= ~TAL_EVCPUSEL0_CH10_Msk;
1872 tmp |= value << TAL_EVCPUSEL0_CH10_Pos;
1873 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1874 TAL_CRITICAL_SECTION_LEAVE();
1875 }
1876
hri_tal_clear_EVCPUSEL0_CH10_bit(const void * const hw)1877 static inline void hri_tal_clear_EVCPUSEL0_CH10_bit(const void *const hw)
1878 {
1879 TAL_CRITICAL_SECTION_ENTER();
1880 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH10_Msk;
1881 TAL_CRITICAL_SECTION_LEAVE();
1882 }
1883
hri_tal_toggle_EVCPUSEL0_CH10_bit(const void * const hw)1884 static inline void hri_tal_toggle_EVCPUSEL0_CH10_bit(const void *const hw)
1885 {
1886 TAL_CRITICAL_SECTION_ENTER();
1887 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH10_Msk;
1888 TAL_CRITICAL_SECTION_LEAVE();
1889 }
1890
hri_tal_set_EVCPUSEL0_CH11_bit(const void * const hw)1891 static inline void hri_tal_set_EVCPUSEL0_CH11_bit(const void *const hw)
1892 {
1893 TAL_CRITICAL_SECTION_ENTER();
1894 ((Tal *)hw)->EVCPUSEL0.reg |= TAL_EVCPUSEL0_CH11_Msk;
1895 TAL_CRITICAL_SECTION_LEAVE();
1896 }
1897
hri_tal_get_EVCPUSEL0_CH11_bit(const void * const hw)1898 static inline bool hri_tal_get_EVCPUSEL0_CH11_bit(const void *const hw)
1899 {
1900 uint32_t tmp;
1901 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1902 tmp = (tmp & TAL_EVCPUSEL0_CH11_Msk) >> TAL_EVCPUSEL0_CH11_Pos;
1903 return (bool)tmp;
1904 }
1905
hri_tal_write_EVCPUSEL0_CH11_bit(const void * const hw,bool value)1906 static inline void hri_tal_write_EVCPUSEL0_CH11_bit(const void *const hw, bool value)
1907 {
1908 uint32_t tmp;
1909 TAL_CRITICAL_SECTION_ENTER();
1910 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1911 tmp &= ~TAL_EVCPUSEL0_CH11_Msk;
1912 tmp |= value << TAL_EVCPUSEL0_CH11_Pos;
1913 ((Tal *)hw)->EVCPUSEL0.reg = tmp;
1914 TAL_CRITICAL_SECTION_LEAVE();
1915 }
1916
hri_tal_clear_EVCPUSEL0_CH11_bit(const void * const hw)1917 static inline void hri_tal_clear_EVCPUSEL0_CH11_bit(const void *const hw)
1918 {
1919 TAL_CRITICAL_SECTION_ENTER();
1920 ((Tal *)hw)->EVCPUSEL0.reg &= ~TAL_EVCPUSEL0_CH11_Msk;
1921 TAL_CRITICAL_SECTION_LEAVE();
1922 }
1923
hri_tal_toggle_EVCPUSEL0_CH11_bit(const void * const hw)1924 static inline void hri_tal_toggle_EVCPUSEL0_CH11_bit(const void *const hw)
1925 {
1926 TAL_CRITICAL_SECTION_ENTER();
1927 ((Tal *)hw)->EVCPUSEL0.reg ^= TAL_EVCPUSEL0_CH11_Msk;
1928 TAL_CRITICAL_SECTION_LEAVE();
1929 }
1930
hri_tal_set_EVCPUSEL0_reg(const void * const hw,hri_tal_evcpusel0_reg_t mask)1931 static inline void hri_tal_set_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask)
1932 {
1933 TAL_CRITICAL_SECTION_ENTER();
1934 ((Tal *)hw)->EVCPUSEL0.reg |= mask;
1935 TAL_CRITICAL_SECTION_LEAVE();
1936 }
1937
hri_tal_get_EVCPUSEL0_reg(const void * const hw,hri_tal_evcpusel0_reg_t mask)1938 static inline hri_tal_evcpusel0_reg_t hri_tal_get_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask)
1939 {
1940 uint32_t tmp;
1941 tmp = ((Tal *)hw)->EVCPUSEL0.reg;
1942 tmp &= mask;
1943 return tmp;
1944 }
1945
hri_tal_write_EVCPUSEL0_reg(const void * const hw,hri_tal_evcpusel0_reg_t data)1946 static inline void hri_tal_write_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t data)
1947 {
1948 TAL_CRITICAL_SECTION_ENTER();
1949 ((Tal *)hw)->EVCPUSEL0.reg = data;
1950 TAL_CRITICAL_SECTION_LEAVE();
1951 }
1952
hri_tal_clear_EVCPUSEL0_reg(const void * const hw,hri_tal_evcpusel0_reg_t mask)1953 static inline void hri_tal_clear_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask)
1954 {
1955 TAL_CRITICAL_SECTION_ENTER();
1956 ((Tal *)hw)->EVCPUSEL0.reg &= ~mask;
1957 TAL_CRITICAL_SECTION_LEAVE();
1958 }
1959
hri_tal_toggle_EVCPUSEL0_reg(const void * const hw,hri_tal_evcpusel0_reg_t mask)1960 static inline void hri_tal_toggle_EVCPUSEL0_reg(const void *const hw, hri_tal_evcpusel0_reg_t mask)
1961 {
1962 TAL_CRITICAL_SECTION_ENTER();
1963 ((Tal *)hw)->EVCPUSEL0.reg ^= mask;
1964 TAL_CRITICAL_SECTION_LEAVE();
1965 }
1966
hri_tal_read_EVCPUSEL0_reg(const void * const hw)1967 static inline hri_tal_evcpusel0_reg_t hri_tal_read_EVCPUSEL0_reg(const void *const hw)
1968 {
1969 return ((Tal *)hw)->EVCPUSEL0.reg;
1970 }
1971
hri_tal_set_EICCPUSEL0_EXTINT0_bit(const void * const hw)1972 static inline void hri_tal_set_EICCPUSEL0_EXTINT0_bit(const void *const hw)
1973 {
1974 TAL_CRITICAL_SECTION_ENTER();
1975 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT0_Msk;
1976 TAL_CRITICAL_SECTION_LEAVE();
1977 }
1978
hri_tal_get_EICCPUSEL0_EXTINT0_bit(const void * const hw)1979 static inline bool hri_tal_get_EICCPUSEL0_EXTINT0_bit(const void *const hw)
1980 {
1981 uint32_t tmp;
1982 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
1983 tmp = (tmp & TAL_EICCPUSEL0_EXTINT0_Msk) >> TAL_EICCPUSEL0_EXTINT0_Pos;
1984 return (bool)tmp;
1985 }
1986
hri_tal_write_EICCPUSEL0_EXTINT0_bit(const void * const hw,bool value)1987 static inline void hri_tal_write_EICCPUSEL0_EXTINT0_bit(const void *const hw, bool value)
1988 {
1989 uint32_t tmp;
1990 TAL_CRITICAL_SECTION_ENTER();
1991 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
1992 tmp &= ~TAL_EICCPUSEL0_EXTINT0_Msk;
1993 tmp |= value << TAL_EICCPUSEL0_EXTINT0_Pos;
1994 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
1995 TAL_CRITICAL_SECTION_LEAVE();
1996 }
1997
hri_tal_clear_EICCPUSEL0_EXTINT0_bit(const void * const hw)1998 static inline void hri_tal_clear_EICCPUSEL0_EXTINT0_bit(const void *const hw)
1999 {
2000 TAL_CRITICAL_SECTION_ENTER();
2001 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT0_Msk;
2002 TAL_CRITICAL_SECTION_LEAVE();
2003 }
2004
hri_tal_toggle_EICCPUSEL0_EXTINT0_bit(const void * const hw)2005 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT0_bit(const void *const hw)
2006 {
2007 TAL_CRITICAL_SECTION_ENTER();
2008 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT0_Msk;
2009 TAL_CRITICAL_SECTION_LEAVE();
2010 }
2011
hri_tal_set_EICCPUSEL0_EXTINT1_bit(const void * const hw)2012 static inline void hri_tal_set_EICCPUSEL0_EXTINT1_bit(const void *const hw)
2013 {
2014 TAL_CRITICAL_SECTION_ENTER();
2015 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT1_Msk;
2016 TAL_CRITICAL_SECTION_LEAVE();
2017 }
2018
hri_tal_get_EICCPUSEL0_EXTINT1_bit(const void * const hw)2019 static inline bool hri_tal_get_EICCPUSEL0_EXTINT1_bit(const void *const hw)
2020 {
2021 uint32_t tmp;
2022 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2023 tmp = (tmp & TAL_EICCPUSEL0_EXTINT1_Msk) >> TAL_EICCPUSEL0_EXTINT1_Pos;
2024 return (bool)tmp;
2025 }
2026
hri_tal_write_EICCPUSEL0_EXTINT1_bit(const void * const hw,bool value)2027 static inline void hri_tal_write_EICCPUSEL0_EXTINT1_bit(const void *const hw, bool value)
2028 {
2029 uint32_t tmp;
2030 TAL_CRITICAL_SECTION_ENTER();
2031 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2032 tmp &= ~TAL_EICCPUSEL0_EXTINT1_Msk;
2033 tmp |= value << TAL_EICCPUSEL0_EXTINT1_Pos;
2034 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2035 TAL_CRITICAL_SECTION_LEAVE();
2036 }
2037
hri_tal_clear_EICCPUSEL0_EXTINT1_bit(const void * const hw)2038 static inline void hri_tal_clear_EICCPUSEL0_EXTINT1_bit(const void *const hw)
2039 {
2040 TAL_CRITICAL_SECTION_ENTER();
2041 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT1_Msk;
2042 TAL_CRITICAL_SECTION_LEAVE();
2043 }
2044
hri_tal_toggle_EICCPUSEL0_EXTINT1_bit(const void * const hw)2045 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT1_bit(const void *const hw)
2046 {
2047 TAL_CRITICAL_SECTION_ENTER();
2048 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT1_Msk;
2049 TAL_CRITICAL_SECTION_LEAVE();
2050 }
2051
hri_tal_set_EICCPUSEL0_EXTINT2_bit(const void * const hw)2052 static inline void hri_tal_set_EICCPUSEL0_EXTINT2_bit(const void *const hw)
2053 {
2054 TAL_CRITICAL_SECTION_ENTER();
2055 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT2_Msk;
2056 TAL_CRITICAL_SECTION_LEAVE();
2057 }
2058
hri_tal_get_EICCPUSEL0_EXTINT2_bit(const void * const hw)2059 static inline bool hri_tal_get_EICCPUSEL0_EXTINT2_bit(const void *const hw)
2060 {
2061 uint32_t tmp;
2062 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2063 tmp = (tmp & TAL_EICCPUSEL0_EXTINT2_Msk) >> TAL_EICCPUSEL0_EXTINT2_Pos;
2064 return (bool)tmp;
2065 }
2066
hri_tal_write_EICCPUSEL0_EXTINT2_bit(const void * const hw,bool value)2067 static inline void hri_tal_write_EICCPUSEL0_EXTINT2_bit(const void *const hw, bool value)
2068 {
2069 uint32_t tmp;
2070 TAL_CRITICAL_SECTION_ENTER();
2071 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2072 tmp &= ~TAL_EICCPUSEL0_EXTINT2_Msk;
2073 tmp |= value << TAL_EICCPUSEL0_EXTINT2_Pos;
2074 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2075 TAL_CRITICAL_SECTION_LEAVE();
2076 }
2077
hri_tal_clear_EICCPUSEL0_EXTINT2_bit(const void * const hw)2078 static inline void hri_tal_clear_EICCPUSEL0_EXTINT2_bit(const void *const hw)
2079 {
2080 TAL_CRITICAL_SECTION_ENTER();
2081 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT2_Msk;
2082 TAL_CRITICAL_SECTION_LEAVE();
2083 }
2084
hri_tal_toggle_EICCPUSEL0_EXTINT2_bit(const void * const hw)2085 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT2_bit(const void *const hw)
2086 {
2087 TAL_CRITICAL_SECTION_ENTER();
2088 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT2_Msk;
2089 TAL_CRITICAL_SECTION_LEAVE();
2090 }
2091
hri_tal_set_EICCPUSEL0_EXTINT3_bit(const void * const hw)2092 static inline void hri_tal_set_EICCPUSEL0_EXTINT3_bit(const void *const hw)
2093 {
2094 TAL_CRITICAL_SECTION_ENTER();
2095 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT3_Msk;
2096 TAL_CRITICAL_SECTION_LEAVE();
2097 }
2098
hri_tal_get_EICCPUSEL0_EXTINT3_bit(const void * const hw)2099 static inline bool hri_tal_get_EICCPUSEL0_EXTINT3_bit(const void *const hw)
2100 {
2101 uint32_t tmp;
2102 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2103 tmp = (tmp & TAL_EICCPUSEL0_EXTINT3_Msk) >> TAL_EICCPUSEL0_EXTINT3_Pos;
2104 return (bool)tmp;
2105 }
2106
hri_tal_write_EICCPUSEL0_EXTINT3_bit(const void * const hw,bool value)2107 static inline void hri_tal_write_EICCPUSEL0_EXTINT3_bit(const void *const hw, bool value)
2108 {
2109 uint32_t tmp;
2110 TAL_CRITICAL_SECTION_ENTER();
2111 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2112 tmp &= ~TAL_EICCPUSEL0_EXTINT3_Msk;
2113 tmp |= value << TAL_EICCPUSEL0_EXTINT3_Pos;
2114 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2115 TAL_CRITICAL_SECTION_LEAVE();
2116 }
2117
hri_tal_clear_EICCPUSEL0_EXTINT3_bit(const void * const hw)2118 static inline void hri_tal_clear_EICCPUSEL0_EXTINT3_bit(const void *const hw)
2119 {
2120 TAL_CRITICAL_SECTION_ENTER();
2121 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT3_Msk;
2122 TAL_CRITICAL_SECTION_LEAVE();
2123 }
2124
hri_tal_toggle_EICCPUSEL0_EXTINT3_bit(const void * const hw)2125 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT3_bit(const void *const hw)
2126 {
2127 TAL_CRITICAL_SECTION_ENTER();
2128 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT3_Msk;
2129 TAL_CRITICAL_SECTION_LEAVE();
2130 }
2131
hri_tal_set_EICCPUSEL0_EXTINT4_bit(const void * const hw)2132 static inline void hri_tal_set_EICCPUSEL0_EXTINT4_bit(const void *const hw)
2133 {
2134 TAL_CRITICAL_SECTION_ENTER();
2135 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT4_Msk;
2136 TAL_CRITICAL_SECTION_LEAVE();
2137 }
2138
hri_tal_get_EICCPUSEL0_EXTINT4_bit(const void * const hw)2139 static inline bool hri_tal_get_EICCPUSEL0_EXTINT4_bit(const void *const hw)
2140 {
2141 uint32_t tmp;
2142 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2143 tmp = (tmp & TAL_EICCPUSEL0_EXTINT4_Msk) >> TAL_EICCPUSEL0_EXTINT4_Pos;
2144 return (bool)tmp;
2145 }
2146
hri_tal_write_EICCPUSEL0_EXTINT4_bit(const void * const hw,bool value)2147 static inline void hri_tal_write_EICCPUSEL0_EXTINT4_bit(const void *const hw, bool value)
2148 {
2149 uint32_t tmp;
2150 TAL_CRITICAL_SECTION_ENTER();
2151 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2152 tmp &= ~TAL_EICCPUSEL0_EXTINT4_Msk;
2153 tmp |= value << TAL_EICCPUSEL0_EXTINT4_Pos;
2154 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2155 TAL_CRITICAL_SECTION_LEAVE();
2156 }
2157
hri_tal_clear_EICCPUSEL0_EXTINT4_bit(const void * const hw)2158 static inline void hri_tal_clear_EICCPUSEL0_EXTINT4_bit(const void *const hw)
2159 {
2160 TAL_CRITICAL_SECTION_ENTER();
2161 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT4_Msk;
2162 TAL_CRITICAL_SECTION_LEAVE();
2163 }
2164
hri_tal_toggle_EICCPUSEL0_EXTINT4_bit(const void * const hw)2165 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT4_bit(const void *const hw)
2166 {
2167 TAL_CRITICAL_SECTION_ENTER();
2168 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT4_Msk;
2169 TAL_CRITICAL_SECTION_LEAVE();
2170 }
2171
hri_tal_set_EICCPUSEL0_EXTINT5_bit(const void * const hw)2172 static inline void hri_tal_set_EICCPUSEL0_EXTINT5_bit(const void *const hw)
2173 {
2174 TAL_CRITICAL_SECTION_ENTER();
2175 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT5_Msk;
2176 TAL_CRITICAL_SECTION_LEAVE();
2177 }
2178
hri_tal_get_EICCPUSEL0_EXTINT5_bit(const void * const hw)2179 static inline bool hri_tal_get_EICCPUSEL0_EXTINT5_bit(const void *const hw)
2180 {
2181 uint32_t tmp;
2182 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2183 tmp = (tmp & TAL_EICCPUSEL0_EXTINT5_Msk) >> TAL_EICCPUSEL0_EXTINT5_Pos;
2184 return (bool)tmp;
2185 }
2186
hri_tal_write_EICCPUSEL0_EXTINT5_bit(const void * const hw,bool value)2187 static inline void hri_tal_write_EICCPUSEL0_EXTINT5_bit(const void *const hw, bool value)
2188 {
2189 uint32_t tmp;
2190 TAL_CRITICAL_SECTION_ENTER();
2191 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2192 tmp &= ~TAL_EICCPUSEL0_EXTINT5_Msk;
2193 tmp |= value << TAL_EICCPUSEL0_EXTINT5_Pos;
2194 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2195 TAL_CRITICAL_SECTION_LEAVE();
2196 }
2197
hri_tal_clear_EICCPUSEL0_EXTINT5_bit(const void * const hw)2198 static inline void hri_tal_clear_EICCPUSEL0_EXTINT5_bit(const void *const hw)
2199 {
2200 TAL_CRITICAL_SECTION_ENTER();
2201 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT5_Msk;
2202 TAL_CRITICAL_SECTION_LEAVE();
2203 }
2204
hri_tal_toggle_EICCPUSEL0_EXTINT5_bit(const void * const hw)2205 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT5_bit(const void *const hw)
2206 {
2207 TAL_CRITICAL_SECTION_ENTER();
2208 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT5_Msk;
2209 TAL_CRITICAL_SECTION_LEAVE();
2210 }
2211
hri_tal_set_EICCPUSEL0_EXTINT6_bit(const void * const hw)2212 static inline void hri_tal_set_EICCPUSEL0_EXTINT6_bit(const void *const hw)
2213 {
2214 TAL_CRITICAL_SECTION_ENTER();
2215 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT6_Msk;
2216 TAL_CRITICAL_SECTION_LEAVE();
2217 }
2218
hri_tal_get_EICCPUSEL0_EXTINT6_bit(const void * const hw)2219 static inline bool hri_tal_get_EICCPUSEL0_EXTINT6_bit(const void *const hw)
2220 {
2221 uint32_t tmp;
2222 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2223 tmp = (tmp & TAL_EICCPUSEL0_EXTINT6_Msk) >> TAL_EICCPUSEL0_EXTINT6_Pos;
2224 return (bool)tmp;
2225 }
2226
hri_tal_write_EICCPUSEL0_EXTINT6_bit(const void * const hw,bool value)2227 static inline void hri_tal_write_EICCPUSEL0_EXTINT6_bit(const void *const hw, bool value)
2228 {
2229 uint32_t tmp;
2230 TAL_CRITICAL_SECTION_ENTER();
2231 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2232 tmp &= ~TAL_EICCPUSEL0_EXTINT6_Msk;
2233 tmp |= value << TAL_EICCPUSEL0_EXTINT6_Pos;
2234 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2235 TAL_CRITICAL_SECTION_LEAVE();
2236 }
2237
hri_tal_clear_EICCPUSEL0_EXTINT6_bit(const void * const hw)2238 static inline void hri_tal_clear_EICCPUSEL0_EXTINT6_bit(const void *const hw)
2239 {
2240 TAL_CRITICAL_SECTION_ENTER();
2241 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT6_Msk;
2242 TAL_CRITICAL_SECTION_LEAVE();
2243 }
2244
hri_tal_toggle_EICCPUSEL0_EXTINT6_bit(const void * const hw)2245 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT6_bit(const void *const hw)
2246 {
2247 TAL_CRITICAL_SECTION_ENTER();
2248 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT6_Msk;
2249 TAL_CRITICAL_SECTION_LEAVE();
2250 }
2251
hri_tal_set_EICCPUSEL0_EXTINT7_bit(const void * const hw)2252 static inline void hri_tal_set_EICCPUSEL0_EXTINT7_bit(const void *const hw)
2253 {
2254 TAL_CRITICAL_SECTION_ENTER();
2255 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT7_Msk;
2256 TAL_CRITICAL_SECTION_LEAVE();
2257 }
2258
hri_tal_get_EICCPUSEL0_EXTINT7_bit(const void * const hw)2259 static inline bool hri_tal_get_EICCPUSEL0_EXTINT7_bit(const void *const hw)
2260 {
2261 uint32_t tmp;
2262 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2263 tmp = (tmp & TAL_EICCPUSEL0_EXTINT7_Msk) >> TAL_EICCPUSEL0_EXTINT7_Pos;
2264 return (bool)tmp;
2265 }
2266
hri_tal_write_EICCPUSEL0_EXTINT7_bit(const void * const hw,bool value)2267 static inline void hri_tal_write_EICCPUSEL0_EXTINT7_bit(const void *const hw, bool value)
2268 {
2269 uint32_t tmp;
2270 TAL_CRITICAL_SECTION_ENTER();
2271 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2272 tmp &= ~TAL_EICCPUSEL0_EXTINT7_Msk;
2273 tmp |= value << TAL_EICCPUSEL0_EXTINT7_Pos;
2274 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2275 TAL_CRITICAL_SECTION_LEAVE();
2276 }
2277
hri_tal_clear_EICCPUSEL0_EXTINT7_bit(const void * const hw)2278 static inline void hri_tal_clear_EICCPUSEL0_EXTINT7_bit(const void *const hw)
2279 {
2280 TAL_CRITICAL_SECTION_ENTER();
2281 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT7_Msk;
2282 TAL_CRITICAL_SECTION_LEAVE();
2283 }
2284
hri_tal_toggle_EICCPUSEL0_EXTINT7_bit(const void * const hw)2285 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT7_bit(const void *const hw)
2286 {
2287 TAL_CRITICAL_SECTION_ENTER();
2288 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT7_Msk;
2289 TAL_CRITICAL_SECTION_LEAVE();
2290 }
2291
hri_tal_set_EICCPUSEL0_EXTINT8_bit(const void * const hw)2292 static inline void hri_tal_set_EICCPUSEL0_EXTINT8_bit(const void *const hw)
2293 {
2294 TAL_CRITICAL_SECTION_ENTER();
2295 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT8_Msk;
2296 TAL_CRITICAL_SECTION_LEAVE();
2297 }
2298
hri_tal_get_EICCPUSEL0_EXTINT8_bit(const void * const hw)2299 static inline bool hri_tal_get_EICCPUSEL0_EXTINT8_bit(const void *const hw)
2300 {
2301 uint32_t tmp;
2302 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2303 tmp = (tmp & TAL_EICCPUSEL0_EXTINT8_Msk) >> TAL_EICCPUSEL0_EXTINT8_Pos;
2304 return (bool)tmp;
2305 }
2306
hri_tal_write_EICCPUSEL0_EXTINT8_bit(const void * const hw,bool value)2307 static inline void hri_tal_write_EICCPUSEL0_EXTINT8_bit(const void *const hw, bool value)
2308 {
2309 uint32_t tmp;
2310 TAL_CRITICAL_SECTION_ENTER();
2311 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2312 tmp &= ~TAL_EICCPUSEL0_EXTINT8_Msk;
2313 tmp |= value << TAL_EICCPUSEL0_EXTINT8_Pos;
2314 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2315 TAL_CRITICAL_SECTION_LEAVE();
2316 }
2317
hri_tal_clear_EICCPUSEL0_EXTINT8_bit(const void * const hw)2318 static inline void hri_tal_clear_EICCPUSEL0_EXTINT8_bit(const void *const hw)
2319 {
2320 TAL_CRITICAL_SECTION_ENTER();
2321 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT8_Msk;
2322 TAL_CRITICAL_SECTION_LEAVE();
2323 }
2324
hri_tal_toggle_EICCPUSEL0_EXTINT8_bit(const void * const hw)2325 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT8_bit(const void *const hw)
2326 {
2327 TAL_CRITICAL_SECTION_ENTER();
2328 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT8_Msk;
2329 TAL_CRITICAL_SECTION_LEAVE();
2330 }
2331
hri_tal_set_EICCPUSEL0_EXTINT9_bit(const void * const hw)2332 static inline void hri_tal_set_EICCPUSEL0_EXTINT9_bit(const void *const hw)
2333 {
2334 TAL_CRITICAL_SECTION_ENTER();
2335 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT9_Msk;
2336 TAL_CRITICAL_SECTION_LEAVE();
2337 }
2338
hri_tal_get_EICCPUSEL0_EXTINT9_bit(const void * const hw)2339 static inline bool hri_tal_get_EICCPUSEL0_EXTINT9_bit(const void *const hw)
2340 {
2341 uint32_t tmp;
2342 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2343 tmp = (tmp & TAL_EICCPUSEL0_EXTINT9_Msk) >> TAL_EICCPUSEL0_EXTINT9_Pos;
2344 return (bool)tmp;
2345 }
2346
hri_tal_write_EICCPUSEL0_EXTINT9_bit(const void * const hw,bool value)2347 static inline void hri_tal_write_EICCPUSEL0_EXTINT9_bit(const void *const hw, bool value)
2348 {
2349 uint32_t tmp;
2350 TAL_CRITICAL_SECTION_ENTER();
2351 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2352 tmp &= ~TAL_EICCPUSEL0_EXTINT9_Msk;
2353 tmp |= value << TAL_EICCPUSEL0_EXTINT9_Pos;
2354 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2355 TAL_CRITICAL_SECTION_LEAVE();
2356 }
2357
hri_tal_clear_EICCPUSEL0_EXTINT9_bit(const void * const hw)2358 static inline void hri_tal_clear_EICCPUSEL0_EXTINT9_bit(const void *const hw)
2359 {
2360 TAL_CRITICAL_SECTION_ENTER();
2361 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT9_Msk;
2362 TAL_CRITICAL_SECTION_LEAVE();
2363 }
2364
hri_tal_toggle_EICCPUSEL0_EXTINT9_bit(const void * const hw)2365 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT9_bit(const void *const hw)
2366 {
2367 TAL_CRITICAL_SECTION_ENTER();
2368 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT9_Msk;
2369 TAL_CRITICAL_SECTION_LEAVE();
2370 }
2371
hri_tal_set_EICCPUSEL0_EXTINT10_bit(const void * const hw)2372 static inline void hri_tal_set_EICCPUSEL0_EXTINT10_bit(const void *const hw)
2373 {
2374 TAL_CRITICAL_SECTION_ENTER();
2375 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT10_Msk;
2376 TAL_CRITICAL_SECTION_LEAVE();
2377 }
2378
hri_tal_get_EICCPUSEL0_EXTINT10_bit(const void * const hw)2379 static inline bool hri_tal_get_EICCPUSEL0_EXTINT10_bit(const void *const hw)
2380 {
2381 uint32_t tmp;
2382 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2383 tmp = (tmp & TAL_EICCPUSEL0_EXTINT10_Msk) >> TAL_EICCPUSEL0_EXTINT10_Pos;
2384 return (bool)tmp;
2385 }
2386
hri_tal_write_EICCPUSEL0_EXTINT10_bit(const void * const hw,bool value)2387 static inline void hri_tal_write_EICCPUSEL0_EXTINT10_bit(const void *const hw, bool value)
2388 {
2389 uint32_t tmp;
2390 TAL_CRITICAL_SECTION_ENTER();
2391 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2392 tmp &= ~TAL_EICCPUSEL0_EXTINT10_Msk;
2393 tmp |= value << TAL_EICCPUSEL0_EXTINT10_Pos;
2394 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2395 TAL_CRITICAL_SECTION_LEAVE();
2396 }
2397
hri_tal_clear_EICCPUSEL0_EXTINT10_bit(const void * const hw)2398 static inline void hri_tal_clear_EICCPUSEL0_EXTINT10_bit(const void *const hw)
2399 {
2400 TAL_CRITICAL_SECTION_ENTER();
2401 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT10_Msk;
2402 TAL_CRITICAL_SECTION_LEAVE();
2403 }
2404
hri_tal_toggle_EICCPUSEL0_EXTINT10_bit(const void * const hw)2405 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT10_bit(const void *const hw)
2406 {
2407 TAL_CRITICAL_SECTION_ENTER();
2408 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT10_Msk;
2409 TAL_CRITICAL_SECTION_LEAVE();
2410 }
2411
hri_tal_set_EICCPUSEL0_EXTINT11_bit(const void * const hw)2412 static inline void hri_tal_set_EICCPUSEL0_EXTINT11_bit(const void *const hw)
2413 {
2414 TAL_CRITICAL_SECTION_ENTER();
2415 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT11_Msk;
2416 TAL_CRITICAL_SECTION_LEAVE();
2417 }
2418
hri_tal_get_EICCPUSEL0_EXTINT11_bit(const void * const hw)2419 static inline bool hri_tal_get_EICCPUSEL0_EXTINT11_bit(const void *const hw)
2420 {
2421 uint32_t tmp;
2422 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2423 tmp = (tmp & TAL_EICCPUSEL0_EXTINT11_Msk) >> TAL_EICCPUSEL0_EXTINT11_Pos;
2424 return (bool)tmp;
2425 }
2426
hri_tal_write_EICCPUSEL0_EXTINT11_bit(const void * const hw,bool value)2427 static inline void hri_tal_write_EICCPUSEL0_EXTINT11_bit(const void *const hw, bool value)
2428 {
2429 uint32_t tmp;
2430 TAL_CRITICAL_SECTION_ENTER();
2431 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2432 tmp &= ~TAL_EICCPUSEL0_EXTINT11_Msk;
2433 tmp |= value << TAL_EICCPUSEL0_EXTINT11_Pos;
2434 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2435 TAL_CRITICAL_SECTION_LEAVE();
2436 }
2437
hri_tal_clear_EICCPUSEL0_EXTINT11_bit(const void * const hw)2438 static inline void hri_tal_clear_EICCPUSEL0_EXTINT11_bit(const void *const hw)
2439 {
2440 TAL_CRITICAL_SECTION_ENTER();
2441 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT11_Msk;
2442 TAL_CRITICAL_SECTION_LEAVE();
2443 }
2444
hri_tal_toggle_EICCPUSEL0_EXTINT11_bit(const void * const hw)2445 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT11_bit(const void *const hw)
2446 {
2447 TAL_CRITICAL_SECTION_ENTER();
2448 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT11_Msk;
2449 TAL_CRITICAL_SECTION_LEAVE();
2450 }
2451
hri_tal_set_EICCPUSEL0_EXTINT12_bit(const void * const hw)2452 static inline void hri_tal_set_EICCPUSEL0_EXTINT12_bit(const void *const hw)
2453 {
2454 TAL_CRITICAL_SECTION_ENTER();
2455 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT12_Msk;
2456 TAL_CRITICAL_SECTION_LEAVE();
2457 }
2458
hri_tal_get_EICCPUSEL0_EXTINT12_bit(const void * const hw)2459 static inline bool hri_tal_get_EICCPUSEL0_EXTINT12_bit(const void *const hw)
2460 {
2461 uint32_t tmp;
2462 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2463 tmp = (tmp & TAL_EICCPUSEL0_EXTINT12_Msk) >> TAL_EICCPUSEL0_EXTINT12_Pos;
2464 return (bool)tmp;
2465 }
2466
hri_tal_write_EICCPUSEL0_EXTINT12_bit(const void * const hw,bool value)2467 static inline void hri_tal_write_EICCPUSEL0_EXTINT12_bit(const void *const hw, bool value)
2468 {
2469 uint32_t tmp;
2470 TAL_CRITICAL_SECTION_ENTER();
2471 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2472 tmp &= ~TAL_EICCPUSEL0_EXTINT12_Msk;
2473 tmp |= value << TAL_EICCPUSEL0_EXTINT12_Pos;
2474 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2475 TAL_CRITICAL_SECTION_LEAVE();
2476 }
2477
hri_tal_clear_EICCPUSEL0_EXTINT12_bit(const void * const hw)2478 static inline void hri_tal_clear_EICCPUSEL0_EXTINT12_bit(const void *const hw)
2479 {
2480 TAL_CRITICAL_SECTION_ENTER();
2481 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT12_Msk;
2482 TAL_CRITICAL_SECTION_LEAVE();
2483 }
2484
hri_tal_toggle_EICCPUSEL0_EXTINT12_bit(const void * const hw)2485 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT12_bit(const void *const hw)
2486 {
2487 TAL_CRITICAL_SECTION_ENTER();
2488 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT12_Msk;
2489 TAL_CRITICAL_SECTION_LEAVE();
2490 }
2491
hri_tal_set_EICCPUSEL0_EXTINT13_bit(const void * const hw)2492 static inline void hri_tal_set_EICCPUSEL0_EXTINT13_bit(const void *const hw)
2493 {
2494 TAL_CRITICAL_SECTION_ENTER();
2495 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT13_Msk;
2496 TAL_CRITICAL_SECTION_LEAVE();
2497 }
2498
hri_tal_get_EICCPUSEL0_EXTINT13_bit(const void * const hw)2499 static inline bool hri_tal_get_EICCPUSEL0_EXTINT13_bit(const void *const hw)
2500 {
2501 uint32_t tmp;
2502 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2503 tmp = (tmp & TAL_EICCPUSEL0_EXTINT13_Msk) >> TAL_EICCPUSEL0_EXTINT13_Pos;
2504 return (bool)tmp;
2505 }
2506
hri_tal_write_EICCPUSEL0_EXTINT13_bit(const void * const hw,bool value)2507 static inline void hri_tal_write_EICCPUSEL0_EXTINT13_bit(const void *const hw, bool value)
2508 {
2509 uint32_t tmp;
2510 TAL_CRITICAL_SECTION_ENTER();
2511 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2512 tmp &= ~TAL_EICCPUSEL0_EXTINT13_Msk;
2513 tmp |= value << TAL_EICCPUSEL0_EXTINT13_Pos;
2514 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2515 TAL_CRITICAL_SECTION_LEAVE();
2516 }
2517
hri_tal_clear_EICCPUSEL0_EXTINT13_bit(const void * const hw)2518 static inline void hri_tal_clear_EICCPUSEL0_EXTINT13_bit(const void *const hw)
2519 {
2520 TAL_CRITICAL_SECTION_ENTER();
2521 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT13_Msk;
2522 TAL_CRITICAL_SECTION_LEAVE();
2523 }
2524
hri_tal_toggle_EICCPUSEL0_EXTINT13_bit(const void * const hw)2525 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT13_bit(const void *const hw)
2526 {
2527 TAL_CRITICAL_SECTION_ENTER();
2528 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT13_Msk;
2529 TAL_CRITICAL_SECTION_LEAVE();
2530 }
2531
hri_tal_set_EICCPUSEL0_EXTINT14_bit(const void * const hw)2532 static inline void hri_tal_set_EICCPUSEL0_EXTINT14_bit(const void *const hw)
2533 {
2534 TAL_CRITICAL_SECTION_ENTER();
2535 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT14_Msk;
2536 TAL_CRITICAL_SECTION_LEAVE();
2537 }
2538
hri_tal_get_EICCPUSEL0_EXTINT14_bit(const void * const hw)2539 static inline bool hri_tal_get_EICCPUSEL0_EXTINT14_bit(const void *const hw)
2540 {
2541 uint32_t tmp;
2542 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2543 tmp = (tmp & TAL_EICCPUSEL0_EXTINT14_Msk) >> TAL_EICCPUSEL0_EXTINT14_Pos;
2544 return (bool)tmp;
2545 }
2546
hri_tal_write_EICCPUSEL0_EXTINT14_bit(const void * const hw,bool value)2547 static inline void hri_tal_write_EICCPUSEL0_EXTINT14_bit(const void *const hw, bool value)
2548 {
2549 uint32_t tmp;
2550 TAL_CRITICAL_SECTION_ENTER();
2551 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2552 tmp &= ~TAL_EICCPUSEL0_EXTINT14_Msk;
2553 tmp |= value << TAL_EICCPUSEL0_EXTINT14_Pos;
2554 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2555 TAL_CRITICAL_SECTION_LEAVE();
2556 }
2557
hri_tal_clear_EICCPUSEL0_EXTINT14_bit(const void * const hw)2558 static inline void hri_tal_clear_EICCPUSEL0_EXTINT14_bit(const void *const hw)
2559 {
2560 TAL_CRITICAL_SECTION_ENTER();
2561 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT14_Msk;
2562 TAL_CRITICAL_SECTION_LEAVE();
2563 }
2564
hri_tal_toggle_EICCPUSEL0_EXTINT14_bit(const void * const hw)2565 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT14_bit(const void *const hw)
2566 {
2567 TAL_CRITICAL_SECTION_ENTER();
2568 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT14_Msk;
2569 TAL_CRITICAL_SECTION_LEAVE();
2570 }
2571
hri_tal_set_EICCPUSEL0_EXTINT15_bit(const void * const hw)2572 static inline void hri_tal_set_EICCPUSEL0_EXTINT15_bit(const void *const hw)
2573 {
2574 TAL_CRITICAL_SECTION_ENTER();
2575 ((Tal *)hw)->EICCPUSEL0.reg |= TAL_EICCPUSEL0_EXTINT15_Msk;
2576 TAL_CRITICAL_SECTION_LEAVE();
2577 }
2578
hri_tal_get_EICCPUSEL0_EXTINT15_bit(const void * const hw)2579 static inline bool hri_tal_get_EICCPUSEL0_EXTINT15_bit(const void *const hw)
2580 {
2581 uint32_t tmp;
2582 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2583 tmp = (tmp & TAL_EICCPUSEL0_EXTINT15_Msk) >> TAL_EICCPUSEL0_EXTINT15_Pos;
2584 return (bool)tmp;
2585 }
2586
hri_tal_write_EICCPUSEL0_EXTINT15_bit(const void * const hw,bool value)2587 static inline void hri_tal_write_EICCPUSEL0_EXTINT15_bit(const void *const hw, bool value)
2588 {
2589 uint32_t tmp;
2590 TAL_CRITICAL_SECTION_ENTER();
2591 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2592 tmp &= ~TAL_EICCPUSEL0_EXTINT15_Msk;
2593 tmp |= value << TAL_EICCPUSEL0_EXTINT15_Pos;
2594 ((Tal *)hw)->EICCPUSEL0.reg = tmp;
2595 TAL_CRITICAL_SECTION_LEAVE();
2596 }
2597
hri_tal_clear_EICCPUSEL0_EXTINT15_bit(const void * const hw)2598 static inline void hri_tal_clear_EICCPUSEL0_EXTINT15_bit(const void *const hw)
2599 {
2600 TAL_CRITICAL_SECTION_ENTER();
2601 ((Tal *)hw)->EICCPUSEL0.reg &= ~TAL_EICCPUSEL0_EXTINT15_Msk;
2602 TAL_CRITICAL_SECTION_LEAVE();
2603 }
2604
hri_tal_toggle_EICCPUSEL0_EXTINT15_bit(const void * const hw)2605 static inline void hri_tal_toggle_EICCPUSEL0_EXTINT15_bit(const void *const hw)
2606 {
2607 TAL_CRITICAL_SECTION_ENTER();
2608 ((Tal *)hw)->EICCPUSEL0.reg ^= TAL_EICCPUSEL0_EXTINT15_Msk;
2609 TAL_CRITICAL_SECTION_LEAVE();
2610 }
2611
hri_tal_set_EICCPUSEL0_reg(const void * const hw,hri_tal_eiccpusel0_reg_t mask)2612 static inline void hri_tal_set_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask)
2613 {
2614 TAL_CRITICAL_SECTION_ENTER();
2615 ((Tal *)hw)->EICCPUSEL0.reg |= mask;
2616 TAL_CRITICAL_SECTION_LEAVE();
2617 }
2618
hri_tal_get_EICCPUSEL0_reg(const void * const hw,hri_tal_eiccpusel0_reg_t mask)2619 static inline hri_tal_eiccpusel0_reg_t hri_tal_get_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask)
2620 {
2621 uint32_t tmp;
2622 tmp = ((Tal *)hw)->EICCPUSEL0.reg;
2623 tmp &= mask;
2624 return tmp;
2625 }
2626
hri_tal_write_EICCPUSEL0_reg(const void * const hw,hri_tal_eiccpusel0_reg_t data)2627 static inline void hri_tal_write_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t data)
2628 {
2629 TAL_CRITICAL_SECTION_ENTER();
2630 ((Tal *)hw)->EICCPUSEL0.reg = data;
2631 TAL_CRITICAL_SECTION_LEAVE();
2632 }
2633
hri_tal_clear_EICCPUSEL0_reg(const void * const hw,hri_tal_eiccpusel0_reg_t mask)2634 static inline void hri_tal_clear_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask)
2635 {
2636 TAL_CRITICAL_SECTION_ENTER();
2637 ((Tal *)hw)->EICCPUSEL0.reg &= ~mask;
2638 TAL_CRITICAL_SECTION_LEAVE();
2639 }
2640
hri_tal_toggle_EICCPUSEL0_reg(const void * const hw,hri_tal_eiccpusel0_reg_t mask)2641 static inline void hri_tal_toggle_EICCPUSEL0_reg(const void *const hw, hri_tal_eiccpusel0_reg_t mask)
2642 {
2643 TAL_CRITICAL_SECTION_ENTER();
2644 ((Tal *)hw)->EICCPUSEL0.reg ^= mask;
2645 TAL_CRITICAL_SECTION_LEAVE();
2646 }
2647
hri_tal_read_EICCPUSEL0_reg(const void * const hw)2648 static inline hri_tal_eiccpusel0_reg_t hri_tal_read_EICCPUSEL0_reg(const void *const hw)
2649 {
2650 return ((Tal *)hw)->EICCPUSEL0.reg;
2651 }
2652
hri_tal_set_INTCPUSEL0_SYSTEM_bit(const void * const hw)2653 static inline void hri_tal_set_INTCPUSEL0_SYSTEM_bit(const void *const hw)
2654 {
2655 TAL_CRITICAL_SECTION_ENTER();
2656 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SYSTEM_Msk;
2657 TAL_CRITICAL_SECTION_LEAVE();
2658 }
2659
hri_tal_get_INTCPUSEL0_SYSTEM_bit(const void * const hw)2660 static inline bool hri_tal_get_INTCPUSEL0_SYSTEM_bit(const void *const hw)
2661 {
2662 uint32_t tmp;
2663 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2664 tmp = (tmp & TAL_INTCPUSEL0_SYSTEM_Msk) >> TAL_INTCPUSEL0_SYSTEM_Pos;
2665 return (bool)tmp;
2666 }
2667
hri_tal_write_INTCPUSEL0_SYSTEM_bit(const void * const hw,bool value)2668 static inline void hri_tal_write_INTCPUSEL0_SYSTEM_bit(const void *const hw, bool value)
2669 {
2670 uint32_t tmp;
2671 TAL_CRITICAL_SECTION_ENTER();
2672 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2673 tmp &= ~TAL_INTCPUSEL0_SYSTEM_Msk;
2674 tmp |= value << TAL_INTCPUSEL0_SYSTEM_Pos;
2675 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
2676 TAL_CRITICAL_SECTION_LEAVE();
2677 }
2678
hri_tal_clear_INTCPUSEL0_SYSTEM_bit(const void * const hw)2679 static inline void hri_tal_clear_INTCPUSEL0_SYSTEM_bit(const void *const hw)
2680 {
2681 TAL_CRITICAL_SECTION_ENTER();
2682 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SYSTEM_Msk;
2683 TAL_CRITICAL_SECTION_LEAVE();
2684 }
2685
hri_tal_toggle_INTCPUSEL0_SYSTEM_bit(const void * const hw)2686 static inline void hri_tal_toggle_INTCPUSEL0_SYSTEM_bit(const void *const hw)
2687 {
2688 TAL_CRITICAL_SECTION_ENTER();
2689 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SYSTEM_Msk;
2690 TAL_CRITICAL_SECTION_LEAVE();
2691 }
2692
hri_tal_set_INTCPUSEL0_WDT_bit(const void * const hw)2693 static inline void hri_tal_set_INTCPUSEL0_WDT_bit(const void *const hw)
2694 {
2695 TAL_CRITICAL_SECTION_ENTER();
2696 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_WDT_Msk;
2697 TAL_CRITICAL_SECTION_LEAVE();
2698 }
2699
hri_tal_get_INTCPUSEL0_WDT_bit(const void * const hw)2700 static inline bool hri_tal_get_INTCPUSEL0_WDT_bit(const void *const hw)
2701 {
2702 uint32_t tmp;
2703 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2704 tmp = (tmp & TAL_INTCPUSEL0_WDT_Msk) >> TAL_INTCPUSEL0_WDT_Pos;
2705 return (bool)tmp;
2706 }
2707
hri_tal_write_INTCPUSEL0_WDT_bit(const void * const hw,bool value)2708 static inline void hri_tal_write_INTCPUSEL0_WDT_bit(const void *const hw, bool value)
2709 {
2710 uint32_t tmp;
2711 TAL_CRITICAL_SECTION_ENTER();
2712 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2713 tmp &= ~TAL_INTCPUSEL0_WDT_Msk;
2714 tmp |= value << TAL_INTCPUSEL0_WDT_Pos;
2715 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
2716 TAL_CRITICAL_SECTION_LEAVE();
2717 }
2718
hri_tal_clear_INTCPUSEL0_WDT_bit(const void * const hw)2719 static inline void hri_tal_clear_INTCPUSEL0_WDT_bit(const void *const hw)
2720 {
2721 TAL_CRITICAL_SECTION_ENTER();
2722 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_WDT_Msk;
2723 TAL_CRITICAL_SECTION_LEAVE();
2724 }
2725
hri_tal_toggle_INTCPUSEL0_WDT_bit(const void * const hw)2726 static inline void hri_tal_toggle_INTCPUSEL0_WDT_bit(const void *const hw)
2727 {
2728 TAL_CRITICAL_SECTION_ENTER();
2729 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_WDT_Msk;
2730 TAL_CRITICAL_SECTION_LEAVE();
2731 }
2732
hri_tal_set_INTCPUSEL0_RTC_bit(const void * const hw)2733 static inline void hri_tal_set_INTCPUSEL0_RTC_bit(const void *const hw)
2734 {
2735 TAL_CRITICAL_SECTION_ENTER();
2736 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_RTC_Msk;
2737 TAL_CRITICAL_SECTION_LEAVE();
2738 }
2739
hri_tal_get_INTCPUSEL0_RTC_bit(const void * const hw)2740 static inline bool hri_tal_get_INTCPUSEL0_RTC_bit(const void *const hw)
2741 {
2742 uint32_t tmp;
2743 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2744 tmp = (tmp & TAL_INTCPUSEL0_RTC_Msk) >> TAL_INTCPUSEL0_RTC_Pos;
2745 return (bool)tmp;
2746 }
2747
hri_tal_write_INTCPUSEL0_RTC_bit(const void * const hw,bool value)2748 static inline void hri_tal_write_INTCPUSEL0_RTC_bit(const void *const hw, bool value)
2749 {
2750 uint32_t tmp;
2751 TAL_CRITICAL_SECTION_ENTER();
2752 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2753 tmp &= ~TAL_INTCPUSEL0_RTC_Msk;
2754 tmp |= value << TAL_INTCPUSEL0_RTC_Pos;
2755 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
2756 TAL_CRITICAL_SECTION_LEAVE();
2757 }
2758
hri_tal_clear_INTCPUSEL0_RTC_bit(const void * const hw)2759 static inline void hri_tal_clear_INTCPUSEL0_RTC_bit(const void *const hw)
2760 {
2761 TAL_CRITICAL_SECTION_ENTER();
2762 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_RTC_Msk;
2763 TAL_CRITICAL_SECTION_LEAVE();
2764 }
2765
hri_tal_toggle_INTCPUSEL0_RTC_bit(const void * const hw)2766 static inline void hri_tal_toggle_INTCPUSEL0_RTC_bit(const void *const hw)
2767 {
2768 TAL_CRITICAL_SECTION_ENTER();
2769 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_RTC_Msk;
2770 TAL_CRITICAL_SECTION_LEAVE();
2771 }
2772
hri_tal_set_INTCPUSEL0_NVMCTRL_bit(const void * const hw)2773 static inline void hri_tal_set_INTCPUSEL0_NVMCTRL_bit(const void *const hw)
2774 {
2775 TAL_CRITICAL_SECTION_ENTER();
2776 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_NVMCTRL_Msk;
2777 TAL_CRITICAL_SECTION_LEAVE();
2778 }
2779
hri_tal_get_INTCPUSEL0_NVMCTRL_bit(const void * const hw)2780 static inline bool hri_tal_get_INTCPUSEL0_NVMCTRL_bit(const void *const hw)
2781 {
2782 uint32_t tmp;
2783 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2784 tmp = (tmp & TAL_INTCPUSEL0_NVMCTRL_Msk) >> TAL_INTCPUSEL0_NVMCTRL_Pos;
2785 return (bool)tmp;
2786 }
2787
hri_tal_write_INTCPUSEL0_NVMCTRL_bit(const void * const hw,bool value)2788 static inline void hri_tal_write_INTCPUSEL0_NVMCTRL_bit(const void *const hw, bool value)
2789 {
2790 uint32_t tmp;
2791 TAL_CRITICAL_SECTION_ENTER();
2792 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2793 tmp &= ~TAL_INTCPUSEL0_NVMCTRL_Msk;
2794 tmp |= value << TAL_INTCPUSEL0_NVMCTRL_Pos;
2795 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
2796 TAL_CRITICAL_SECTION_LEAVE();
2797 }
2798
hri_tal_clear_INTCPUSEL0_NVMCTRL_bit(const void * const hw)2799 static inline void hri_tal_clear_INTCPUSEL0_NVMCTRL_bit(const void *const hw)
2800 {
2801 TAL_CRITICAL_SECTION_ENTER();
2802 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_NVMCTRL_Msk;
2803 TAL_CRITICAL_SECTION_LEAVE();
2804 }
2805
hri_tal_toggle_INTCPUSEL0_NVMCTRL_bit(const void * const hw)2806 static inline void hri_tal_toggle_INTCPUSEL0_NVMCTRL_bit(const void *const hw)
2807 {
2808 TAL_CRITICAL_SECTION_ENTER();
2809 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_NVMCTRL_Msk;
2810 TAL_CRITICAL_SECTION_LEAVE();
2811 }
2812
hri_tal_set_INTCPUSEL0_USB_bit(const void * const hw)2813 static inline void hri_tal_set_INTCPUSEL0_USB_bit(const void *const hw)
2814 {
2815 TAL_CRITICAL_SECTION_ENTER();
2816 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_USB_Msk;
2817 TAL_CRITICAL_SECTION_LEAVE();
2818 }
2819
hri_tal_get_INTCPUSEL0_USB_bit(const void * const hw)2820 static inline bool hri_tal_get_INTCPUSEL0_USB_bit(const void *const hw)
2821 {
2822 uint32_t tmp;
2823 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2824 tmp = (tmp & TAL_INTCPUSEL0_USB_Msk) >> TAL_INTCPUSEL0_USB_Pos;
2825 return (bool)tmp;
2826 }
2827
hri_tal_write_INTCPUSEL0_USB_bit(const void * const hw,bool value)2828 static inline void hri_tal_write_INTCPUSEL0_USB_bit(const void *const hw, bool value)
2829 {
2830 uint32_t tmp;
2831 TAL_CRITICAL_SECTION_ENTER();
2832 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2833 tmp &= ~TAL_INTCPUSEL0_USB_Msk;
2834 tmp |= value << TAL_INTCPUSEL0_USB_Pos;
2835 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
2836 TAL_CRITICAL_SECTION_LEAVE();
2837 }
2838
hri_tal_clear_INTCPUSEL0_USB_bit(const void * const hw)2839 static inline void hri_tal_clear_INTCPUSEL0_USB_bit(const void *const hw)
2840 {
2841 TAL_CRITICAL_SECTION_ENTER();
2842 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_USB_Msk;
2843 TAL_CRITICAL_SECTION_LEAVE();
2844 }
2845
hri_tal_toggle_INTCPUSEL0_USB_bit(const void * const hw)2846 static inline void hri_tal_toggle_INTCPUSEL0_USB_bit(const void *const hw)
2847 {
2848 TAL_CRITICAL_SECTION_ENTER();
2849 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_USB_Msk;
2850 TAL_CRITICAL_SECTION_LEAVE();
2851 }
2852
hri_tal_set_INTCPUSEL0_SERCOM0_bit(const void * const hw)2853 static inline void hri_tal_set_INTCPUSEL0_SERCOM0_bit(const void *const hw)
2854 {
2855 TAL_CRITICAL_SECTION_ENTER();
2856 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SERCOM0_Msk;
2857 TAL_CRITICAL_SECTION_LEAVE();
2858 }
2859
hri_tal_get_INTCPUSEL0_SERCOM0_bit(const void * const hw)2860 static inline bool hri_tal_get_INTCPUSEL0_SERCOM0_bit(const void *const hw)
2861 {
2862 uint32_t tmp;
2863 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2864 tmp = (tmp & TAL_INTCPUSEL0_SERCOM0_Msk) >> TAL_INTCPUSEL0_SERCOM0_Pos;
2865 return (bool)tmp;
2866 }
2867
hri_tal_write_INTCPUSEL0_SERCOM0_bit(const void * const hw,bool value)2868 static inline void hri_tal_write_INTCPUSEL0_SERCOM0_bit(const void *const hw, bool value)
2869 {
2870 uint32_t tmp;
2871 TAL_CRITICAL_SECTION_ENTER();
2872 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2873 tmp &= ~TAL_INTCPUSEL0_SERCOM0_Msk;
2874 tmp |= value << TAL_INTCPUSEL0_SERCOM0_Pos;
2875 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
2876 TAL_CRITICAL_SECTION_LEAVE();
2877 }
2878
hri_tal_clear_INTCPUSEL0_SERCOM0_bit(const void * const hw)2879 static inline void hri_tal_clear_INTCPUSEL0_SERCOM0_bit(const void *const hw)
2880 {
2881 TAL_CRITICAL_SECTION_ENTER();
2882 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SERCOM0_Msk;
2883 TAL_CRITICAL_SECTION_LEAVE();
2884 }
2885
hri_tal_toggle_INTCPUSEL0_SERCOM0_bit(const void * const hw)2886 static inline void hri_tal_toggle_INTCPUSEL0_SERCOM0_bit(const void *const hw)
2887 {
2888 TAL_CRITICAL_SECTION_ENTER();
2889 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SERCOM0_Msk;
2890 TAL_CRITICAL_SECTION_LEAVE();
2891 }
2892
hri_tal_set_INTCPUSEL0_SERCOM1_bit(const void * const hw)2893 static inline void hri_tal_set_INTCPUSEL0_SERCOM1_bit(const void *const hw)
2894 {
2895 TAL_CRITICAL_SECTION_ENTER();
2896 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SERCOM1_Msk;
2897 TAL_CRITICAL_SECTION_LEAVE();
2898 }
2899
hri_tal_get_INTCPUSEL0_SERCOM1_bit(const void * const hw)2900 static inline bool hri_tal_get_INTCPUSEL0_SERCOM1_bit(const void *const hw)
2901 {
2902 uint32_t tmp;
2903 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2904 tmp = (tmp & TAL_INTCPUSEL0_SERCOM1_Msk) >> TAL_INTCPUSEL0_SERCOM1_Pos;
2905 return (bool)tmp;
2906 }
2907
hri_tal_write_INTCPUSEL0_SERCOM1_bit(const void * const hw,bool value)2908 static inline void hri_tal_write_INTCPUSEL0_SERCOM1_bit(const void *const hw, bool value)
2909 {
2910 uint32_t tmp;
2911 TAL_CRITICAL_SECTION_ENTER();
2912 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2913 tmp &= ~TAL_INTCPUSEL0_SERCOM1_Msk;
2914 tmp |= value << TAL_INTCPUSEL0_SERCOM1_Pos;
2915 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
2916 TAL_CRITICAL_SECTION_LEAVE();
2917 }
2918
hri_tal_clear_INTCPUSEL0_SERCOM1_bit(const void * const hw)2919 static inline void hri_tal_clear_INTCPUSEL0_SERCOM1_bit(const void *const hw)
2920 {
2921 TAL_CRITICAL_SECTION_ENTER();
2922 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SERCOM1_Msk;
2923 TAL_CRITICAL_SECTION_LEAVE();
2924 }
2925
hri_tal_toggle_INTCPUSEL0_SERCOM1_bit(const void * const hw)2926 static inline void hri_tal_toggle_INTCPUSEL0_SERCOM1_bit(const void *const hw)
2927 {
2928 TAL_CRITICAL_SECTION_ENTER();
2929 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SERCOM1_Msk;
2930 TAL_CRITICAL_SECTION_LEAVE();
2931 }
2932
hri_tal_set_INTCPUSEL0_SERCOM2_bit(const void * const hw)2933 static inline void hri_tal_set_INTCPUSEL0_SERCOM2_bit(const void *const hw)
2934 {
2935 TAL_CRITICAL_SECTION_ENTER();
2936 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SERCOM2_Msk;
2937 TAL_CRITICAL_SECTION_LEAVE();
2938 }
2939
hri_tal_get_INTCPUSEL0_SERCOM2_bit(const void * const hw)2940 static inline bool hri_tal_get_INTCPUSEL0_SERCOM2_bit(const void *const hw)
2941 {
2942 uint32_t tmp;
2943 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2944 tmp = (tmp & TAL_INTCPUSEL0_SERCOM2_Msk) >> TAL_INTCPUSEL0_SERCOM2_Pos;
2945 return (bool)tmp;
2946 }
2947
hri_tal_write_INTCPUSEL0_SERCOM2_bit(const void * const hw,bool value)2948 static inline void hri_tal_write_INTCPUSEL0_SERCOM2_bit(const void *const hw, bool value)
2949 {
2950 uint32_t tmp;
2951 TAL_CRITICAL_SECTION_ENTER();
2952 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2953 tmp &= ~TAL_INTCPUSEL0_SERCOM2_Msk;
2954 tmp |= value << TAL_INTCPUSEL0_SERCOM2_Pos;
2955 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
2956 TAL_CRITICAL_SECTION_LEAVE();
2957 }
2958
hri_tal_clear_INTCPUSEL0_SERCOM2_bit(const void * const hw)2959 static inline void hri_tal_clear_INTCPUSEL0_SERCOM2_bit(const void *const hw)
2960 {
2961 TAL_CRITICAL_SECTION_ENTER();
2962 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SERCOM2_Msk;
2963 TAL_CRITICAL_SECTION_LEAVE();
2964 }
2965
hri_tal_toggle_INTCPUSEL0_SERCOM2_bit(const void * const hw)2966 static inline void hri_tal_toggle_INTCPUSEL0_SERCOM2_bit(const void *const hw)
2967 {
2968 TAL_CRITICAL_SECTION_ENTER();
2969 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SERCOM2_Msk;
2970 TAL_CRITICAL_SECTION_LEAVE();
2971 }
2972
hri_tal_set_INTCPUSEL0_SERCOM3_bit(const void * const hw)2973 static inline void hri_tal_set_INTCPUSEL0_SERCOM3_bit(const void *const hw)
2974 {
2975 TAL_CRITICAL_SECTION_ENTER();
2976 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SERCOM3_Msk;
2977 TAL_CRITICAL_SECTION_LEAVE();
2978 }
2979
hri_tal_get_INTCPUSEL0_SERCOM3_bit(const void * const hw)2980 static inline bool hri_tal_get_INTCPUSEL0_SERCOM3_bit(const void *const hw)
2981 {
2982 uint32_t tmp;
2983 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2984 tmp = (tmp & TAL_INTCPUSEL0_SERCOM3_Msk) >> TAL_INTCPUSEL0_SERCOM3_Pos;
2985 return (bool)tmp;
2986 }
2987
hri_tal_write_INTCPUSEL0_SERCOM3_bit(const void * const hw,bool value)2988 static inline void hri_tal_write_INTCPUSEL0_SERCOM3_bit(const void *const hw, bool value)
2989 {
2990 uint32_t tmp;
2991 TAL_CRITICAL_SECTION_ENTER();
2992 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
2993 tmp &= ~TAL_INTCPUSEL0_SERCOM3_Msk;
2994 tmp |= value << TAL_INTCPUSEL0_SERCOM3_Pos;
2995 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
2996 TAL_CRITICAL_SECTION_LEAVE();
2997 }
2998
hri_tal_clear_INTCPUSEL0_SERCOM3_bit(const void * const hw)2999 static inline void hri_tal_clear_INTCPUSEL0_SERCOM3_bit(const void *const hw)
3000 {
3001 TAL_CRITICAL_SECTION_ENTER();
3002 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SERCOM3_Msk;
3003 TAL_CRITICAL_SECTION_LEAVE();
3004 }
3005
hri_tal_toggle_INTCPUSEL0_SERCOM3_bit(const void * const hw)3006 static inline void hri_tal_toggle_INTCPUSEL0_SERCOM3_bit(const void *const hw)
3007 {
3008 TAL_CRITICAL_SECTION_ENTER();
3009 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SERCOM3_Msk;
3010 TAL_CRITICAL_SECTION_LEAVE();
3011 }
3012
hri_tal_set_INTCPUSEL0_SERCOM4_bit(const void * const hw)3013 static inline void hri_tal_set_INTCPUSEL0_SERCOM4_bit(const void *const hw)
3014 {
3015 TAL_CRITICAL_SECTION_ENTER();
3016 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SERCOM4_Msk;
3017 TAL_CRITICAL_SECTION_LEAVE();
3018 }
3019
hri_tal_get_INTCPUSEL0_SERCOM4_bit(const void * const hw)3020 static inline bool hri_tal_get_INTCPUSEL0_SERCOM4_bit(const void *const hw)
3021 {
3022 uint32_t tmp;
3023 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
3024 tmp = (tmp & TAL_INTCPUSEL0_SERCOM4_Msk) >> TAL_INTCPUSEL0_SERCOM4_Pos;
3025 return (bool)tmp;
3026 }
3027
hri_tal_write_INTCPUSEL0_SERCOM4_bit(const void * const hw,bool value)3028 static inline void hri_tal_write_INTCPUSEL0_SERCOM4_bit(const void *const hw, bool value)
3029 {
3030 uint32_t tmp;
3031 TAL_CRITICAL_SECTION_ENTER();
3032 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
3033 tmp &= ~TAL_INTCPUSEL0_SERCOM4_Msk;
3034 tmp |= value << TAL_INTCPUSEL0_SERCOM4_Pos;
3035 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
3036 TAL_CRITICAL_SECTION_LEAVE();
3037 }
3038
hri_tal_clear_INTCPUSEL0_SERCOM4_bit(const void * const hw)3039 static inline void hri_tal_clear_INTCPUSEL0_SERCOM4_bit(const void *const hw)
3040 {
3041 TAL_CRITICAL_SECTION_ENTER();
3042 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SERCOM4_Msk;
3043 TAL_CRITICAL_SECTION_LEAVE();
3044 }
3045
hri_tal_toggle_INTCPUSEL0_SERCOM4_bit(const void * const hw)3046 static inline void hri_tal_toggle_INTCPUSEL0_SERCOM4_bit(const void *const hw)
3047 {
3048 TAL_CRITICAL_SECTION_ENTER();
3049 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SERCOM4_Msk;
3050 TAL_CRITICAL_SECTION_LEAVE();
3051 }
3052
hri_tal_set_INTCPUSEL0_SERCOM5_bit(const void * const hw)3053 static inline void hri_tal_set_INTCPUSEL0_SERCOM5_bit(const void *const hw)
3054 {
3055 TAL_CRITICAL_SECTION_ENTER();
3056 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_SERCOM5_Msk;
3057 TAL_CRITICAL_SECTION_LEAVE();
3058 }
3059
hri_tal_get_INTCPUSEL0_SERCOM5_bit(const void * const hw)3060 static inline bool hri_tal_get_INTCPUSEL0_SERCOM5_bit(const void *const hw)
3061 {
3062 uint32_t tmp;
3063 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
3064 tmp = (tmp & TAL_INTCPUSEL0_SERCOM5_Msk) >> TAL_INTCPUSEL0_SERCOM5_Pos;
3065 return (bool)tmp;
3066 }
3067
hri_tal_write_INTCPUSEL0_SERCOM5_bit(const void * const hw,bool value)3068 static inline void hri_tal_write_INTCPUSEL0_SERCOM5_bit(const void *const hw, bool value)
3069 {
3070 uint32_t tmp;
3071 TAL_CRITICAL_SECTION_ENTER();
3072 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
3073 tmp &= ~TAL_INTCPUSEL0_SERCOM5_Msk;
3074 tmp |= value << TAL_INTCPUSEL0_SERCOM5_Pos;
3075 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
3076 TAL_CRITICAL_SECTION_LEAVE();
3077 }
3078
hri_tal_clear_INTCPUSEL0_SERCOM5_bit(const void * const hw)3079 static inline void hri_tal_clear_INTCPUSEL0_SERCOM5_bit(const void *const hw)
3080 {
3081 TAL_CRITICAL_SECTION_ENTER();
3082 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_SERCOM5_Msk;
3083 TAL_CRITICAL_SECTION_LEAVE();
3084 }
3085
hri_tal_toggle_INTCPUSEL0_SERCOM5_bit(const void * const hw)3086 static inline void hri_tal_toggle_INTCPUSEL0_SERCOM5_bit(const void *const hw)
3087 {
3088 TAL_CRITICAL_SECTION_ENTER();
3089 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_SERCOM5_Msk;
3090 TAL_CRITICAL_SECTION_LEAVE();
3091 }
3092
hri_tal_set_INTCPUSEL0_TCC0_bit(const void * const hw)3093 static inline void hri_tal_set_INTCPUSEL0_TCC0_bit(const void *const hw)
3094 {
3095 TAL_CRITICAL_SECTION_ENTER();
3096 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_TCC0_Msk;
3097 TAL_CRITICAL_SECTION_LEAVE();
3098 }
3099
hri_tal_get_INTCPUSEL0_TCC0_bit(const void * const hw)3100 static inline bool hri_tal_get_INTCPUSEL0_TCC0_bit(const void *const hw)
3101 {
3102 uint32_t tmp;
3103 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
3104 tmp = (tmp & TAL_INTCPUSEL0_TCC0_Msk) >> TAL_INTCPUSEL0_TCC0_Pos;
3105 return (bool)tmp;
3106 }
3107
hri_tal_write_INTCPUSEL0_TCC0_bit(const void * const hw,bool value)3108 static inline void hri_tal_write_INTCPUSEL0_TCC0_bit(const void *const hw, bool value)
3109 {
3110 uint32_t tmp;
3111 TAL_CRITICAL_SECTION_ENTER();
3112 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
3113 tmp &= ~TAL_INTCPUSEL0_TCC0_Msk;
3114 tmp |= value << TAL_INTCPUSEL0_TCC0_Pos;
3115 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
3116 TAL_CRITICAL_SECTION_LEAVE();
3117 }
3118
hri_tal_clear_INTCPUSEL0_TCC0_bit(const void * const hw)3119 static inline void hri_tal_clear_INTCPUSEL0_TCC0_bit(const void *const hw)
3120 {
3121 TAL_CRITICAL_SECTION_ENTER();
3122 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_TCC0_Msk;
3123 TAL_CRITICAL_SECTION_LEAVE();
3124 }
3125
hri_tal_toggle_INTCPUSEL0_TCC0_bit(const void * const hw)3126 static inline void hri_tal_toggle_INTCPUSEL0_TCC0_bit(const void *const hw)
3127 {
3128 TAL_CRITICAL_SECTION_ENTER();
3129 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_TCC0_Msk;
3130 TAL_CRITICAL_SECTION_LEAVE();
3131 }
3132
hri_tal_set_INTCPUSEL0_TCC1_bit(const void * const hw)3133 static inline void hri_tal_set_INTCPUSEL0_TCC1_bit(const void *const hw)
3134 {
3135 TAL_CRITICAL_SECTION_ENTER();
3136 ((Tal *)hw)->INTCPUSEL0.reg |= TAL_INTCPUSEL0_TCC1_Msk;
3137 TAL_CRITICAL_SECTION_LEAVE();
3138 }
3139
hri_tal_get_INTCPUSEL0_TCC1_bit(const void * const hw)3140 static inline bool hri_tal_get_INTCPUSEL0_TCC1_bit(const void *const hw)
3141 {
3142 uint32_t tmp;
3143 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
3144 tmp = (tmp & TAL_INTCPUSEL0_TCC1_Msk) >> TAL_INTCPUSEL0_TCC1_Pos;
3145 return (bool)tmp;
3146 }
3147
hri_tal_write_INTCPUSEL0_TCC1_bit(const void * const hw,bool value)3148 static inline void hri_tal_write_INTCPUSEL0_TCC1_bit(const void *const hw, bool value)
3149 {
3150 uint32_t tmp;
3151 TAL_CRITICAL_SECTION_ENTER();
3152 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
3153 tmp &= ~TAL_INTCPUSEL0_TCC1_Msk;
3154 tmp |= value << TAL_INTCPUSEL0_TCC1_Pos;
3155 ((Tal *)hw)->INTCPUSEL0.reg = tmp;
3156 TAL_CRITICAL_SECTION_LEAVE();
3157 }
3158
hri_tal_clear_INTCPUSEL0_TCC1_bit(const void * const hw)3159 static inline void hri_tal_clear_INTCPUSEL0_TCC1_bit(const void *const hw)
3160 {
3161 TAL_CRITICAL_SECTION_ENTER();
3162 ((Tal *)hw)->INTCPUSEL0.reg &= ~TAL_INTCPUSEL0_TCC1_Msk;
3163 TAL_CRITICAL_SECTION_LEAVE();
3164 }
3165
hri_tal_toggle_INTCPUSEL0_TCC1_bit(const void * const hw)3166 static inline void hri_tal_toggle_INTCPUSEL0_TCC1_bit(const void *const hw)
3167 {
3168 TAL_CRITICAL_SECTION_ENTER();
3169 ((Tal *)hw)->INTCPUSEL0.reg ^= TAL_INTCPUSEL0_TCC1_Msk;
3170 TAL_CRITICAL_SECTION_LEAVE();
3171 }
3172
hri_tal_set_INTCPUSEL0_reg(const void * const hw,hri_tal_intcpusel0_reg_t mask)3173 static inline void hri_tal_set_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask)
3174 {
3175 TAL_CRITICAL_SECTION_ENTER();
3176 ((Tal *)hw)->INTCPUSEL0.reg |= mask;
3177 TAL_CRITICAL_SECTION_LEAVE();
3178 }
3179
hri_tal_get_INTCPUSEL0_reg(const void * const hw,hri_tal_intcpusel0_reg_t mask)3180 static inline hri_tal_intcpusel0_reg_t hri_tal_get_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask)
3181 {
3182 uint32_t tmp;
3183 tmp = ((Tal *)hw)->INTCPUSEL0.reg;
3184 tmp &= mask;
3185 return tmp;
3186 }
3187
hri_tal_write_INTCPUSEL0_reg(const void * const hw,hri_tal_intcpusel0_reg_t data)3188 static inline void hri_tal_write_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t data)
3189 {
3190 TAL_CRITICAL_SECTION_ENTER();
3191 ((Tal *)hw)->INTCPUSEL0.reg = data;
3192 TAL_CRITICAL_SECTION_LEAVE();
3193 }
3194
hri_tal_clear_INTCPUSEL0_reg(const void * const hw,hri_tal_intcpusel0_reg_t mask)3195 static inline void hri_tal_clear_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask)
3196 {
3197 TAL_CRITICAL_SECTION_ENTER();
3198 ((Tal *)hw)->INTCPUSEL0.reg &= ~mask;
3199 TAL_CRITICAL_SECTION_LEAVE();
3200 }
3201
hri_tal_toggle_INTCPUSEL0_reg(const void * const hw,hri_tal_intcpusel0_reg_t mask)3202 static inline void hri_tal_toggle_INTCPUSEL0_reg(const void *const hw, hri_tal_intcpusel0_reg_t mask)
3203 {
3204 TAL_CRITICAL_SECTION_ENTER();
3205 ((Tal *)hw)->INTCPUSEL0.reg ^= mask;
3206 TAL_CRITICAL_SECTION_LEAVE();
3207 }
3208
hri_tal_read_INTCPUSEL0_reg(const void * const hw)3209 static inline hri_tal_intcpusel0_reg_t hri_tal_read_INTCPUSEL0_reg(const void *const hw)
3210 {
3211 return ((Tal *)hw)->INTCPUSEL0.reg;
3212 }
3213
hri_tal_set_INTCPUSEL1_TCC2_bit(const void * const hw)3214 static inline void hri_tal_set_INTCPUSEL1_TCC2_bit(const void *const hw)
3215 {
3216 TAL_CRITICAL_SECTION_ENTER();
3217 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_TCC2_Msk;
3218 TAL_CRITICAL_SECTION_LEAVE();
3219 }
3220
hri_tal_get_INTCPUSEL1_TCC2_bit(const void * const hw)3221 static inline bool hri_tal_get_INTCPUSEL1_TCC2_bit(const void *const hw)
3222 {
3223 uint32_t tmp;
3224 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3225 tmp = (tmp & TAL_INTCPUSEL1_TCC2_Msk) >> TAL_INTCPUSEL1_TCC2_Pos;
3226 return (bool)tmp;
3227 }
3228
hri_tal_write_INTCPUSEL1_TCC2_bit(const void * const hw,bool value)3229 static inline void hri_tal_write_INTCPUSEL1_TCC2_bit(const void *const hw, bool value)
3230 {
3231 uint32_t tmp;
3232 TAL_CRITICAL_SECTION_ENTER();
3233 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3234 tmp &= ~TAL_INTCPUSEL1_TCC2_Msk;
3235 tmp |= value << TAL_INTCPUSEL1_TCC2_Pos;
3236 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3237 TAL_CRITICAL_SECTION_LEAVE();
3238 }
3239
hri_tal_clear_INTCPUSEL1_TCC2_bit(const void * const hw)3240 static inline void hri_tal_clear_INTCPUSEL1_TCC2_bit(const void *const hw)
3241 {
3242 TAL_CRITICAL_SECTION_ENTER();
3243 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_TCC2_Msk;
3244 TAL_CRITICAL_SECTION_LEAVE();
3245 }
3246
hri_tal_toggle_INTCPUSEL1_TCC2_bit(const void * const hw)3247 static inline void hri_tal_toggle_INTCPUSEL1_TCC2_bit(const void *const hw)
3248 {
3249 TAL_CRITICAL_SECTION_ENTER();
3250 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_TCC2_Msk;
3251 TAL_CRITICAL_SECTION_LEAVE();
3252 }
3253
hri_tal_set_INTCPUSEL1_TC0_bit(const void * const hw)3254 static inline void hri_tal_set_INTCPUSEL1_TC0_bit(const void *const hw)
3255 {
3256 TAL_CRITICAL_SECTION_ENTER();
3257 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_TC0_Msk;
3258 TAL_CRITICAL_SECTION_LEAVE();
3259 }
3260
hri_tal_get_INTCPUSEL1_TC0_bit(const void * const hw)3261 static inline bool hri_tal_get_INTCPUSEL1_TC0_bit(const void *const hw)
3262 {
3263 uint32_t tmp;
3264 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3265 tmp = (tmp & TAL_INTCPUSEL1_TC0_Msk) >> TAL_INTCPUSEL1_TC0_Pos;
3266 return (bool)tmp;
3267 }
3268
hri_tal_write_INTCPUSEL1_TC0_bit(const void * const hw,bool value)3269 static inline void hri_tal_write_INTCPUSEL1_TC0_bit(const void *const hw, bool value)
3270 {
3271 uint32_t tmp;
3272 TAL_CRITICAL_SECTION_ENTER();
3273 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3274 tmp &= ~TAL_INTCPUSEL1_TC0_Msk;
3275 tmp |= value << TAL_INTCPUSEL1_TC0_Pos;
3276 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3277 TAL_CRITICAL_SECTION_LEAVE();
3278 }
3279
hri_tal_clear_INTCPUSEL1_TC0_bit(const void * const hw)3280 static inline void hri_tal_clear_INTCPUSEL1_TC0_bit(const void *const hw)
3281 {
3282 TAL_CRITICAL_SECTION_ENTER();
3283 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_TC0_Msk;
3284 TAL_CRITICAL_SECTION_LEAVE();
3285 }
3286
hri_tal_toggle_INTCPUSEL1_TC0_bit(const void * const hw)3287 static inline void hri_tal_toggle_INTCPUSEL1_TC0_bit(const void *const hw)
3288 {
3289 TAL_CRITICAL_SECTION_ENTER();
3290 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_TC0_Msk;
3291 TAL_CRITICAL_SECTION_LEAVE();
3292 }
3293
hri_tal_set_INTCPUSEL1_TC1_bit(const void * const hw)3294 static inline void hri_tal_set_INTCPUSEL1_TC1_bit(const void *const hw)
3295 {
3296 TAL_CRITICAL_SECTION_ENTER();
3297 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_TC1_Msk;
3298 TAL_CRITICAL_SECTION_LEAVE();
3299 }
3300
hri_tal_get_INTCPUSEL1_TC1_bit(const void * const hw)3301 static inline bool hri_tal_get_INTCPUSEL1_TC1_bit(const void *const hw)
3302 {
3303 uint32_t tmp;
3304 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3305 tmp = (tmp & TAL_INTCPUSEL1_TC1_Msk) >> TAL_INTCPUSEL1_TC1_Pos;
3306 return (bool)tmp;
3307 }
3308
hri_tal_write_INTCPUSEL1_TC1_bit(const void * const hw,bool value)3309 static inline void hri_tal_write_INTCPUSEL1_TC1_bit(const void *const hw, bool value)
3310 {
3311 uint32_t tmp;
3312 TAL_CRITICAL_SECTION_ENTER();
3313 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3314 tmp &= ~TAL_INTCPUSEL1_TC1_Msk;
3315 tmp |= value << TAL_INTCPUSEL1_TC1_Pos;
3316 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3317 TAL_CRITICAL_SECTION_LEAVE();
3318 }
3319
hri_tal_clear_INTCPUSEL1_TC1_bit(const void * const hw)3320 static inline void hri_tal_clear_INTCPUSEL1_TC1_bit(const void *const hw)
3321 {
3322 TAL_CRITICAL_SECTION_ENTER();
3323 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_TC1_Msk;
3324 TAL_CRITICAL_SECTION_LEAVE();
3325 }
3326
hri_tal_toggle_INTCPUSEL1_TC1_bit(const void * const hw)3327 static inline void hri_tal_toggle_INTCPUSEL1_TC1_bit(const void *const hw)
3328 {
3329 TAL_CRITICAL_SECTION_ENTER();
3330 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_TC1_Msk;
3331 TAL_CRITICAL_SECTION_LEAVE();
3332 }
3333
hri_tal_set_INTCPUSEL1_TC2_bit(const void * const hw)3334 static inline void hri_tal_set_INTCPUSEL1_TC2_bit(const void *const hw)
3335 {
3336 TAL_CRITICAL_SECTION_ENTER();
3337 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_TC2_Msk;
3338 TAL_CRITICAL_SECTION_LEAVE();
3339 }
3340
hri_tal_get_INTCPUSEL1_TC2_bit(const void * const hw)3341 static inline bool hri_tal_get_INTCPUSEL1_TC2_bit(const void *const hw)
3342 {
3343 uint32_t tmp;
3344 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3345 tmp = (tmp & TAL_INTCPUSEL1_TC2_Msk) >> TAL_INTCPUSEL1_TC2_Pos;
3346 return (bool)tmp;
3347 }
3348
hri_tal_write_INTCPUSEL1_TC2_bit(const void * const hw,bool value)3349 static inline void hri_tal_write_INTCPUSEL1_TC2_bit(const void *const hw, bool value)
3350 {
3351 uint32_t tmp;
3352 TAL_CRITICAL_SECTION_ENTER();
3353 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3354 tmp &= ~TAL_INTCPUSEL1_TC2_Msk;
3355 tmp |= value << TAL_INTCPUSEL1_TC2_Pos;
3356 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3357 TAL_CRITICAL_SECTION_LEAVE();
3358 }
3359
hri_tal_clear_INTCPUSEL1_TC2_bit(const void * const hw)3360 static inline void hri_tal_clear_INTCPUSEL1_TC2_bit(const void *const hw)
3361 {
3362 TAL_CRITICAL_SECTION_ENTER();
3363 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_TC2_Msk;
3364 TAL_CRITICAL_SECTION_LEAVE();
3365 }
3366
hri_tal_toggle_INTCPUSEL1_TC2_bit(const void * const hw)3367 static inline void hri_tal_toggle_INTCPUSEL1_TC2_bit(const void *const hw)
3368 {
3369 TAL_CRITICAL_SECTION_ENTER();
3370 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_TC2_Msk;
3371 TAL_CRITICAL_SECTION_LEAVE();
3372 }
3373
hri_tal_set_INTCPUSEL1_TC3_bit(const void * const hw)3374 static inline void hri_tal_set_INTCPUSEL1_TC3_bit(const void *const hw)
3375 {
3376 TAL_CRITICAL_SECTION_ENTER();
3377 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_TC3_Msk;
3378 TAL_CRITICAL_SECTION_LEAVE();
3379 }
3380
hri_tal_get_INTCPUSEL1_TC3_bit(const void * const hw)3381 static inline bool hri_tal_get_INTCPUSEL1_TC3_bit(const void *const hw)
3382 {
3383 uint32_t tmp;
3384 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3385 tmp = (tmp & TAL_INTCPUSEL1_TC3_Msk) >> TAL_INTCPUSEL1_TC3_Pos;
3386 return (bool)tmp;
3387 }
3388
hri_tal_write_INTCPUSEL1_TC3_bit(const void * const hw,bool value)3389 static inline void hri_tal_write_INTCPUSEL1_TC3_bit(const void *const hw, bool value)
3390 {
3391 uint32_t tmp;
3392 TAL_CRITICAL_SECTION_ENTER();
3393 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3394 tmp &= ~TAL_INTCPUSEL1_TC3_Msk;
3395 tmp |= value << TAL_INTCPUSEL1_TC3_Pos;
3396 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3397 TAL_CRITICAL_SECTION_LEAVE();
3398 }
3399
hri_tal_clear_INTCPUSEL1_TC3_bit(const void * const hw)3400 static inline void hri_tal_clear_INTCPUSEL1_TC3_bit(const void *const hw)
3401 {
3402 TAL_CRITICAL_SECTION_ENTER();
3403 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_TC3_Msk;
3404 TAL_CRITICAL_SECTION_LEAVE();
3405 }
3406
hri_tal_toggle_INTCPUSEL1_TC3_bit(const void * const hw)3407 static inline void hri_tal_toggle_INTCPUSEL1_TC3_bit(const void *const hw)
3408 {
3409 TAL_CRITICAL_SECTION_ENTER();
3410 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_TC3_Msk;
3411 TAL_CRITICAL_SECTION_LEAVE();
3412 }
3413
hri_tal_set_INTCPUSEL1_TC4_bit(const void * const hw)3414 static inline void hri_tal_set_INTCPUSEL1_TC4_bit(const void *const hw)
3415 {
3416 TAL_CRITICAL_SECTION_ENTER();
3417 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_TC4_Msk;
3418 TAL_CRITICAL_SECTION_LEAVE();
3419 }
3420
hri_tal_get_INTCPUSEL1_TC4_bit(const void * const hw)3421 static inline bool hri_tal_get_INTCPUSEL1_TC4_bit(const void *const hw)
3422 {
3423 uint32_t tmp;
3424 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3425 tmp = (tmp & TAL_INTCPUSEL1_TC4_Msk) >> TAL_INTCPUSEL1_TC4_Pos;
3426 return (bool)tmp;
3427 }
3428
hri_tal_write_INTCPUSEL1_TC4_bit(const void * const hw,bool value)3429 static inline void hri_tal_write_INTCPUSEL1_TC4_bit(const void *const hw, bool value)
3430 {
3431 uint32_t tmp;
3432 TAL_CRITICAL_SECTION_ENTER();
3433 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3434 tmp &= ~TAL_INTCPUSEL1_TC4_Msk;
3435 tmp |= value << TAL_INTCPUSEL1_TC4_Pos;
3436 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3437 TAL_CRITICAL_SECTION_LEAVE();
3438 }
3439
hri_tal_clear_INTCPUSEL1_TC4_bit(const void * const hw)3440 static inline void hri_tal_clear_INTCPUSEL1_TC4_bit(const void *const hw)
3441 {
3442 TAL_CRITICAL_SECTION_ENTER();
3443 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_TC4_Msk;
3444 TAL_CRITICAL_SECTION_LEAVE();
3445 }
3446
hri_tal_toggle_INTCPUSEL1_TC4_bit(const void * const hw)3447 static inline void hri_tal_toggle_INTCPUSEL1_TC4_bit(const void *const hw)
3448 {
3449 TAL_CRITICAL_SECTION_ENTER();
3450 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_TC4_Msk;
3451 TAL_CRITICAL_SECTION_LEAVE();
3452 }
3453
hri_tal_set_INTCPUSEL1_ADC_bit(const void * const hw)3454 static inline void hri_tal_set_INTCPUSEL1_ADC_bit(const void *const hw)
3455 {
3456 TAL_CRITICAL_SECTION_ENTER();
3457 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_ADC_Msk;
3458 TAL_CRITICAL_SECTION_LEAVE();
3459 }
3460
hri_tal_get_INTCPUSEL1_ADC_bit(const void * const hw)3461 static inline bool hri_tal_get_INTCPUSEL1_ADC_bit(const void *const hw)
3462 {
3463 uint32_t tmp;
3464 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3465 tmp = (tmp & TAL_INTCPUSEL1_ADC_Msk) >> TAL_INTCPUSEL1_ADC_Pos;
3466 return (bool)tmp;
3467 }
3468
hri_tal_write_INTCPUSEL1_ADC_bit(const void * const hw,bool value)3469 static inline void hri_tal_write_INTCPUSEL1_ADC_bit(const void *const hw, bool value)
3470 {
3471 uint32_t tmp;
3472 TAL_CRITICAL_SECTION_ENTER();
3473 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3474 tmp &= ~TAL_INTCPUSEL1_ADC_Msk;
3475 tmp |= value << TAL_INTCPUSEL1_ADC_Pos;
3476 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3477 TAL_CRITICAL_SECTION_LEAVE();
3478 }
3479
hri_tal_clear_INTCPUSEL1_ADC_bit(const void * const hw)3480 static inline void hri_tal_clear_INTCPUSEL1_ADC_bit(const void *const hw)
3481 {
3482 TAL_CRITICAL_SECTION_ENTER();
3483 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_ADC_Msk;
3484 TAL_CRITICAL_SECTION_LEAVE();
3485 }
3486
hri_tal_toggle_INTCPUSEL1_ADC_bit(const void * const hw)3487 static inline void hri_tal_toggle_INTCPUSEL1_ADC_bit(const void *const hw)
3488 {
3489 TAL_CRITICAL_SECTION_ENTER();
3490 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_ADC_Msk;
3491 TAL_CRITICAL_SECTION_LEAVE();
3492 }
3493
hri_tal_set_INTCPUSEL1_AC_bit(const void * const hw)3494 static inline void hri_tal_set_INTCPUSEL1_AC_bit(const void *const hw)
3495 {
3496 TAL_CRITICAL_SECTION_ENTER();
3497 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_AC_Msk;
3498 TAL_CRITICAL_SECTION_LEAVE();
3499 }
3500
hri_tal_get_INTCPUSEL1_AC_bit(const void * const hw)3501 static inline bool hri_tal_get_INTCPUSEL1_AC_bit(const void *const hw)
3502 {
3503 uint32_t tmp;
3504 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3505 tmp = (tmp & TAL_INTCPUSEL1_AC_Msk) >> TAL_INTCPUSEL1_AC_Pos;
3506 return (bool)tmp;
3507 }
3508
hri_tal_write_INTCPUSEL1_AC_bit(const void * const hw,bool value)3509 static inline void hri_tal_write_INTCPUSEL1_AC_bit(const void *const hw, bool value)
3510 {
3511 uint32_t tmp;
3512 TAL_CRITICAL_SECTION_ENTER();
3513 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3514 tmp &= ~TAL_INTCPUSEL1_AC_Msk;
3515 tmp |= value << TAL_INTCPUSEL1_AC_Pos;
3516 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3517 TAL_CRITICAL_SECTION_LEAVE();
3518 }
3519
hri_tal_clear_INTCPUSEL1_AC_bit(const void * const hw)3520 static inline void hri_tal_clear_INTCPUSEL1_AC_bit(const void *const hw)
3521 {
3522 TAL_CRITICAL_SECTION_ENTER();
3523 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_AC_Msk;
3524 TAL_CRITICAL_SECTION_LEAVE();
3525 }
3526
hri_tal_toggle_INTCPUSEL1_AC_bit(const void * const hw)3527 static inline void hri_tal_toggle_INTCPUSEL1_AC_bit(const void *const hw)
3528 {
3529 TAL_CRITICAL_SECTION_ENTER();
3530 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_AC_Msk;
3531 TAL_CRITICAL_SECTION_LEAVE();
3532 }
3533
hri_tal_set_INTCPUSEL1_DAC_bit(const void * const hw)3534 static inline void hri_tal_set_INTCPUSEL1_DAC_bit(const void *const hw)
3535 {
3536 TAL_CRITICAL_SECTION_ENTER();
3537 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_DAC_Msk;
3538 TAL_CRITICAL_SECTION_LEAVE();
3539 }
3540
hri_tal_get_INTCPUSEL1_DAC_bit(const void * const hw)3541 static inline bool hri_tal_get_INTCPUSEL1_DAC_bit(const void *const hw)
3542 {
3543 uint32_t tmp;
3544 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3545 tmp = (tmp & TAL_INTCPUSEL1_DAC_Msk) >> TAL_INTCPUSEL1_DAC_Pos;
3546 return (bool)tmp;
3547 }
3548
hri_tal_write_INTCPUSEL1_DAC_bit(const void * const hw,bool value)3549 static inline void hri_tal_write_INTCPUSEL1_DAC_bit(const void *const hw, bool value)
3550 {
3551 uint32_t tmp;
3552 TAL_CRITICAL_SECTION_ENTER();
3553 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3554 tmp &= ~TAL_INTCPUSEL1_DAC_Msk;
3555 tmp |= value << TAL_INTCPUSEL1_DAC_Pos;
3556 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3557 TAL_CRITICAL_SECTION_LEAVE();
3558 }
3559
hri_tal_clear_INTCPUSEL1_DAC_bit(const void * const hw)3560 static inline void hri_tal_clear_INTCPUSEL1_DAC_bit(const void *const hw)
3561 {
3562 TAL_CRITICAL_SECTION_ENTER();
3563 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_DAC_Msk;
3564 TAL_CRITICAL_SECTION_LEAVE();
3565 }
3566
hri_tal_toggle_INTCPUSEL1_DAC_bit(const void * const hw)3567 static inline void hri_tal_toggle_INTCPUSEL1_DAC_bit(const void *const hw)
3568 {
3569 TAL_CRITICAL_SECTION_ENTER();
3570 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_DAC_Msk;
3571 TAL_CRITICAL_SECTION_LEAVE();
3572 }
3573
hri_tal_set_INTCPUSEL1_PTC_bit(const void * const hw)3574 static inline void hri_tal_set_INTCPUSEL1_PTC_bit(const void *const hw)
3575 {
3576 TAL_CRITICAL_SECTION_ENTER();
3577 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_PTC_Msk;
3578 TAL_CRITICAL_SECTION_LEAVE();
3579 }
3580
hri_tal_get_INTCPUSEL1_PTC_bit(const void * const hw)3581 static inline bool hri_tal_get_INTCPUSEL1_PTC_bit(const void *const hw)
3582 {
3583 uint32_t tmp;
3584 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3585 tmp = (tmp & TAL_INTCPUSEL1_PTC_Msk) >> TAL_INTCPUSEL1_PTC_Pos;
3586 return (bool)tmp;
3587 }
3588
hri_tal_write_INTCPUSEL1_PTC_bit(const void * const hw,bool value)3589 static inline void hri_tal_write_INTCPUSEL1_PTC_bit(const void *const hw, bool value)
3590 {
3591 uint32_t tmp;
3592 TAL_CRITICAL_SECTION_ENTER();
3593 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3594 tmp &= ~TAL_INTCPUSEL1_PTC_Msk;
3595 tmp |= value << TAL_INTCPUSEL1_PTC_Pos;
3596 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3597 TAL_CRITICAL_SECTION_LEAVE();
3598 }
3599
hri_tal_clear_INTCPUSEL1_PTC_bit(const void * const hw)3600 static inline void hri_tal_clear_INTCPUSEL1_PTC_bit(const void *const hw)
3601 {
3602 TAL_CRITICAL_SECTION_ENTER();
3603 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_PTC_Msk;
3604 TAL_CRITICAL_SECTION_LEAVE();
3605 }
3606
hri_tal_toggle_INTCPUSEL1_PTC_bit(const void * const hw)3607 static inline void hri_tal_toggle_INTCPUSEL1_PTC_bit(const void *const hw)
3608 {
3609 TAL_CRITICAL_SECTION_ENTER();
3610 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_PTC_Msk;
3611 TAL_CRITICAL_SECTION_LEAVE();
3612 }
3613
hri_tal_set_INTCPUSEL1_AES_bit(const void * const hw)3614 static inline void hri_tal_set_INTCPUSEL1_AES_bit(const void *const hw)
3615 {
3616 TAL_CRITICAL_SECTION_ENTER();
3617 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_AES_Msk;
3618 TAL_CRITICAL_SECTION_LEAVE();
3619 }
3620
hri_tal_get_INTCPUSEL1_AES_bit(const void * const hw)3621 static inline bool hri_tal_get_INTCPUSEL1_AES_bit(const void *const hw)
3622 {
3623 uint32_t tmp;
3624 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3625 tmp = (tmp & TAL_INTCPUSEL1_AES_Msk) >> TAL_INTCPUSEL1_AES_Pos;
3626 return (bool)tmp;
3627 }
3628
hri_tal_write_INTCPUSEL1_AES_bit(const void * const hw,bool value)3629 static inline void hri_tal_write_INTCPUSEL1_AES_bit(const void *const hw, bool value)
3630 {
3631 uint32_t tmp;
3632 TAL_CRITICAL_SECTION_ENTER();
3633 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3634 tmp &= ~TAL_INTCPUSEL1_AES_Msk;
3635 tmp |= value << TAL_INTCPUSEL1_AES_Pos;
3636 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3637 TAL_CRITICAL_SECTION_LEAVE();
3638 }
3639
hri_tal_clear_INTCPUSEL1_AES_bit(const void * const hw)3640 static inline void hri_tal_clear_INTCPUSEL1_AES_bit(const void *const hw)
3641 {
3642 TAL_CRITICAL_SECTION_ENTER();
3643 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_AES_Msk;
3644 TAL_CRITICAL_SECTION_LEAVE();
3645 }
3646
hri_tal_toggle_INTCPUSEL1_AES_bit(const void * const hw)3647 static inline void hri_tal_toggle_INTCPUSEL1_AES_bit(const void *const hw)
3648 {
3649 TAL_CRITICAL_SECTION_ENTER();
3650 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_AES_Msk;
3651 TAL_CRITICAL_SECTION_LEAVE();
3652 }
3653
hri_tal_set_INTCPUSEL1_TRNG_bit(const void * const hw)3654 static inline void hri_tal_set_INTCPUSEL1_TRNG_bit(const void *const hw)
3655 {
3656 TAL_CRITICAL_SECTION_ENTER();
3657 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_TRNG_Msk;
3658 TAL_CRITICAL_SECTION_LEAVE();
3659 }
3660
hri_tal_get_INTCPUSEL1_TRNG_bit(const void * const hw)3661 static inline bool hri_tal_get_INTCPUSEL1_TRNG_bit(const void *const hw)
3662 {
3663 uint32_t tmp;
3664 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3665 tmp = (tmp & TAL_INTCPUSEL1_TRNG_Msk) >> TAL_INTCPUSEL1_TRNG_Pos;
3666 return (bool)tmp;
3667 }
3668
hri_tal_write_INTCPUSEL1_TRNG_bit(const void * const hw,bool value)3669 static inline void hri_tal_write_INTCPUSEL1_TRNG_bit(const void *const hw, bool value)
3670 {
3671 uint32_t tmp;
3672 TAL_CRITICAL_SECTION_ENTER();
3673 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3674 tmp &= ~TAL_INTCPUSEL1_TRNG_Msk;
3675 tmp |= value << TAL_INTCPUSEL1_TRNG_Pos;
3676 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3677 TAL_CRITICAL_SECTION_LEAVE();
3678 }
3679
hri_tal_clear_INTCPUSEL1_TRNG_bit(const void * const hw)3680 static inline void hri_tal_clear_INTCPUSEL1_TRNG_bit(const void *const hw)
3681 {
3682 TAL_CRITICAL_SECTION_ENTER();
3683 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_TRNG_Msk;
3684 TAL_CRITICAL_SECTION_LEAVE();
3685 }
3686
hri_tal_toggle_INTCPUSEL1_TRNG_bit(const void * const hw)3687 static inline void hri_tal_toggle_INTCPUSEL1_TRNG_bit(const void *const hw)
3688 {
3689 TAL_CRITICAL_SECTION_ENTER();
3690 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_TRNG_Msk;
3691 TAL_CRITICAL_SECTION_LEAVE();
3692 }
3693
hri_tal_set_INTCPUSEL1_PICOP_bit(const void * const hw)3694 static inline void hri_tal_set_INTCPUSEL1_PICOP_bit(const void *const hw)
3695 {
3696 TAL_CRITICAL_SECTION_ENTER();
3697 ((Tal *)hw)->INTCPUSEL1.reg |= TAL_INTCPUSEL1_PICOP_Msk;
3698 TAL_CRITICAL_SECTION_LEAVE();
3699 }
3700
hri_tal_get_INTCPUSEL1_PICOP_bit(const void * const hw)3701 static inline bool hri_tal_get_INTCPUSEL1_PICOP_bit(const void *const hw)
3702 {
3703 uint32_t tmp;
3704 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3705 tmp = (tmp & TAL_INTCPUSEL1_PICOP_Msk) >> TAL_INTCPUSEL1_PICOP_Pos;
3706 return (bool)tmp;
3707 }
3708
hri_tal_write_INTCPUSEL1_PICOP_bit(const void * const hw,bool value)3709 static inline void hri_tal_write_INTCPUSEL1_PICOP_bit(const void *const hw, bool value)
3710 {
3711 uint32_t tmp;
3712 TAL_CRITICAL_SECTION_ENTER();
3713 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3714 tmp &= ~TAL_INTCPUSEL1_PICOP_Msk;
3715 tmp |= value << TAL_INTCPUSEL1_PICOP_Pos;
3716 ((Tal *)hw)->INTCPUSEL1.reg = tmp;
3717 TAL_CRITICAL_SECTION_LEAVE();
3718 }
3719
hri_tal_clear_INTCPUSEL1_PICOP_bit(const void * const hw)3720 static inline void hri_tal_clear_INTCPUSEL1_PICOP_bit(const void *const hw)
3721 {
3722 TAL_CRITICAL_SECTION_ENTER();
3723 ((Tal *)hw)->INTCPUSEL1.reg &= ~TAL_INTCPUSEL1_PICOP_Msk;
3724 TAL_CRITICAL_SECTION_LEAVE();
3725 }
3726
hri_tal_toggle_INTCPUSEL1_PICOP_bit(const void * const hw)3727 static inline void hri_tal_toggle_INTCPUSEL1_PICOP_bit(const void *const hw)
3728 {
3729 TAL_CRITICAL_SECTION_ENTER();
3730 ((Tal *)hw)->INTCPUSEL1.reg ^= TAL_INTCPUSEL1_PICOP_Msk;
3731 TAL_CRITICAL_SECTION_LEAVE();
3732 }
3733
hri_tal_set_INTCPUSEL1_reg(const void * const hw,hri_tal_intcpusel1_reg_t mask)3734 static inline void hri_tal_set_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask)
3735 {
3736 TAL_CRITICAL_SECTION_ENTER();
3737 ((Tal *)hw)->INTCPUSEL1.reg |= mask;
3738 TAL_CRITICAL_SECTION_LEAVE();
3739 }
3740
hri_tal_get_INTCPUSEL1_reg(const void * const hw,hri_tal_intcpusel1_reg_t mask)3741 static inline hri_tal_intcpusel1_reg_t hri_tal_get_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask)
3742 {
3743 uint32_t tmp;
3744 tmp = ((Tal *)hw)->INTCPUSEL1.reg;
3745 tmp &= mask;
3746 return tmp;
3747 }
3748
hri_tal_write_INTCPUSEL1_reg(const void * const hw,hri_tal_intcpusel1_reg_t data)3749 static inline void hri_tal_write_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t data)
3750 {
3751 TAL_CRITICAL_SECTION_ENTER();
3752 ((Tal *)hw)->INTCPUSEL1.reg = data;
3753 TAL_CRITICAL_SECTION_LEAVE();
3754 }
3755
hri_tal_clear_INTCPUSEL1_reg(const void * const hw,hri_tal_intcpusel1_reg_t mask)3756 static inline void hri_tal_clear_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask)
3757 {
3758 TAL_CRITICAL_SECTION_ENTER();
3759 ((Tal *)hw)->INTCPUSEL1.reg &= ~mask;
3760 TAL_CRITICAL_SECTION_LEAVE();
3761 }
3762
hri_tal_toggle_INTCPUSEL1_reg(const void * const hw,hri_tal_intcpusel1_reg_t mask)3763 static inline void hri_tal_toggle_INTCPUSEL1_reg(const void *const hw, hri_tal_intcpusel1_reg_t mask)
3764 {
3765 TAL_CRITICAL_SECTION_ENTER();
3766 ((Tal *)hw)->INTCPUSEL1.reg ^= mask;
3767 TAL_CRITICAL_SECTION_LEAVE();
3768 }
3769
hri_tal_read_INTCPUSEL1_reg(const void * const hw)3770 static inline hri_tal_intcpusel1_reg_t hri_tal_read_INTCPUSEL1_reg(const void *const hw)
3771 {
3772 return ((Tal *)hw)->INTCPUSEL1.reg;
3773 }
3774
hri_tal_set_IRQTRIG_ENABLE_bit(const void * const hw)3775 static inline void hri_tal_set_IRQTRIG_ENABLE_bit(const void *const hw)
3776 {
3777 TAL_CRITICAL_SECTION_ENTER();
3778 ((Tal *)hw)->IRQTRIG.reg |= TAL_IRQTRIG_ENABLE;
3779 TAL_CRITICAL_SECTION_LEAVE();
3780 }
3781
hri_tal_get_IRQTRIG_ENABLE_bit(const void * const hw)3782 static inline bool hri_tal_get_IRQTRIG_ENABLE_bit(const void *const hw)
3783 {
3784 uint16_t tmp;
3785 tmp = ((Tal *)hw)->IRQTRIG.reg;
3786 tmp = (tmp & TAL_IRQTRIG_ENABLE) >> TAL_IRQTRIG_ENABLE_Pos;
3787 return (bool)tmp;
3788 }
3789
hri_tal_write_IRQTRIG_ENABLE_bit(const void * const hw,bool value)3790 static inline void hri_tal_write_IRQTRIG_ENABLE_bit(const void *const hw, bool value)
3791 {
3792 uint16_t tmp;
3793 TAL_CRITICAL_SECTION_ENTER();
3794 tmp = ((Tal *)hw)->IRQTRIG.reg;
3795 tmp &= ~TAL_IRQTRIG_ENABLE;
3796 tmp |= value << TAL_IRQTRIG_ENABLE_Pos;
3797 ((Tal *)hw)->IRQTRIG.reg = tmp;
3798 TAL_CRITICAL_SECTION_LEAVE();
3799 }
3800
hri_tal_clear_IRQTRIG_ENABLE_bit(const void * const hw)3801 static inline void hri_tal_clear_IRQTRIG_ENABLE_bit(const void *const hw)
3802 {
3803 TAL_CRITICAL_SECTION_ENTER();
3804 ((Tal *)hw)->IRQTRIG.reg &= ~TAL_IRQTRIG_ENABLE;
3805 TAL_CRITICAL_SECTION_LEAVE();
3806 }
3807
hri_tal_toggle_IRQTRIG_ENABLE_bit(const void * const hw)3808 static inline void hri_tal_toggle_IRQTRIG_ENABLE_bit(const void *const hw)
3809 {
3810 TAL_CRITICAL_SECTION_ENTER();
3811 ((Tal *)hw)->IRQTRIG.reg ^= TAL_IRQTRIG_ENABLE;
3812 TAL_CRITICAL_SECTION_LEAVE();
3813 }
3814
hri_tal_set_IRQTRIG_IRQNUM_bf(const void * const hw,hri_tal_irqtrig_reg_t mask)3815 static inline void hri_tal_set_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask)
3816 {
3817 TAL_CRITICAL_SECTION_ENTER();
3818 ((Tal *)hw)->IRQTRIG.reg |= TAL_IRQTRIG_IRQNUM(mask);
3819 TAL_CRITICAL_SECTION_LEAVE();
3820 }
3821
hri_tal_get_IRQTRIG_IRQNUM_bf(const void * const hw,hri_tal_irqtrig_reg_t mask)3822 static inline hri_tal_irqtrig_reg_t hri_tal_get_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask)
3823 {
3824 uint16_t tmp;
3825 tmp = ((Tal *)hw)->IRQTRIG.reg;
3826 tmp = (tmp & TAL_IRQTRIG_IRQNUM(mask)) >> TAL_IRQTRIG_IRQNUM_Pos;
3827 return tmp;
3828 }
3829
hri_tal_write_IRQTRIG_IRQNUM_bf(const void * const hw,hri_tal_irqtrig_reg_t data)3830 static inline void hri_tal_write_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t data)
3831 {
3832 uint16_t tmp;
3833 TAL_CRITICAL_SECTION_ENTER();
3834 tmp = ((Tal *)hw)->IRQTRIG.reg;
3835 tmp &= ~TAL_IRQTRIG_IRQNUM_Msk;
3836 tmp |= TAL_IRQTRIG_IRQNUM(data);
3837 ((Tal *)hw)->IRQTRIG.reg = tmp;
3838 TAL_CRITICAL_SECTION_LEAVE();
3839 }
3840
hri_tal_clear_IRQTRIG_IRQNUM_bf(const void * const hw,hri_tal_irqtrig_reg_t mask)3841 static inline void hri_tal_clear_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask)
3842 {
3843 TAL_CRITICAL_SECTION_ENTER();
3844 ((Tal *)hw)->IRQTRIG.reg &= ~TAL_IRQTRIG_IRQNUM(mask);
3845 TAL_CRITICAL_SECTION_LEAVE();
3846 }
3847
hri_tal_toggle_IRQTRIG_IRQNUM_bf(const void * const hw,hri_tal_irqtrig_reg_t mask)3848 static inline void hri_tal_toggle_IRQTRIG_IRQNUM_bf(const void *const hw, hri_tal_irqtrig_reg_t mask)
3849 {
3850 TAL_CRITICAL_SECTION_ENTER();
3851 ((Tal *)hw)->IRQTRIG.reg ^= TAL_IRQTRIG_IRQNUM(mask);
3852 TAL_CRITICAL_SECTION_LEAVE();
3853 }
3854
hri_tal_read_IRQTRIG_IRQNUM_bf(const void * const hw)3855 static inline hri_tal_irqtrig_reg_t hri_tal_read_IRQTRIG_IRQNUM_bf(const void *const hw)
3856 {
3857 uint16_t tmp;
3858 tmp = ((Tal *)hw)->IRQTRIG.reg;
3859 tmp = (tmp & TAL_IRQTRIG_IRQNUM_Msk) >> TAL_IRQTRIG_IRQNUM_Pos;
3860 return tmp;
3861 }
3862
hri_tal_set_IRQTRIG_OVERRIDE_bf(const void * const hw,hri_tal_irqtrig_reg_t mask)3863 static inline void hri_tal_set_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask)
3864 {
3865 TAL_CRITICAL_SECTION_ENTER();
3866 ((Tal *)hw)->IRQTRIG.reg |= TAL_IRQTRIG_OVERRIDE(mask);
3867 TAL_CRITICAL_SECTION_LEAVE();
3868 }
3869
hri_tal_get_IRQTRIG_OVERRIDE_bf(const void * const hw,hri_tal_irqtrig_reg_t mask)3870 static inline hri_tal_irqtrig_reg_t hri_tal_get_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask)
3871 {
3872 uint16_t tmp;
3873 tmp = ((Tal *)hw)->IRQTRIG.reg;
3874 tmp = (tmp & TAL_IRQTRIG_OVERRIDE(mask)) >> TAL_IRQTRIG_OVERRIDE_Pos;
3875 return tmp;
3876 }
3877
hri_tal_write_IRQTRIG_OVERRIDE_bf(const void * const hw,hri_tal_irqtrig_reg_t data)3878 static inline void hri_tal_write_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t data)
3879 {
3880 uint16_t tmp;
3881 TAL_CRITICAL_SECTION_ENTER();
3882 tmp = ((Tal *)hw)->IRQTRIG.reg;
3883 tmp &= ~TAL_IRQTRIG_OVERRIDE_Msk;
3884 tmp |= TAL_IRQTRIG_OVERRIDE(data);
3885 ((Tal *)hw)->IRQTRIG.reg = tmp;
3886 TAL_CRITICAL_SECTION_LEAVE();
3887 }
3888
hri_tal_clear_IRQTRIG_OVERRIDE_bf(const void * const hw,hri_tal_irqtrig_reg_t mask)3889 static inline void hri_tal_clear_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask)
3890 {
3891 TAL_CRITICAL_SECTION_ENTER();
3892 ((Tal *)hw)->IRQTRIG.reg &= ~TAL_IRQTRIG_OVERRIDE(mask);
3893 TAL_CRITICAL_SECTION_LEAVE();
3894 }
3895
hri_tal_toggle_IRQTRIG_OVERRIDE_bf(const void * const hw,hri_tal_irqtrig_reg_t mask)3896 static inline void hri_tal_toggle_IRQTRIG_OVERRIDE_bf(const void *const hw, hri_tal_irqtrig_reg_t mask)
3897 {
3898 TAL_CRITICAL_SECTION_ENTER();
3899 ((Tal *)hw)->IRQTRIG.reg ^= TAL_IRQTRIG_OVERRIDE(mask);
3900 TAL_CRITICAL_SECTION_LEAVE();
3901 }
3902
hri_tal_read_IRQTRIG_OVERRIDE_bf(const void * const hw)3903 static inline hri_tal_irqtrig_reg_t hri_tal_read_IRQTRIG_OVERRIDE_bf(const void *const hw)
3904 {
3905 uint16_t tmp;
3906 tmp = ((Tal *)hw)->IRQTRIG.reg;
3907 tmp = (tmp & TAL_IRQTRIG_OVERRIDE_Msk) >> TAL_IRQTRIG_OVERRIDE_Pos;
3908 return tmp;
3909 }
3910
hri_tal_set_IRQTRIG_reg(const void * const hw,hri_tal_irqtrig_reg_t mask)3911 static inline void hri_tal_set_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask)
3912 {
3913 TAL_CRITICAL_SECTION_ENTER();
3914 ((Tal *)hw)->IRQTRIG.reg |= mask;
3915 TAL_CRITICAL_SECTION_LEAVE();
3916 }
3917
hri_tal_get_IRQTRIG_reg(const void * const hw,hri_tal_irqtrig_reg_t mask)3918 static inline hri_tal_irqtrig_reg_t hri_tal_get_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask)
3919 {
3920 uint16_t tmp;
3921 tmp = ((Tal *)hw)->IRQTRIG.reg;
3922 tmp &= mask;
3923 return tmp;
3924 }
3925
hri_tal_write_IRQTRIG_reg(const void * const hw,hri_tal_irqtrig_reg_t data)3926 static inline void hri_tal_write_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t data)
3927 {
3928 TAL_CRITICAL_SECTION_ENTER();
3929 ((Tal *)hw)->IRQTRIG.reg = data;
3930 TAL_CRITICAL_SECTION_LEAVE();
3931 }
3932
hri_tal_clear_IRQTRIG_reg(const void * const hw,hri_tal_irqtrig_reg_t mask)3933 static inline void hri_tal_clear_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask)
3934 {
3935 TAL_CRITICAL_SECTION_ENTER();
3936 ((Tal *)hw)->IRQTRIG.reg &= ~mask;
3937 TAL_CRITICAL_SECTION_LEAVE();
3938 }
3939
hri_tal_toggle_IRQTRIG_reg(const void * const hw,hri_tal_irqtrig_reg_t mask)3940 static inline void hri_tal_toggle_IRQTRIG_reg(const void *const hw, hri_tal_irqtrig_reg_t mask)
3941 {
3942 TAL_CRITICAL_SECTION_ENTER();
3943 ((Tal *)hw)->IRQTRIG.reg ^= mask;
3944 TAL_CRITICAL_SECTION_LEAVE();
3945 }
3946
hri_tal_read_IRQTRIG_reg(const void * const hw)3947 static inline hri_tal_irqtrig_reg_t hri_tal_read_IRQTRIG_reg(const void *const hw)
3948 {
3949 return ((Tal *)hw)->IRQTRIG.reg;
3950 }
3951
hri_tal_get_BRKSTATUS_CM0P_bf(const void * const hw,hri_tal_brkstatus_reg_t mask)3952 static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_CM0P_bf(const void *const hw, hri_tal_brkstatus_reg_t mask)
3953 {
3954 return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_CM0P(mask)) >> TAL_BRKSTATUS_CM0P_Pos;
3955 }
3956
hri_tal_read_BRKSTATUS_CM0P_bf(const void * const hw)3957 static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_CM0P_bf(const void *const hw)
3958 {
3959 return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_CM0P_Msk) >> TAL_BRKSTATUS_CM0P_Pos;
3960 }
3961
hri_tal_get_BRKSTATUS_PPP_bf(const void * const hw,hri_tal_brkstatus_reg_t mask)3962 static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_PPP_bf(const void *const hw, hri_tal_brkstatus_reg_t mask)
3963 {
3964 return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_PPP(mask)) >> TAL_BRKSTATUS_PPP_Pos;
3965 }
3966
hri_tal_read_BRKSTATUS_PPP_bf(const void * const hw)3967 static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_PPP_bf(const void *const hw)
3968 {
3969 return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_PPP_Msk) >> TAL_BRKSTATUS_PPP_Pos;
3970 }
3971
hri_tal_get_BRKSTATUS_EVBRK_bf(const void * const hw,hri_tal_brkstatus_reg_t mask)3972 static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_EVBRK_bf(const void *const hw, hri_tal_brkstatus_reg_t mask)
3973 {
3974 return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EVBRK(mask)) >> TAL_BRKSTATUS_EVBRK_Pos;
3975 }
3976
hri_tal_read_BRKSTATUS_EVBRK_bf(const void * const hw)3977 static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_EVBRK_bf(const void *const hw)
3978 {
3979 return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EVBRK_Msk) >> TAL_BRKSTATUS_EVBRK_Pos;
3980 }
3981
hri_tal_get_BRKSTATUS_EXTBRK_bf(const void * const hw,hri_tal_brkstatus_reg_t mask)3982 static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_EXTBRK_bf(const void *const hw,
3983 hri_tal_brkstatus_reg_t mask)
3984 {
3985 return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EXTBRK(mask)) >> TAL_BRKSTATUS_EXTBRK_Pos;
3986 }
3987
hri_tal_read_BRKSTATUS_EXTBRK_bf(const void * const hw)3988 static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_EXTBRK_bf(const void *const hw)
3989 {
3990 return (((Tal *)hw)->BRKSTATUS.reg & TAL_BRKSTATUS_EXTBRK_Msk) >> TAL_BRKSTATUS_EXTBRK_Pos;
3991 }
3992
hri_tal_get_BRKSTATUS_reg(const void * const hw,hri_tal_brkstatus_reg_t mask)3993 static inline hri_tal_brkstatus_reg_t hri_tal_get_BRKSTATUS_reg(const void *const hw, hri_tal_brkstatus_reg_t mask)
3994 {
3995 uint16_t tmp;
3996 tmp = ((Tal *)hw)->BRKSTATUS.reg;
3997 tmp &= mask;
3998 return tmp;
3999 }
4000
hri_tal_read_BRKSTATUS_reg(const void * const hw)4001 static inline hri_tal_brkstatus_reg_t hri_tal_read_BRKSTATUS_reg(const void *const hw)
4002 {
4003 return ((Tal *)hw)->BRKSTATUS.reg;
4004 }
4005
hri_tal_get_INTSTATUS_IRQ0_bit(const void * const hw,uint8_t index)4006 static inline bool hri_tal_get_INTSTATUS_IRQ0_bit(const void *const hw, uint8_t index)
4007 {
4008 return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ0) >> TAL_INTSTATUS_IRQ0_Pos;
4009 }
4010
hri_tal_get_INTSTATUS_IRQ1_bit(const void * const hw,uint8_t index)4011 static inline bool hri_tal_get_INTSTATUS_IRQ1_bit(const void *const hw, uint8_t index)
4012 {
4013 return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ1) >> TAL_INTSTATUS_IRQ1_Pos;
4014 }
4015
hri_tal_get_INTSTATUS_IRQ2_bit(const void * const hw,uint8_t index)4016 static inline bool hri_tal_get_INTSTATUS_IRQ2_bit(const void *const hw, uint8_t index)
4017 {
4018 return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ2) >> TAL_INTSTATUS_IRQ2_Pos;
4019 }
4020
hri_tal_get_INTSTATUS_IRQ3_bit(const void * const hw,uint8_t index)4021 static inline bool hri_tal_get_INTSTATUS_IRQ3_bit(const void *const hw, uint8_t index)
4022 {
4023 return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ3) >> TAL_INTSTATUS_IRQ3_Pos;
4024 }
4025
hri_tal_get_INTSTATUS_IRQ4_bit(const void * const hw,uint8_t index)4026 static inline bool hri_tal_get_INTSTATUS_IRQ4_bit(const void *const hw, uint8_t index)
4027 {
4028 return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ4) >> TAL_INTSTATUS_IRQ4_Pos;
4029 }
4030
hri_tal_get_INTSTATUS_IRQ5_bit(const void * const hw,uint8_t index)4031 static inline bool hri_tal_get_INTSTATUS_IRQ5_bit(const void *const hw, uint8_t index)
4032 {
4033 return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ5) >> TAL_INTSTATUS_IRQ5_Pos;
4034 }
4035
hri_tal_get_INTSTATUS_IRQ6_bit(const void * const hw,uint8_t index)4036 static inline bool hri_tal_get_INTSTATUS_IRQ6_bit(const void *const hw, uint8_t index)
4037 {
4038 return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ6) >> TAL_INTSTATUS_IRQ6_Pos;
4039 }
4040
hri_tal_get_INTSTATUS_IRQ7_bit(const void * const hw,uint8_t index)4041 static inline bool hri_tal_get_INTSTATUS_IRQ7_bit(const void *const hw, uint8_t index)
4042 {
4043 return (((Tal *)hw)->INTSTATUS[index].reg & TAL_INTSTATUS_IRQ7) >> TAL_INTSTATUS_IRQ7_Pos;
4044 }
4045
hri_tal_get_INTSTATUS_reg(const void * const hw,uint8_t index,hri_tal_intstatus_reg_t mask)4046 static inline hri_tal_intstatus_reg_t hri_tal_get_INTSTATUS_reg(const void *const hw, uint8_t index,
4047 hri_tal_intstatus_reg_t mask)
4048 {
4049 uint8_t tmp;
4050 tmp = ((Tal *)hw)->INTSTATUS[index].reg;
4051 tmp &= mask;
4052 return tmp;
4053 }
4054
hri_tal_read_INTSTATUS_reg(const void * const hw,uint8_t index)4055 static inline hri_tal_intstatus_reg_t hri_tal_read_INTSTATUS_reg(const void *const hw, uint8_t index)
4056 {
4057 return ((Tal *)hw)->INTSTATUS[index].reg;
4058 }
4059
hri_tal_get_CPUIRQS_CPUIRQS_bf(const void * const hw,uint8_t index,hri_tal_cpuirqs_reg_t mask)4060 static inline hri_tal_cpuirqs_reg_t hri_tal_get_CPUIRQS_CPUIRQS_bf(const void *const hw, uint8_t index,
4061 hri_tal_cpuirqs_reg_t mask)
4062 {
4063 return (((Tal *)hw)->CPUIRQS[index].reg & TAL_CPUIRQS_CPUIRQS(mask)) >> TAL_CPUIRQS_CPUIRQS_Pos;
4064 }
4065
hri_tal_read_CPUIRQS_CPUIRQS_bf(const void * const hw,uint8_t index)4066 static inline hri_tal_cpuirqs_reg_t hri_tal_read_CPUIRQS_CPUIRQS_bf(const void *const hw, uint8_t index)
4067 {
4068 return (((Tal *)hw)->CPUIRQS[index].reg & TAL_CPUIRQS_CPUIRQS_Msk) >> TAL_CPUIRQS_CPUIRQS_Pos;
4069 }
4070
hri_tal_get_CPUIRQS_reg(const void * const hw,uint8_t index,hri_tal_cpuirqs_reg_t mask)4071 static inline hri_tal_cpuirqs_reg_t hri_tal_get_CPUIRQS_reg(const void *const hw, uint8_t index,
4072 hri_tal_cpuirqs_reg_t mask)
4073 {
4074 uint32_t tmp;
4075 tmp = ((Tal *)hw)->CPUIRQS[index].reg;
4076 tmp &= mask;
4077 return tmp;
4078 }
4079
hri_tal_read_CPUIRQS_reg(const void * const hw,uint8_t index)4080 static inline hri_tal_cpuirqs_reg_t hri_tal_read_CPUIRQS_reg(const void *const hw, uint8_t index)
4081 {
4082 return ((Tal *)hw)->CPUIRQS[index].reg;
4083 }
4084
hri_talctis_set_CTICTRLA_RESTART_bit(const void * const hw)4085 static inline void hri_talctis_set_CTICTRLA_RESTART_bit(const void *const hw)
4086 {
4087 TAL_CRITICAL_SECTION_ENTER();
4088 ((TalCtis *)hw)->CTICTRLA.reg |= TAL_CTICTRLA_RESTART;
4089 TAL_CRITICAL_SECTION_LEAVE();
4090 }
4091
hri_talctis_get_CTICTRLA_RESTART_bit(const void * const hw)4092 static inline bool hri_talctis_get_CTICTRLA_RESTART_bit(const void *const hw)
4093 {
4094 uint8_t tmp;
4095 tmp = ((TalCtis *)hw)->CTICTRLA.reg;
4096 tmp = (tmp & TAL_CTICTRLA_RESTART) >> TAL_CTICTRLA_RESTART_Pos;
4097 return (bool)tmp;
4098 }
4099
hri_talctis_write_CTICTRLA_RESTART_bit(const void * const hw,bool value)4100 static inline void hri_talctis_write_CTICTRLA_RESTART_bit(const void *const hw, bool value)
4101 {
4102 uint8_t tmp;
4103 TAL_CRITICAL_SECTION_ENTER();
4104 tmp = ((TalCtis *)hw)->CTICTRLA.reg;
4105 tmp &= ~TAL_CTICTRLA_RESTART;
4106 tmp |= value << TAL_CTICTRLA_RESTART_Pos;
4107 ((TalCtis *)hw)->CTICTRLA.reg = tmp;
4108 TAL_CRITICAL_SECTION_LEAVE();
4109 }
4110
hri_talctis_clear_CTICTRLA_RESTART_bit(const void * const hw)4111 static inline void hri_talctis_clear_CTICTRLA_RESTART_bit(const void *const hw)
4112 {
4113 TAL_CRITICAL_SECTION_ENTER();
4114 ((TalCtis *)hw)->CTICTRLA.reg &= ~TAL_CTICTRLA_RESTART;
4115 TAL_CRITICAL_SECTION_LEAVE();
4116 }
4117
hri_talctis_toggle_CTICTRLA_RESTART_bit(const void * const hw)4118 static inline void hri_talctis_toggle_CTICTRLA_RESTART_bit(const void *const hw)
4119 {
4120 TAL_CRITICAL_SECTION_ENTER();
4121 ((TalCtis *)hw)->CTICTRLA.reg ^= TAL_CTICTRLA_RESTART;
4122 TAL_CRITICAL_SECTION_LEAVE();
4123 }
4124
hri_talctis_set_CTICTRLA_ACTION_bf(const void * const hw,hri_tal_ctictrla_reg_t mask)4125 static inline void hri_talctis_set_CTICTRLA_ACTION_bf(const void *const hw, hri_tal_ctictrla_reg_t mask)
4126 {
4127 TAL_CRITICAL_SECTION_ENTER();
4128 ((TalCtis *)hw)->CTICTRLA.reg |= TAL_CTICTRLA_ACTION(mask);
4129 TAL_CRITICAL_SECTION_LEAVE();
4130 }
4131
hri_talctis_get_CTICTRLA_ACTION_bf(const void * const hw,hri_tal_ctictrla_reg_t mask)4132 static inline hri_tal_ctictrla_reg_t hri_talctis_get_CTICTRLA_ACTION_bf(const void *const hw,
4133 hri_tal_ctictrla_reg_t mask)
4134 {
4135 uint8_t tmp;
4136 tmp = ((TalCtis *)hw)->CTICTRLA.reg;
4137 tmp = (tmp & TAL_CTICTRLA_ACTION(mask)) >> TAL_CTICTRLA_ACTION_Pos;
4138 return tmp;
4139 }
4140
hri_talctis_write_CTICTRLA_ACTION_bf(const void * const hw,hri_tal_ctictrla_reg_t data)4141 static inline void hri_talctis_write_CTICTRLA_ACTION_bf(const void *const hw, hri_tal_ctictrla_reg_t data)
4142 {
4143 uint8_t tmp;
4144 TAL_CRITICAL_SECTION_ENTER();
4145 tmp = ((TalCtis *)hw)->CTICTRLA.reg;
4146 tmp &= ~TAL_CTICTRLA_ACTION_Msk;
4147 tmp |= TAL_CTICTRLA_ACTION(data);
4148 ((TalCtis *)hw)->CTICTRLA.reg = tmp;
4149 TAL_CRITICAL_SECTION_LEAVE();
4150 }
4151
hri_talctis_clear_CTICTRLA_ACTION_bf(const void * const hw,hri_tal_ctictrla_reg_t mask)4152 static inline void hri_talctis_clear_CTICTRLA_ACTION_bf(const void *const hw, hri_tal_ctictrla_reg_t mask)
4153 {
4154 TAL_CRITICAL_SECTION_ENTER();
4155 ((TalCtis *)hw)->CTICTRLA.reg &= ~TAL_CTICTRLA_ACTION(mask);
4156 TAL_CRITICAL_SECTION_LEAVE();
4157 }
4158
hri_talctis_toggle_CTICTRLA_ACTION_bf(const void * const hw,hri_tal_ctictrla_reg_t mask)4159 static inline void hri_talctis_toggle_CTICTRLA_ACTION_bf(const void *const hw, hri_tal_ctictrla_reg_t mask)
4160 {
4161 TAL_CRITICAL_SECTION_ENTER();
4162 ((TalCtis *)hw)->CTICTRLA.reg ^= TAL_CTICTRLA_ACTION(mask);
4163 TAL_CRITICAL_SECTION_LEAVE();
4164 }
4165
hri_talctis_read_CTICTRLA_ACTION_bf(const void * const hw)4166 static inline hri_tal_ctictrla_reg_t hri_talctis_read_CTICTRLA_ACTION_bf(const void *const hw)
4167 {
4168 uint8_t tmp;
4169 tmp = ((TalCtis *)hw)->CTICTRLA.reg;
4170 tmp = (tmp & TAL_CTICTRLA_ACTION_Msk) >> TAL_CTICTRLA_ACTION_Pos;
4171 return tmp;
4172 }
4173
hri_talctis_set_CTICTRLA_reg(const void * const hw,hri_tal_ctictrla_reg_t mask)4174 static inline void hri_talctis_set_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask)
4175 {
4176 TAL_CRITICAL_SECTION_ENTER();
4177 ((TalCtis *)hw)->CTICTRLA.reg |= mask;
4178 TAL_CRITICAL_SECTION_LEAVE();
4179 }
4180
hri_talctis_get_CTICTRLA_reg(const void * const hw,hri_tal_ctictrla_reg_t mask)4181 static inline hri_tal_ctictrla_reg_t hri_talctis_get_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask)
4182 {
4183 uint8_t tmp;
4184 tmp = ((TalCtis *)hw)->CTICTRLA.reg;
4185 tmp &= mask;
4186 return tmp;
4187 }
4188
hri_talctis_write_CTICTRLA_reg(const void * const hw,hri_tal_ctictrla_reg_t data)4189 static inline void hri_talctis_write_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t data)
4190 {
4191 TAL_CRITICAL_SECTION_ENTER();
4192 ((TalCtis *)hw)->CTICTRLA.reg = data;
4193 TAL_CRITICAL_SECTION_LEAVE();
4194 }
4195
hri_talctis_clear_CTICTRLA_reg(const void * const hw,hri_tal_ctictrla_reg_t mask)4196 static inline void hri_talctis_clear_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask)
4197 {
4198 TAL_CRITICAL_SECTION_ENTER();
4199 ((TalCtis *)hw)->CTICTRLA.reg &= ~mask;
4200 TAL_CRITICAL_SECTION_LEAVE();
4201 }
4202
hri_talctis_toggle_CTICTRLA_reg(const void * const hw,hri_tal_ctictrla_reg_t mask)4203 static inline void hri_talctis_toggle_CTICTRLA_reg(const void *const hw, hri_tal_ctictrla_reg_t mask)
4204 {
4205 TAL_CRITICAL_SECTION_ENTER();
4206 ((TalCtis *)hw)->CTICTRLA.reg ^= mask;
4207 TAL_CRITICAL_SECTION_LEAVE();
4208 }
4209
hri_talctis_read_CTICTRLA_reg(const void * const hw)4210 static inline hri_tal_ctictrla_reg_t hri_talctis_read_CTICTRLA_reg(const void *const hw)
4211 {
4212 return ((TalCtis *)hw)->CTICTRLA.reg;
4213 }
4214
hri_talctis_set_CTIMASK_CM0P_bit(const void * const hw)4215 static inline void hri_talctis_set_CTIMASK_CM0P_bit(const void *const hw)
4216 {
4217 TAL_CRITICAL_SECTION_ENTER();
4218 ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_CM0P;
4219 TAL_CRITICAL_SECTION_LEAVE();
4220 }
4221
hri_talctis_get_CTIMASK_CM0P_bit(const void * const hw)4222 static inline bool hri_talctis_get_CTIMASK_CM0P_bit(const void *const hw)
4223 {
4224 uint8_t tmp;
4225 tmp = ((TalCtis *)hw)->CTIMASK.reg;
4226 tmp = (tmp & TAL_CTIMASK_CM0P) >> TAL_CTIMASK_CM0P_Pos;
4227 return (bool)tmp;
4228 }
4229
hri_talctis_write_CTIMASK_CM0P_bit(const void * const hw,bool value)4230 static inline void hri_talctis_write_CTIMASK_CM0P_bit(const void *const hw, bool value)
4231 {
4232 uint8_t tmp;
4233 TAL_CRITICAL_SECTION_ENTER();
4234 tmp = ((TalCtis *)hw)->CTIMASK.reg;
4235 tmp &= ~TAL_CTIMASK_CM0P;
4236 tmp |= value << TAL_CTIMASK_CM0P_Pos;
4237 ((TalCtis *)hw)->CTIMASK.reg = tmp;
4238 TAL_CRITICAL_SECTION_LEAVE();
4239 }
4240
hri_talctis_clear_CTIMASK_CM0P_bit(const void * const hw)4241 static inline void hri_talctis_clear_CTIMASK_CM0P_bit(const void *const hw)
4242 {
4243 TAL_CRITICAL_SECTION_ENTER();
4244 ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_CM0P;
4245 TAL_CRITICAL_SECTION_LEAVE();
4246 }
4247
hri_talctis_toggle_CTIMASK_CM0P_bit(const void * const hw)4248 static inline void hri_talctis_toggle_CTIMASK_CM0P_bit(const void *const hw)
4249 {
4250 TAL_CRITICAL_SECTION_ENTER();
4251 ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_CM0P;
4252 TAL_CRITICAL_SECTION_LEAVE();
4253 }
4254
hri_talctis_set_CTIMASK_PPP_bit(const void * const hw)4255 static inline void hri_talctis_set_CTIMASK_PPP_bit(const void *const hw)
4256 {
4257 TAL_CRITICAL_SECTION_ENTER();
4258 ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_PPP;
4259 TAL_CRITICAL_SECTION_LEAVE();
4260 }
4261
hri_talctis_get_CTIMASK_PPP_bit(const void * const hw)4262 static inline bool hri_talctis_get_CTIMASK_PPP_bit(const void *const hw)
4263 {
4264 uint8_t tmp;
4265 tmp = ((TalCtis *)hw)->CTIMASK.reg;
4266 tmp = (tmp & TAL_CTIMASK_PPP) >> TAL_CTIMASK_PPP_Pos;
4267 return (bool)tmp;
4268 }
4269
hri_talctis_write_CTIMASK_PPP_bit(const void * const hw,bool value)4270 static inline void hri_talctis_write_CTIMASK_PPP_bit(const void *const hw, bool value)
4271 {
4272 uint8_t tmp;
4273 TAL_CRITICAL_SECTION_ENTER();
4274 tmp = ((TalCtis *)hw)->CTIMASK.reg;
4275 tmp &= ~TAL_CTIMASK_PPP;
4276 tmp |= value << TAL_CTIMASK_PPP_Pos;
4277 ((TalCtis *)hw)->CTIMASK.reg = tmp;
4278 TAL_CRITICAL_SECTION_LEAVE();
4279 }
4280
hri_talctis_clear_CTIMASK_PPP_bit(const void * const hw)4281 static inline void hri_talctis_clear_CTIMASK_PPP_bit(const void *const hw)
4282 {
4283 TAL_CRITICAL_SECTION_ENTER();
4284 ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_PPP;
4285 TAL_CRITICAL_SECTION_LEAVE();
4286 }
4287
hri_talctis_toggle_CTIMASK_PPP_bit(const void * const hw)4288 static inline void hri_talctis_toggle_CTIMASK_PPP_bit(const void *const hw)
4289 {
4290 TAL_CRITICAL_SECTION_ENTER();
4291 ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_PPP;
4292 TAL_CRITICAL_SECTION_LEAVE();
4293 }
4294
hri_talctis_set_CTIMASK_EVBRK_bit(const void * const hw)4295 static inline void hri_talctis_set_CTIMASK_EVBRK_bit(const void *const hw)
4296 {
4297 TAL_CRITICAL_SECTION_ENTER();
4298 ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_EVBRK;
4299 TAL_CRITICAL_SECTION_LEAVE();
4300 }
4301
hri_talctis_get_CTIMASK_EVBRK_bit(const void * const hw)4302 static inline bool hri_talctis_get_CTIMASK_EVBRK_bit(const void *const hw)
4303 {
4304 uint8_t tmp;
4305 tmp = ((TalCtis *)hw)->CTIMASK.reg;
4306 tmp = (tmp & TAL_CTIMASK_EVBRK) >> TAL_CTIMASK_EVBRK_Pos;
4307 return (bool)tmp;
4308 }
4309
hri_talctis_write_CTIMASK_EVBRK_bit(const void * const hw,bool value)4310 static inline void hri_talctis_write_CTIMASK_EVBRK_bit(const void *const hw, bool value)
4311 {
4312 uint8_t tmp;
4313 TAL_CRITICAL_SECTION_ENTER();
4314 tmp = ((TalCtis *)hw)->CTIMASK.reg;
4315 tmp &= ~TAL_CTIMASK_EVBRK;
4316 tmp |= value << TAL_CTIMASK_EVBRK_Pos;
4317 ((TalCtis *)hw)->CTIMASK.reg = tmp;
4318 TAL_CRITICAL_SECTION_LEAVE();
4319 }
4320
hri_talctis_clear_CTIMASK_EVBRK_bit(const void * const hw)4321 static inline void hri_talctis_clear_CTIMASK_EVBRK_bit(const void *const hw)
4322 {
4323 TAL_CRITICAL_SECTION_ENTER();
4324 ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_EVBRK;
4325 TAL_CRITICAL_SECTION_LEAVE();
4326 }
4327
hri_talctis_toggle_CTIMASK_EVBRK_bit(const void * const hw)4328 static inline void hri_talctis_toggle_CTIMASK_EVBRK_bit(const void *const hw)
4329 {
4330 TAL_CRITICAL_SECTION_ENTER();
4331 ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_EVBRK;
4332 TAL_CRITICAL_SECTION_LEAVE();
4333 }
4334
hri_talctis_set_CTIMASK_EXTBRK_bit(const void * const hw)4335 static inline void hri_talctis_set_CTIMASK_EXTBRK_bit(const void *const hw)
4336 {
4337 TAL_CRITICAL_SECTION_ENTER();
4338 ((TalCtis *)hw)->CTIMASK.reg |= TAL_CTIMASK_EXTBRK;
4339 TAL_CRITICAL_SECTION_LEAVE();
4340 }
4341
hri_talctis_get_CTIMASK_EXTBRK_bit(const void * const hw)4342 static inline bool hri_talctis_get_CTIMASK_EXTBRK_bit(const void *const hw)
4343 {
4344 uint8_t tmp;
4345 tmp = ((TalCtis *)hw)->CTIMASK.reg;
4346 tmp = (tmp & TAL_CTIMASK_EXTBRK) >> TAL_CTIMASK_EXTBRK_Pos;
4347 return (bool)tmp;
4348 }
4349
hri_talctis_write_CTIMASK_EXTBRK_bit(const void * const hw,bool value)4350 static inline void hri_talctis_write_CTIMASK_EXTBRK_bit(const void *const hw, bool value)
4351 {
4352 uint8_t tmp;
4353 TAL_CRITICAL_SECTION_ENTER();
4354 tmp = ((TalCtis *)hw)->CTIMASK.reg;
4355 tmp &= ~TAL_CTIMASK_EXTBRK;
4356 tmp |= value << TAL_CTIMASK_EXTBRK_Pos;
4357 ((TalCtis *)hw)->CTIMASK.reg = tmp;
4358 TAL_CRITICAL_SECTION_LEAVE();
4359 }
4360
hri_talctis_clear_CTIMASK_EXTBRK_bit(const void * const hw)4361 static inline void hri_talctis_clear_CTIMASK_EXTBRK_bit(const void *const hw)
4362 {
4363 TAL_CRITICAL_SECTION_ENTER();
4364 ((TalCtis *)hw)->CTIMASK.reg &= ~TAL_CTIMASK_EXTBRK;
4365 TAL_CRITICAL_SECTION_LEAVE();
4366 }
4367
hri_talctis_toggle_CTIMASK_EXTBRK_bit(const void * const hw)4368 static inline void hri_talctis_toggle_CTIMASK_EXTBRK_bit(const void *const hw)
4369 {
4370 TAL_CRITICAL_SECTION_ENTER();
4371 ((TalCtis *)hw)->CTIMASK.reg ^= TAL_CTIMASK_EXTBRK;
4372 TAL_CRITICAL_SECTION_LEAVE();
4373 }
4374
hri_talctis_set_CTIMASK_reg(const void * const hw,hri_tal_ctimask_reg_t mask)4375 static inline void hri_talctis_set_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask)
4376 {
4377 TAL_CRITICAL_SECTION_ENTER();
4378 ((TalCtis *)hw)->CTIMASK.reg |= mask;
4379 TAL_CRITICAL_SECTION_LEAVE();
4380 }
4381
hri_talctis_get_CTIMASK_reg(const void * const hw,hri_tal_ctimask_reg_t mask)4382 static inline hri_tal_ctimask_reg_t hri_talctis_get_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask)
4383 {
4384 uint8_t tmp;
4385 tmp = ((TalCtis *)hw)->CTIMASK.reg;
4386 tmp &= mask;
4387 return tmp;
4388 }
4389
hri_talctis_write_CTIMASK_reg(const void * const hw,hri_tal_ctimask_reg_t data)4390 static inline void hri_talctis_write_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t data)
4391 {
4392 TAL_CRITICAL_SECTION_ENTER();
4393 ((TalCtis *)hw)->CTIMASK.reg = data;
4394 TAL_CRITICAL_SECTION_LEAVE();
4395 }
4396
hri_talctis_clear_CTIMASK_reg(const void * const hw,hri_tal_ctimask_reg_t mask)4397 static inline void hri_talctis_clear_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask)
4398 {
4399 TAL_CRITICAL_SECTION_ENTER();
4400 ((TalCtis *)hw)->CTIMASK.reg &= ~mask;
4401 TAL_CRITICAL_SECTION_LEAVE();
4402 }
4403
hri_talctis_toggle_CTIMASK_reg(const void * const hw,hri_tal_ctimask_reg_t mask)4404 static inline void hri_talctis_toggle_CTIMASK_reg(const void *const hw, hri_tal_ctimask_reg_t mask)
4405 {
4406 TAL_CRITICAL_SECTION_ENTER();
4407 ((TalCtis *)hw)->CTIMASK.reg ^= mask;
4408 TAL_CRITICAL_SECTION_LEAVE();
4409 }
4410
hri_talctis_read_CTIMASK_reg(const void * const hw)4411 static inline hri_tal_ctimask_reg_t hri_talctis_read_CTIMASK_reg(const void *const hw)
4412 {
4413 return ((TalCtis *)hw)->CTIMASK.reg;
4414 }
4415
hri_tal_set_CTICTRLA_RESTART_bit(const void * const hw,uint8_t submodule_index)4416 static inline void hri_tal_set_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index)
4417 {
4418 TAL_CRITICAL_SECTION_ENTER();
4419 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= TAL_CTICTRLA_RESTART;
4420 TAL_CRITICAL_SECTION_LEAVE();
4421 }
4422
hri_tal_get_CTICTRLA_RESTART_bit(const void * const hw,uint8_t submodule_index)4423 static inline bool hri_tal_get_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index)
4424 {
4425 uint8_t tmp;
4426 tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg;
4427 tmp = (tmp & TAL_CTICTRLA_RESTART) >> TAL_CTICTRLA_RESTART_Pos;
4428 return (bool)tmp;
4429 }
4430
hri_tal_write_CTICTRLA_RESTART_bit(const void * const hw,uint8_t submodule_index,bool value)4431 static inline void hri_tal_write_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index, bool value)
4432 {
4433 uint8_t tmp;
4434 TAL_CRITICAL_SECTION_ENTER();
4435 tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg;
4436 tmp &= ~TAL_CTICTRLA_RESTART;
4437 tmp |= value << TAL_CTICTRLA_RESTART_Pos;
4438 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = tmp;
4439 TAL_CRITICAL_SECTION_LEAVE();
4440 }
4441
hri_tal_clear_CTICTRLA_RESTART_bit(const void * const hw,uint8_t submodule_index)4442 static inline void hri_tal_clear_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index)
4443 {
4444 TAL_CRITICAL_SECTION_ENTER();
4445 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~TAL_CTICTRLA_RESTART;
4446 TAL_CRITICAL_SECTION_LEAVE();
4447 }
4448
hri_tal_toggle_CTICTRLA_RESTART_bit(const void * const hw,uint8_t submodule_index)4449 static inline void hri_tal_toggle_CTICTRLA_RESTART_bit(const void *const hw, uint8_t submodule_index)
4450 {
4451 TAL_CRITICAL_SECTION_ENTER();
4452 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= TAL_CTICTRLA_RESTART;
4453 TAL_CRITICAL_SECTION_LEAVE();
4454 }
4455
hri_tal_set_CTICTRLA_ACTION_bf(const void * const hw,uint8_t submodule_index,hri_tal_ctictrla_reg_t mask)4456 static inline void hri_tal_set_CTICTRLA_ACTION_bf(const void *const hw, uint8_t submodule_index,
4457 hri_tal_ctictrla_reg_t mask)
4458 {
4459 TAL_CRITICAL_SECTION_ENTER();
4460 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= TAL_CTICTRLA_ACTION(mask);
4461 TAL_CRITICAL_SECTION_LEAVE();
4462 }
4463
hri_tal_get_CTICTRLA_ACTION_bf(const void * const hw,uint8_t submodule_index,hri_tal_ctictrla_reg_t mask)4464 static inline hri_tal_ctictrla_reg_t hri_tal_get_CTICTRLA_ACTION_bf(const void *const hw, uint8_t submodule_index,
4465 hri_tal_ctictrla_reg_t mask)
4466 {
4467 uint8_t tmp;
4468 tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg;
4469 tmp = (tmp & TAL_CTICTRLA_ACTION(mask)) >> TAL_CTICTRLA_ACTION_Pos;
4470 return tmp;
4471 }
4472
hri_tal_write_CTICTRLA_ACTION_bf(const void * const hw,uint8_t submodule_index,hri_tal_ctictrla_reg_t data)4473 static inline void hri_tal_write_CTICTRLA_ACTION_bf(const void *const hw, uint8_t submodule_index,
4474 hri_tal_ctictrla_reg_t data)
4475 {
4476 uint8_t tmp;
4477 TAL_CRITICAL_SECTION_ENTER();
4478 tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg;
4479 tmp &= ~TAL_CTICTRLA_ACTION_Msk;
4480 tmp |= TAL_CTICTRLA_ACTION(data);
4481 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = tmp;
4482 TAL_CRITICAL_SECTION_LEAVE();
4483 }
4484
hri_tal_clear_CTICTRLA_ACTION_bf(const void * const hw,uint8_t submodule_index,hri_tal_ctictrla_reg_t mask)4485 static inline void hri_tal_clear_CTICTRLA_ACTION_bf(const void *const hw, uint8_t submodule_index,
4486 hri_tal_ctictrla_reg_t mask)
4487 {
4488 TAL_CRITICAL_SECTION_ENTER();
4489 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~TAL_CTICTRLA_ACTION(mask);
4490 TAL_CRITICAL_SECTION_LEAVE();
4491 }
4492
hri_tal_toggle_CTICTRLA_ACTION_bf(const void * const hw,uint8_t submodule_index,hri_tal_ctictrla_reg_t mask)4493 static inline void hri_tal_toggle_CTICTRLA_ACTION_bf(const void *const hw, uint8_t submodule_index,
4494 hri_tal_ctictrla_reg_t mask)
4495 {
4496 TAL_CRITICAL_SECTION_ENTER();
4497 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= TAL_CTICTRLA_ACTION(mask);
4498 TAL_CRITICAL_SECTION_LEAVE();
4499 }
4500
hri_tal_read_CTICTRLA_ACTION_bf(const void * const hw,uint8_t submodule_index)4501 static inline hri_tal_ctictrla_reg_t hri_tal_read_CTICTRLA_ACTION_bf(const void *const hw, uint8_t submodule_index)
4502 {
4503 uint8_t tmp;
4504 tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg;
4505 tmp = (tmp & TAL_CTICTRLA_ACTION_Msk) >> TAL_CTICTRLA_ACTION_Pos;
4506 return tmp;
4507 }
4508
hri_tal_set_CTICTRLA_reg(const void * const hw,uint8_t submodule_index,hri_tal_ctictrla_reg_t mask)4509 static inline void hri_tal_set_CTICTRLA_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctictrla_reg_t mask)
4510 {
4511 TAL_CRITICAL_SECTION_ENTER();
4512 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg |= mask;
4513 TAL_CRITICAL_SECTION_LEAVE();
4514 }
4515
hri_tal_get_CTICTRLA_reg(const void * const hw,uint8_t submodule_index,hri_tal_ctictrla_reg_t mask)4516 static inline hri_tal_ctictrla_reg_t hri_tal_get_CTICTRLA_reg(const void *const hw, uint8_t submodule_index,
4517 hri_tal_ctictrla_reg_t mask)
4518 {
4519 uint8_t tmp;
4520 tmp = ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg;
4521 tmp &= mask;
4522 return tmp;
4523 }
4524
hri_tal_write_CTICTRLA_reg(const void * const hw,uint8_t submodule_index,hri_tal_ctictrla_reg_t data)4525 static inline void hri_tal_write_CTICTRLA_reg(const void *const hw, uint8_t submodule_index,
4526 hri_tal_ctictrla_reg_t data)
4527 {
4528 TAL_CRITICAL_SECTION_ENTER();
4529 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg = data;
4530 TAL_CRITICAL_SECTION_LEAVE();
4531 }
4532
hri_tal_clear_CTICTRLA_reg(const void * const hw,uint8_t submodule_index,hri_tal_ctictrla_reg_t mask)4533 static inline void hri_tal_clear_CTICTRLA_reg(const void *const hw, uint8_t submodule_index,
4534 hri_tal_ctictrla_reg_t mask)
4535 {
4536 TAL_CRITICAL_SECTION_ENTER();
4537 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg &= ~mask;
4538 TAL_CRITICAL_SECTION_LEAVE();
4539 }
4540
hri_tal_toggle_CTICTRLA_reg(const void * const hw,uint8_t submodule_index,hri_tal_ctictrla_reg_t mask)4541 static inline void hri_tal_toggle_CTICTRLA_reg(const void *const hw, uint8_t submodule_index,
4542 hri_tal_ctictrla_reg_t mask)
4543 {
4544 TAL_CRITICAL_SECTION_ENTER();
4545 ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg ^= mask;
4546 TAL_CRITICAL_SECTION_LEAVE();
4547 }
4548
hri_tal_read_CTICTRLA_reg(const void * const hw,uint8_t submodule_index)4549 static inline hri_tal_ctictrla_reg_t hri_tal_read_CTICTRLA_reg(const void *const hw, uint8_t submodule_index)
4550 {
4551 return ((Tal *)hw)->Ctis[submodule_index].CTICTRLA.reg;
4552 }
4553
hri_tal_set_CTIMASK_CM0P_bit(const void * const hw,uint8_t submodule_index)4554 static inline void hri_tal_set_CTIMASK_CM0P_bit(const void *const hw, uint8_t submodule_index)
4555 {
4556 TAL_CRITICAL_SECTION_ENTER();
4557 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_CM0P;
4558 TAL_CRITICAL_SECTION_LEAVE();
4559 }
4560
hri_tal_get_CTIMASK_CM0P_bit(const void * const hw,uint8_t submodule_index)4561 static inline bool hri_tal_get_CTIMASK_CM0P_bit(const void *const hw, uint8_t submodule_index)
4562 {
4563 uint8_t tmp;
4564 tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg;
4565 tmp = (tmp & TAL_CTIMASK_CM0P) >> TAL_CTIMASK_CM0P_Pos;
4566 return (bool)tmp;
4567 }
4568
hri_tal_write_CTIMASK_CM0P_bit(const void * const hw,uint8_t submodule_index,bool value)4569 static inline void hri_tal_write_CTIMASK_CM0P_bit(const void *const hw, uint8_t submodule_index, bool value)
4570 {
4571 uint8_t tmp;
4572 TAL_CRITICAL_SECTION_ENTER();
4573 tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg;
4574 tmp &= ~TAL_CTIMASK_CM0P;
4575 tmp |= value << TAL_CTIMASK_CM0P_Pos;
4576 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp;
4577 TAL_CRITICAL_SECTION_LEAVE();
4578 }
4579
hri_tal_clear_CTIMASK_CM0P_bit(const void * const hw,uint8_t submodule_index)4580 static inline void hri_tal_clear_CTIMASK_CM0P_bit(const void *const hw, uint8_t submodule_index)
4581 {
4582 TAL_CRITICAL_SECTION_ENTER();
4583 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_CM0P;
4584 TAL_CRITICAL_SECTION_LEAVE();
4585 }
4586
hri_tal_toggle_CTIMASK_CM0P_bit(const void * const hw,uint8_t submodule_index)4587 static inline void hri_tal_toggle_CTIMASK_CM0P_bit(const void *const hw, uint8_t submodule_index)
4588 {
4589 TAL_CRITICAL_SECTION_ENTER();
4590 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_CM0P;
4591 TAL_CRITICAL_SECTION_LEAVE();
4592 }
4593
hri_tal_set_CTIMASK_PPP_bit(const void * const hw,uint8_t submodule_index)4594 static inline void hri_tal_set_CTIMASK_PPP_bit(const void *const hw, uint8_t submodule_index)
4595 {
4596 TAL_CRITICAL_SECTION_ENTER();
4597 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_PPP;
4598 TAL_CRITICAL_SECTION_LEAVE();
4599 }
4600
hri_tal_get_CTIMASK_PPP_bit(const void * const hw,uint8_t submodule_index)4601 static inline bool hri_tal_get_CTIMASK_PPP_bit(const void *const hw, uint8_t submodule_index)
4602 {
4603 uint8_t tmp;
4604 tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg;
4605 tmp = (tmp & TAL_CTIMASK_PPP) >> TAL_CTIMASK_PPP_Pos;
4606 return (bool)tmp;
4607 }
4608
hri_tal_write_CTIMASK_PPP_bit(const void * const hw,uint8_t submodule_index,bool value)4609 static inline void hri_tal_write_CTIMASK_PPP_bit(const void *const hw, uint8_t submodule_index, bool value)
4610 {
4611 uint8_t tmp;
4612 TAL_CRITICAL_SECTION_ENTER();
4613 tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg;
4614 tmp &= ~TAL_CTIMASK_PPP;
4615 tmp |= value << TAL_CTIMASK_PPP_Pos;
4616 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp;
4617 TAL_CRITICAL_SECTION_LEAVE();
4618 }
4619
hri_tal_clear_CTIMASK_PPP_bit(const void * const hw,uint8_t submodule_index)4620 static inline void hri_tal_clear_CTIMASK_PPP_bit(const void *const hw, uint8_t submodule_index)
4621 {
4622 TAL_CRITICAL_SECTION_ENTER();
4623 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_PPP;
4624 TAL_CRITICAL_SECTION_LEAVE();
4625 }
4626
hri_tal_toggle_CTIMASK_PPP_bit(const void * const hw,uint8_t submodule_index)4627 static inline void hri_tal_toggle_CTIMASK_PPP_bit(const void *const hw, uint8_t submodule_index)
4628 {
4629 TAL_CRITICAL_SECTION_ENTER();
4630 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_PPP;
4631 TAL_CRITICAL_SECTION_LEAVE();
4632 }
4633
hri_tal_set_CTIMASK_EVBRK_bit(const void * const hw,uint8_t submodule_index)4634 static inline void hri_tal_set_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index)
4635 {
4636 TAL_CRITICAL_SECTION_ENTER();
4637 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_EVBRK;
4638 TAL_CRITICAL_SECTION_LEAVE();
4639 }
4640
hri_tal_get_CTIMASK_EVBRK_bit(const void * const hw,uint8_t submodule_index)4641 static inline bool hri_tal_get_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index)
4642 {
4643 uint8_t tmp;
4644 tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg;
4645 tmp = (tmp & TAL_CTIMASK_EVBRK) >> TAL_CTIMASK_EVBRK_Pos;
4646 return (bool)tmp;
4647 }
4648
hri_tal_write_CTIMASK_EVBRK_bit(const void * const hw,uint8_t submodule_index,bool value)4649 static inline void hri_tal_write_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index, bool value)
4650 {
4651 uint8_t tmp;
4652 TAL_CRITICAL_SECTION_ENTER();
4653 tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg;
4654 tmp &= ~TAL_CTIMASK_EVBRK;
4655 tmp |= value << TAL_CTIMASK_EVBRK_Pos;
4656 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp;
4657 TAL_CRITICAL_SECTION_LEAVE();
4658 }
4659
hri_tal_clear_CTIMASK_EVBRK_bit(const void * const hw,uint8_t submodule_index)4660 static inline void hri_tal_clear_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index)
4661 {
4662 TAL_CRITICAL_SECTION_ENTER();
4663 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_EVBRK;
4664 TAL_CRITICAL_SECTION_LEAVE();
4665 }
4666
hri_tal_toggle_CTIMASK_EVBRK_bit(const void * const hw,uint8_t submodule_index)4667 static inline void hri_tal_toggle_CTIMASK_EVBRK_bit(const void *const hw, uint8_t submodule_index)
4668 {
4669 TAL_CRITICAL_SECTION_ENTER();
4670 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_EVBRK;
4671 TAL_CRITICAL_SECTION_LEAVE();
4672 }
4673
hri_tal_set_CTIMASK_EXTBRK_bit(const void * const hw,uint8_t submodule_index)4674 static inline void hri_tal_set_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index)
4675 {
4676 TAL_CRITICAL_SECTION_ENTER();
4677 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= TAL_CTIMASK_EXTBRK;
4678 TAL_CRITICAL_SECTION_LEAVE();
4679 }
4680
hri_tal_get_CTIMASK_EXTBRK_bit(const void * const hw,uint8_t submodule_index)4681 static inline bool hri_tal_get_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index)
4682 {
4683 uint8_t tmp;
4684 tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg;
4685 tmp = (tmp & TAL_CTIMASK_EXTBRK) >> TAL_CTIMASK_EXTBRK_Pos;
4686 return (bool)tmp;
4687 }
4688
hri_tal_write_CTIMASK_EXTBRK_bit(const void * const hw,uint8_t submodule_index,bool value)4689 static inline void hri_tal_write_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index, bool value)
4690 {
4691 uint8_t tmp;
4692 TAL_CRITICAL_SECTION_ENTER();
4693 tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg;
4694 tmp &= ~TAL_CTIMASK_EXTBRK;
4695 tmp |= value << TAL_CTIMASK_EXTBRK_Pos;
4696 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = tmp;
4697 TAL_CRITICAL_SECTION_LEAVE();
4698 }
4699
hri_tal_clear_CTIMASK_EXTBRK_bit(const void * const hw,uint8_t submodule_index)4700 static inline void hri_tal_clear_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index)
4701 {
4702 TAL_CRITICAL_SECTION_ENTER();
4703 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~TAL_CTIMASK_EXTBRK;
4704 TAL_CRITICAL_SECTION_LEAVE();
4705 }
4706
hri_tal_toggle_CTIMASK_EXTBRK_bit(const void * const hw,uint8_t submodule_index)4707 static inline void hri_tal_toggle_CTIMASK_EXTBRK_bit(const void *const hw, uint8_t submodule_index)
4708 {
4709 TAL_CRITICAL_SECTION_ENTER();
4710 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= TAL_CTIMASK_EXTBRK;
4711 TAL_CRITICAL_SECTION_LEAVE();
4712 }
4713
hri_tal_set_CTIMASK_reg(const void * const hw,uint8_t submodule_index,hri_tal_ctimask_reg_t mask)4714 static inline void hri_tal_set_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t mask)
4715 {
4716 TAL_CRITICAL_SECTION_ENTER();
4717 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg |= mask;
4718 TAL_CRITICAL_SECTION_LEAVE();
4719 }
4720
hri_tal_get_CTIMASK_reg(const void * const hw,uint8_t submodule_index,hri_tal_ctimask_reg_t mask)4721 static inline hri_tal_ctimask_reg_t hri_tal_get_CTIMASK_reg(const void *const hw, uint8_t submodule_index,
4722 hri_tal_ctimask_reg_t mask)
4723 {
4724 uint8_t tmp;
4725 tmp = ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg;
4726 tmp &= mask;
4727 return tmp;
4728 }
4729
hri_tal_write_CTIMASK_reg(const void * const hw,uint8_t submodule_index,hri_tal_ctimask_reg_t data)4730 static inline void hri_tal_write_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t data)
4731 {
4732 TAL_CRITICAL_SECTION_ENTER();
4733 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg = data;
4734 TAL_CRITICAL_SECTION_LEAVE();
4735 }
4736
hri_tal_clear_CTIMASK_reg(const void * const hw,uint8_t submodule_index,hri_tal_ctimask_reg_t mask)4737 static inline void hri_tal_clear_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t mask)
4738 {
4739 TAL_CRITICAL_SECTION_ENTER();
4740 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg &= ~mask;
4741 TAL_CRITICAL_SECTION_LEAVE();
4742 }
4743
hri_tal_toggle_CTIMASK_reg(const void * const hw,uint8_t submodule_index,hri_tal_ctimask_reg_t mask)4744 static inline void hri_tal_toggle_CTIMASK_reg(const void *const hw, uint8_t submodule_index, hri_tal_ctimask_reg_t mask)
4745 {
4746 TAL_CRITICAL_SECTION_ENTER();
4747 ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg ^= mask;
4748 TAL_CRITICAL_SECTION_LEAVE();
4749 }
4750
hri_tal_read_CTIMASK_reg(const void * const hw,uint8_t submodule_index)4751 static inline hri_tal_ctimask_reg_t hri_tal_read_CTIMASK_reg(const void *const hw, uint8_t submodule_index)
4752 {
4753 return ((Tal *)hw)->Ctis[submodule_index].CTIMASK.reg;
4754 }
4755
4756 #ifdef __cplusplus
4757 }
4758 #endif
4759
4760 #endif /* _HRI_TAL_L21_H_INCLUDED */
4761 #endif /* _SAML21_TAL_COMPONENT_ */
4762
