Searched refs:__OM (Results 1 – 7 of 7) sorted by relevance
290 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro480 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…528 …__OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Regi…534 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */536 …__OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU …537 …__OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC …538 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */539 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */540 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */541 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */[all …]
222 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro397 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…737 __OM union739 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */740 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */741 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */750 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */754 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */1238 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
222 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro397 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…719 __OM union721 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */722 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */723 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */732 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */736 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */1220 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
275 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro465 …__OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Regist…798 __OM union800 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */801 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */802 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */811 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */815 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */1407 …__OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Regi…
217 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
227 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
222 #define __OM volatile /*! Defines 'write only' structure member permissions */ macro
