1 /**************************************************************************//**
2 * @file core_cm4.h
3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
4 * @version V4.30
5 * @date 20. October 2015
6 ******************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8
9 All rights reserved.
10 Redistribution and use in source and binary forms, with or without
11 modification, are permitted provided that the following conditions are met:
12 - Redistributions of source code must retain the above copyright
13 notice, this list of conditions and the following disclaimer.
14 - Redistributions in binary form must reproduce the above copyright
15 notice, this list of conditions and the following disclaimer in the
16 documentation and/or other materials provided with the distribution.
17 - Neither the name of ARM nor the names of its contributors may be used
18 to endorse or promote products derived from this software without
19 specific prior written permission.
20 *
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 ---------------------------------------------------------------------------*/
33
34
35 #if defined ( __ICCARM__ )
36 #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38 #pragma clang system_header /* treat file as system include file */
39 #endif
40
41 #ifndef __CORE_CM4_H_GENERIC
42 #define __CORE_CM4_H_GENERIC
43
44 #include <stdint.h>
45
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49
50 /**
51 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
52 CMSIS violates the following MISRA-C:2004 rules:
53
54 \li Required Rule 8.5, object/function definition in header file.<br>
55 Function definitions in header files are used to allow 'inlining'.
56
57 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
58 Unions are used for effective representation of core registers.
59
60 \li Advisory Rule 19.7, Function-like macro defined.<br>
61 Function-like macros are used to allow more efficient code.
62 */
63
64
65 /*******************************************************************************
66 * CMSIS definitions
67 ******************************************************************************/
68 /**
69 \ingroup Cortex_M4
70 @{
71 */
72
73 /* CMSIS CM4 definitions */
74 #define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
75 #define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
76 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
77 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
78
79 #define __CORTEX_M (0x04U) /*!< Cortex-M Core */
80
81
82 #if defined ( __CC_ARM )
83 #define __ASM __asm /*!< asm keyword for ARM Compiler */
84 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
85 #define __STATIC_INLINE static __inline
86
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88 #define __ASM __asm /*!< asm keyword for ARM Compiler */
89 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
90 #define __STATIC_INLINE static __inline
91
92 #elif defined ( __GNUC__ )
93 #define __ASM __asm /*!< asm keyword for GNU Compiler */
94 #define __INLINE inline /*!< inline keyword for GNU Compiler */
95 #define __STATIC_INLINE static inline
96
97 #elif defined ( __ICCARM__ )
98 #define __ASM __asm /*!< asm keyword for IAR Compiler */
99 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
100 #define __STATIC_INLINE static inline
101
102 #elif defined ( __TMS470__ )
103 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
104 #define __STATIC_INLINE static inline
105
106 #elif defined ( __TASKING__ )
107 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
108 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
109 #define __STATIC_INLINE static inline
110
111 #elif defined ( __CSMC__ )
112 #define __packed
113 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
114 #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
115 #define __STATIC_INLINE static inline
116
117 #else
118 #error Unknown compiler
119 #endif
120
121 /** __FPU_USED indicates whether an FPU is used or not.
122 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
123 */
124 #if defined ( __CC_ARM )
125 #if defined __TARGET_FPU_VFP
126 #if (__FPU_PRESENT == 1U)
127 #define __FPU_USED 1U
128 #else
129 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
130 #define __FPU_USED 0U
131 #endif
132 #else
133 #define __FPU_USED 0U
134 #endif
135
136 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
137 #if defined __ARM_PCS_VFP
138 #if (__FPU_PRESENT == 1)
139 #define __FPU_USED 1U
140 #else
141 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
142 #define __FPU_USED 0U
143 #endif
144 #else
145 #define __FPU_USED 0U
146 #endif
147
148 #elif defined ( __GNUC__ )
149 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
150 #if (__FPU_PRESENT == 1U)
151 #define __FPU_USED 1U
152 #else
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #define __FPU_USED 0U
155 #endif
156 #else
157 #define __FPU_USED 0U
158 #endif
159
160 #elif defined ( __ICCARM__ )
161 #if defined __ARMVFP__
162 #if (__FPU_PRESENT == 1U)
163 #define __FPU_USED 1U
164 #else
165 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
166 #define __FPU_USED 0U
167 #endif
168 #else
169 #define __FPU_USED 0U
170 #endif
171
172 #elif defined ( __TMS470__ )
173 #if defined __TI_VFP_SUPPORT__
174 #if (__FPU_PRESENT == 1U)
175 #define __FPU_USED 1U
176 #else
177 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
178 #define __FPU_USED 0U
179 #endif
180 #else
181 #define __FPU_USED 0U
182 #endif
183
184 #elif defined ( __TASKING__ )
185 #if defined __FPU_VFP__
186 #if (__FPU_PRESENT == 1U)
187 #define __FPU_USED 1U
188 #else
189 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
190 #define __FPU_USED 0U
191 #endif
192 #else
193 #define __FPU_USED 0U
194 #endif
195
196 #elif defined ( __CSMC__ )
197 #if ( __CSMC__ & 0x400U)
198 #if (__FPU_PRESENT == 1U)
199 #define __FPU_USED 1U
200 #else
201 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
202 #define __FPU_USED 0U
203 #endif
204 #else
205 #define __FPU_USED 0U
206 #endif
207
208 #endif
209
210 #include "core_cmInstr.h" /* Core Instruction Access */
211 #include "core_cmFunc.h" /* Core Function Access */
212 #include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
213
214 #ifdef __cplusplus
215 }
216 #endif
217
218 #endif /* __CORE_CM4_H_GENERIC */
219
220 #ifndef __CMSIS_GENERIC
221
222 #ifndef __CORE_CM4_H_DEPENDANT
223 #define __CORE_CM4_H_DEPENDANT
224
225 #ifdef __cplusplus
226 extern "C" {
227 #endif
228
229 /* check device defines and use defaults */
230 #if defined __CHECK_DEVICE_DEFINES
231 #ifndef __CM4_REV
232 #define __CM4_REV 0x0000U
233 #warning "__CM4_REV not defined in device header file; using default!"
234 #endif
235
236 #ifndef __FPU_PRESENT
237 #define __FPU_PRESENT 0U
238 #warning "__FPU_PRESENT not defined in device header file; using default!"
239 #endif
240
241 #ifndef __MPU_PRESENT
242 #define __MPU_PRESENT 0U
243 #warning "__MPU_PRESENT not defined in device header file; using default!"
244 #endif
245
246 #ifndef __NVIC_PRIO_BITS
247 #define __NVIC_PRIO_BITS 4U
248 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
249 #endif
250
251 #ifndef __Vendor_SysTickConfig
252 #define __Vendor_SysTickConfig 0U
253 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
254 #endif
255 #endif
256
257 /* IO definitions (access restrictions to peripheral registers) */
258 /**
259 \defgroup CMSIS_glob_defs CMSIS Global Defines
260
261 <strong>IO Type Qualifiers</strong> are used
262 \li to specify the access to peripheral variables.
263 \li for automatic generation of peripheral register debug information.
264 */
265 #ifdef __cplusplus
266 #define __I volatile /*!< Defines 'read only' permissions */
267 #else
268 #define __I volatile const /*!< Defines 'read only' permissions */
269 #endif
270 #define __O volatile /*!< Defines 'write only' permissions */
271 #define __IO volatile /*!< Defines 'read / write' permissions */
272
273 /* following defines should be used for structure members */
274 #define __IM volatile const /*! Defines 'read only' structure member permissions */
275 #define __OM volatile /*! Defines 'write only' structure member permissions */
276 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
277
278 /*@} end of group Cortex_M4 */
279
280
281
282 /*******************************************************************************
283 * Register Abstraction
284 Core Register contain:
285 - Core Register
286 - Core NVIC Register
287 - Core SCB Register
288 - Core SysTick Register
289 - Core Debug Register
290 - Core MPU Register
291 - Core FPU Register
292 ******************************************************************************/
293 /**
294 \defgroup CMSIS_core_register Defines and Type Definitions
295 \brief Type definitions and defines for Cortex-M processor based devices.
296 */
297
298 /**
299 \ingroup CMSIS_core_register
300 \defgroup CMSIS_CORE Status and Control Registers
301 \brief Core Register type definitions.
302 @{
303 */
304
305 /**
306 \brief Union type to access the Application Program Status Register (APSR).
307 */
308 typedef union
309 {
310 struct
311 {
312 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
313 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
314 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
315 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
316 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
317 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
318 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
319 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
320 } b; /*!< Structure used for bit access */
321 uint32_t w; /*!< Type used for word access */
322 } APSR_Type;
323
324 /* APSR Register Definitions */
325 #define APSR_N_Pos 31U /*!< APSR: N Position */
326 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
327
328 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
329 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
330
331 #define APSR_C_Pos 29U /*!< APSR: C Position */
332 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
333
334 #define APSR_V_Pos 28U /*!< APSR: V Position */
335 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
336
337 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
338 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
339
340 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
341 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
342
343
344 /**
345 \brief Union type to access the Interrupt Program Status Register (IPSR).
346 */
347 typedef union
348 {
349 struct
350 {
351 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
352 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
353 } b; /*!< Structure used for bit access */
354 uint32_t w; /*!< Type used for word access */
355 } IPSR_Type;
356
357 /* IPSR Register Definitions */
358 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
359 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
360
361
362 /**
363 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
364 */
365 typedef union
366 {
367 struct
368 {
369 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
370 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
371 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
372 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
373 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
374 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
375 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
376 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
377 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
378 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
379 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
380 } b; /*!< Structure used for bit access */
381 uint32_t w; /*!< Type used for word access */
382 } xPSR_Type;
383
384 /* xPSR Register Definitions */
385 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
386 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
387
388 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
389 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
390
391 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
392 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
393
394 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
395 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
396
397 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
398 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
399
400 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
401 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
402
403 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
404 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
405
406 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
407 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
408
409 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
410 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
411
412
413 /**
414 \brief Union type to access the Control Registers (CONTROL).
415 */
416 typedef union
417 {
418 struct
419 {
420 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
421 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
422 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
423 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
424 } b; /*!< Structure used for bit access */
425 uint32_t w; /*!< Type used for word access */
426 } CONTROL_Type;
427
428 /* CONTROL Register Definitions */
429 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
430 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
431
432 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
433 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
434
435 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
436 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
437
438 /*@} end of group CMSIS_CORE */
439
440
441 /**
442 \ingroup CMSIS_core_register
443 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
444 \brief Type definitions for the NVIC Registers
445 @{
446 */
447
448 /**
449 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
450 */
451 typedef struct
452 {
453 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
454 uint32_t RESERVED0[24U];
455 __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
456 uint32_t RSERVED1[24U];
457 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
458 uint32_t RESERVED2[24U];
459 __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
460 uint32_t RESERVED3[24U];
461 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
462 uint32_t RESERVED4[56U];
463 __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
464 uint32_t RESERVED5[644U];
465 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
466 } NVIC_Type;
467
468 /* Software Triggered Interrupt Register Definitions */
469 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
470 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
471
472 /*@} end of group CMSIS_NVIC */
473
474
475 /**
476 \ingroup CMSIS_core_register
477 \defgroup CMSIS_SCB System Control Block (SCB)
478 \brief Type definitions for the System Control Block Registers
479 @{
480 */
481
482 /**
483 \brief Structure type to access the System Control Block (SCB).
484 */
485 typedef struct
486 {
487 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
488 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
489 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
490 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
491 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
492 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
493 __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
494 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
495 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
496 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
497 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
498 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
499 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
500 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
501 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
502 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
503 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
504 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
505 __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
506 uint32_t RESERVED0[5U];
507 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
508 } SCB_Type;
509
510 /* SCB CPUID Register Definitions */
511 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
512 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
513
514 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
515 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
516
517 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
518 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
519
520 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
521 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
522
523 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
524 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
525
526 /* SCB Interrupt Control State Register Definitions */
527 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
528 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
529
530 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
531 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
532
533 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
534 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
535
536 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
537 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
538
539 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
540 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
541
542 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
543 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
544
545 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
546 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
547
548 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
549 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
550
551 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
552 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
553
554 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
555 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
556
557 /* SCB Vector Table Offset Register Definitions */
558 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
559 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
560
561 /* SCB Application Interrupt and Reset Control Register Definitions */
562 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
563 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
564
565 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
566 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
567
568 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
569 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
570
571 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
572 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
573
574 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
575 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
576
577 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
578 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
579
580 #define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
581 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
582
583 /* SCB System Control Register Definitions */
584 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
585 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
586
587 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
588 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
589
590 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
591 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
592
593 /* SCB Configuration Control Register Definitions */
594 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
595 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
596
597 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
598 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
599
600 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
601 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
602
603 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
604 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
605
606 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
607 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
608
609 #define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
610 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
611
612 /* SCB System Handler Control and State Register Definitions */
613 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
614 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
615
616 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
617 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
618
619 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
620 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
621
622 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
623 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
624
625 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
626 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
627
628 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
629 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
630
631 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
632 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
633
634 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
635 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
636
637 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
638 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
639
640 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
641 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
642
643 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
644 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
645
646 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
647 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
648
649 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
650 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
651
652 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
653 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
654
655 /* SCB Configurable Fault Status Register Definitions */
656 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
657 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
658
659 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
660 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
661
662 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
663 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
664
665 /* SCB Hard Fault Status Register Definitions */
666 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
667 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
668
669 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
670 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
671
672 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
673 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
674
675 /* SCB Debug Fault Status Register Definitions */
676 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
677 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
678
679 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
680 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
681
682 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
683 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
684
685 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
686 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
687
688 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
689 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
690
691 /*@} end of group CMSIS_SCB */
692
693
694 /**
695 \ingroup CMSIS_core_register
696 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
697 \brief Type definitions for the System Control and ID Register not in the SCB
698 @{
699 */
700
701 /**
702 \brief Structure type to access the System Control and ID Register not in the SCB.
703 */
704 typedef struct
705 {
706 uint32_t RESERVED0[1U];
707 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
708 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
709 } SCnSCB_Type;
710
711 /* Interrupt Controller Type Register Definitions */
712 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
713 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
714
715 /* Auxiliary Control Register Definitions */
716 #define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
717 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
718
719 #define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
720 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
721
722 #define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
723 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
724
725 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
726 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
727
728 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
729 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
730
731 /*@} end of group CMSIS_SCnotSCB */
732
733
734 /**
735 \ingroup CMSIS_core_register
736 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
737 \brief Type definitions for the System Timer Registers.
738 @{
739 */
740
741 /**
742 \brief Structure type to access the System Timer (SysTick).
743 */
744 typedef struct
745 {
746 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
747 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
748 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
749 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
750 } SysTick_Type;
751
752 /* SysTick Control / Status Register Definitions */
753 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
754 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
755
756 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
757 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
758
759 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
760 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
761
762 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
763 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
764
765 /* SysTick Reload Register Definitions */
766 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
767 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
768
769 /* SysTick Current Register Definitions */
770 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
771 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
772
773 /* SysTick Calibration Register Definitions */
774 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
775 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
776
777 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
778 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
779
780 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
781 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
782
783 /*@} end of group CMSIS_SysTick */
784
785
786 /**
787 \ingroup CMSIS_core_register
788 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
789 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
790 @{
791 */
792
793 /**
794 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
795 */
796 typedef struct
797 {
798 __OM union
799 {
800 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
801 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
802 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
803 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
804 uint32_t RESERVED0[864U];
805 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
806 uint32_t RESERVED1[15U];
807 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
808 uint32_t RESERVED2[15U];
809 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
810 uint32_t RESERVED3[29U];
811 __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
812 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
813 __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
814 uint32_t RESERVED4[43U];
815 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
816 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
817 uint32_t RESERVED5[6U];
818 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
819 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
820 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
821 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
822 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
823 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
824 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
825 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
826 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
827 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
828 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
829 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
830 } ITM_Type;
831
832 /* ITM Trace Privilege Register Definitions */
833 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
834 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
835
836 /* ITM Trace Control Register Definitions */
837 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
838 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
839
840 #define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
841 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
842
843 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
844 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
845
846 #define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
847 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
848
849 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
850 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
851
852 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
853 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
854
855 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
856 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
857
858 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
859 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
860
861 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
862 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
863
864 /* ITM Integration Write Register Definitions */
865 #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
866 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
867
868 /* ITM Integration Read Register Definitions */
869 #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
870 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
871
872 /* ITM Integration Mode Control Register Definitions */
873 #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
874 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
875
876 /* ITM Lock Status Register Definitions */
877 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
878 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
879
880 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
881 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
882
883 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
884 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
885
886 /*@}*/ /* end of group CMSIS_ITM */
887
888
889 /**
890 \ingroup CMSIS_core_register
891 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
892 \brief Type definitions for the Data Watchpoint and Trace (DWT)
893 @{
894 */
895
896 /**
897 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
898 */
899 typedef struct
900 {
901 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
902 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
903 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
904 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
905 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
906 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
907 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
908 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
909 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
910 __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
911 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
912 uint32_t RESERVED0[1U];
913 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
914 __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
915 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
916 uint32_t RESERVED1[1U];
917 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
918 __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
919 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
920 uint32_t RESERVED2[1U];
921 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
922 __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
923 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
924 } DWT_Type;
925
926 /* DWT Control Register Definitions */
927 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
928 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
929
930 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
931 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
932
933 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
934 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
935
936 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
937 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
938
939 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
940 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
941
942 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
943 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
944
945 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
946 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
947
948 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
949 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
950
951 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
952 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
953
954 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
955 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
956
957 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
958 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
959
960 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
961 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
962
963 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
964 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
965
966 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
967 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
968
969 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
970 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
971
972 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
973 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
974
975 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
976 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
977
978 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
979 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
980
981 /* DWT CPI Count Register Definitions */
982 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
983 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
984
985 /* DWT Exception Overhead Count Register Definitions */
986 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
987 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
988
989 /* DWT Sleep Count Register Definitions */
990 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
991 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
992
993 /* DWT LSU Count Register Definitions */
994 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
995 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
996
997 /* DWT Folded-instruction Count Register Definitions */
998 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
999 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1000
1001 /* DWT Comparator Mask Register Definitions */
1002 #define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
1003 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
1004
1005 /* DWT Comparator Function Register Definitions */
1006 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1007 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1008
1009 #define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
1010 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
1011
1012 #define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
1013 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
1014
1015 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1016 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1017
1018 #define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
1019 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
1020
1021 #define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
1022 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
1023
1024 #define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
1025 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
1026
1027 #define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
1028 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
1029
1030 #define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
1031 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
1032
1033 /*@}*/ /* end of group CMSIS_DWT */
1034
1035
1036 /**
1037 \ingroup CMSIS_core_register
1038 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1039 \brief Type definitions for the Trace Port Interface (TPI)
1040 @{
1041 */
1042
1043 /**
1044 \brief Structure type to access the Trace Port Interface Register (TPI).
1045 */
1046 typedef struct
1047 {
1048 __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1049 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1050 uint32_t RESERVED0[2U];
1051 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1052 uint32_t RESERVED1[55U];
1053 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1054 uint32_t RESERVED2[131U];
1055 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1056 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1057 __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
1058 uint32_t RESERVED3[759U];
1059 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
1060 __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
1061 __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
1062 uint32_t RESERVED4[1U];
1063 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
1064 __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
1065 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1066 uint32_t RESERVED5[39U];
1067 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1068 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1069 uint32_t RESERVED7[8U];
1070 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
1071 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
1072 } TPI_Type;
1073
1074 /* TPI Asynchronous Clock Prescaler Register Definitions */
1075 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1076 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1077
1078 /* TPI Selected Pin Protocol Register Definitions */
1079 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1080 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1081
1082 /* TPI Formatter and Flush Status Register Definitions */
1083 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1084 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1085
1086 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1087 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1088
1089 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1090 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1091
1092 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1093 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1094
1095 /* TPI Formatter and Flush Control Register Definitions */
1096 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1097 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1098
1099 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1100 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1101
1102 /* TPI TRIGGER Register Definitions */
1103 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1104 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1105
1106 /* TPI Integration ETM Data Register Definitions (FIFO0) */
1107 #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
1108 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
1109
1110 #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
1111 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
1112
1113 #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
1114 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
1115
1116 #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
1117 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
1118
1119 #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
1120 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
1121
1122 #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
1123 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
1124
1125 #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
1126 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
1127
1128 /* TPI ITATBCTR2 Register Definitions */
1129 #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
1130 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
1131
1132 /* TPI Integration ITM Data Register Definitions (FIFO1) */
1133 #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
1134 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
1135
1136 #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
1137 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
1138
1139 #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
1140 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
1141
1142 #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
1143 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
1144
1145 #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
1146 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
1147
1148 #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
1149 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
1150
1151 #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
1152 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
1153
1154 /* TPI ITATBCTR0 Register Definitions */
1155 #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
1156 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
1157
1158 /* TPI Integration Mode Control Register Definitions */
1159 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1160 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1161
1162 /* TPI DEVID Register Definitions */
1163 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1164 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1165
1166 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1167 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1168
1169 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1170 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1171
1172 #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
1173 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
1174
1175 #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
1176 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
1177
1178 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1179 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1180
1181 /* TPI DEVTYPE Register Definitions */
1182 #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
1183 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1184
1185 #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
1186 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1187
1188 /*@}*/ /* end of group CMSIS_TPI */
1189
1190
1191 #if (__MPU_PRESENT == 1U)
1192 /**
1193 \ingroup CMSIS_core_register
1194 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1195 \brief Type definitions for the Memory Protection Unit (MPU)
1196 @{
1197 */
1198
1199 /**
1200 \brief Structure type to access the Memory Protection Unit (MPU).
1201 */
1202 typedef struct
1203 {
1204 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1205 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1206 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1207 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1208 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1209 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1210 __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1211 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1212 __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1213 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1214 __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1215 } MPU_Type;
1216
1217 /* MPU Type Register Definitions */
1218 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1219 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1220
1221 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1222 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1223
1224 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1225 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1226
1227 /* MPU Control Register Definitions */
1228 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1229 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1230
1231 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1232 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1233
1234 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1235 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1236
1237 /* MPU Region Number Register Definitions */
1238 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1239 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1240
1241 /* MPU Region Base Address Register Definitions */
1242 #define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
1243 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1244
1245 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
1246 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1247
1248 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
1249 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
1250
1251 /* MPU Region Attribute and Size Register Definitions */
1252 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
1253 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1254
1255 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
1256 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1257
1258 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
1259 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1260
1261 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
1262 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1263
1264 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
1265 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1266
1267 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
1268 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1269
1270 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
1271 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1272
1273 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
1274 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1275
1276 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
1277 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1278
1279 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
1280 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
1281
1282 /*@} end of group CMSIS_MPU */
1283 #endif
1284
1285
1286 #if (__FPU_PRESENT == 1U)
1287 /**
1288 \ingroup CMSIS_core_register
1289 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1290 \brief Type definitions for the Floating Point Unit (FPU)
1291 @{
1292 */
1293
1294 /**
1295 \brief Structure type to access the Floating Point Unit (FPU).
1296 */
1297 typedef struct
1298 {
1299 uint32_t RESERVED0[1U];
1300 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1301 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1302 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1303 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
1304 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
1305 } FPU_Type;
1306
1307 /* Floating-Point Context Control Register Definitions */
1308 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1309 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1310
1311 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1312 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1313
1314 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1315 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1316
1317 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1318 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1319
1320 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1321 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1322
1323 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1324 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1325
1326 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1327 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1328
1329 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1330 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1331
1332 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1333 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1334
1335 /* Floating-Point Context Address Register Definitions */
1336 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1337 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1338
1339 /* Floating-Point Default Status Control Register Definitions */
1340 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1341 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1342
1343 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1344 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1345
1346 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1347 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1348
1349 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1350 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1351
1352 /* Media and FP Feature Register 0 Definitions */
1353 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1354 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1355
1356 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1357 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1358
1359 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1360 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1361
1362 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1363 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1364
1365 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1366 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1367
1368 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1369 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1370
1371 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1372 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1373
1374 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1375 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1376
1377 /* Media and FP Feature Register 1 Definitions */
1378 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1379 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1380
1381 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1382 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1383
1384 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1385 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1386
1387 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1388 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1389
1390 /*@} end of group CMSIS_FPU */
1391 #endif
1392
1393
1394 /**
1395 \ingroup CMSIS_core_register
1396 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1397 \brief Type definitions for the Core Debug Registers
1398 @{
1399 */
1400
1401 /**
1402 \brief Structure type to access the Core Debug Register (CoreDebug).
1403 */
1404 typedef struct
1405 {
1406 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1407 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1408 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1409 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1410 } CoreDebug_Type;
1411
1412 /* Debug Halting Control and Status Register Definitions */
1413 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
1414 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1415
1416 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
1417 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1418
1419 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1420 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1421
1422 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
1423 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1424
1425 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
1426 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1427
1428 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
1429 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1430
1431 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
1432 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1433
1434 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1435 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1436
1437 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
1438 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1439
1440 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
1441 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1442
1443 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
1444 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1445
1446 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1447 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1448
1449 /* Debug Core Register Selector Register Definitions */
1450 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
1451 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1452
1453 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
1454 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
1455
1456 /* Debug Exception and Monitor Control Register Definitions */
1457 #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
1458 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1459
1460 #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
1461 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1462
1463 #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
1464 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1465
1466 #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
1467 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1468
1469 #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
1470 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1471
1472 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
1473 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1474
1475 #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
1476 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1477
1478 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
1479 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1480
1481 #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
1482 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1483
1484 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
1485 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1486
1487 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1488 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1489
1490 #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
1491 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1492
1493 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
1494 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1495
1496 /*@} end of group CMSIS_CoreDebug */
1497
1498
1499 /**
1500 \ingroup CMSIS_core_register
1501 \defgroup CMSIS_core_bitfield Core register bit field macros
1502 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1503 @{
1504 */
1505
1506 /**
1507 \brief Mask and shift a bit field value for use in a register bit range.
1508 \param[in] field Name of the register bit field.
1509 \param[in] value Value of the bit field.
1510 \return Masked and shifted value.
1511 */
1512 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
1513
1514 /**
1515 \brief Mask and shift a register value to extract a bit filed value.
1516 \param[in] field Name of the register bit field.
1517 \param[in] value Value of register.
1518 \return Masked and shifted bit field value.
1519 */
1520 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
1521
1522 /*@} end of group CMSIS_core_bitfield */
1523
1524
1525 /**
1526 \ingroup CMSIS_core_register
1527 \defgroup CMSIS_core_base Core Definitions
1528 \brief Definitions for base addresses, unions, and structures.
1529 @{
1530 */
1531
1532 /* Memory mapping of Cortex-M4 Hardware */
1533 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1534 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1535 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1536 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1537 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1538 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1539 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1540 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1541
1542 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1543 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1544 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1545 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1546 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1547 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1548 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1549 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1550
1551 #if (__MPU_PRESENT == 1U)
1552 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1553 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1554 #endif
1555
1556 #if (__FPU_PRESENT == 1U)
1557 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
1558 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
1559 #endif
1560
1561 /*@} */
1562
1563
1564
1565 /*******************************************************************************
1566 * Hardware Abstraction Layer
1567 Core Function Interface contains:
1568 - Core NVIC Functions
1569 - Core SysTick Functions
1570 - Core Debug Functions
1571 - Core Register Access Functions
1572 ******************************************************************************/
1573 /**
1574 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1575 */
1576
1577
1578
1579 /* ########################## NVIC functions #################################### */
1580 /**
1581 \ingroup CMSIS_Core_FunctionInterface
1582 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1583 \brief Functions that manage interrupts and exceptions via the NVIC.
1584 @{
1585 */
1586
1587 /**
1588 \brief Set Priority Grouping
1589 \details Sets the priority grouping field using the required unlock sequence.
1590 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1591 Only values from 0..7 are used.
1592 In case of a conflict between priority grouping and available
1593 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1594 \param [in] PriorityGroup Priority grouping field.
1595 */
NVIC_SetPriorityGrouping(uint32_t PriorityGroup)1596 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1597 {
1598 uint32_t reg_value;
1599 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1600
1601 reg_value = SCB->AIRCR; /* read old register configuration */
1602 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
1603 reg_value = (reg_value |
1604 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1605 (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
1606 SCB->AIRCR = reg_value;
1607 }
1608
1609
1610 /**
1611 \brief Get Priority Grouping
1612 \details Reads the priority grouping field from the NVIC Interrupt Controller.
1613 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1614 */
NVIC_GetPriorityGrouping(void)1615 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1616 {
1617 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
1618 }
1619
1620
1621 /**
1622 \brief Enable External Interrupt
1623 \details Enables a device-specific interrupt in the NVIC interrupt controller.
1624 \param [in] IRQn External interrupt number. Value cannot be negative.
1625 */
NVIC_EnableIRQ(IRQn_Type IRQn)1626 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1627 {
1628 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1629 }
1630
1631
1632 /**
1633 \brief Disable External Interrupt
1634 \details Disables a device-specific interrupt in the NVIC interrupt controller.
1635 \param [in] IRQn External interrupt number. Value cannot be negative.
1636 */
NVIC_DisableIRQ(IRQn_Type IRQn)1637 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1638 {
1639 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1640 }
1641
1642
1643 /**
1644 \brief Get Pending Interrupt
1645 \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
1646 \param [in] IRQn Interrupt number.
1647 \return 0 Interrupt status is not pending.
1648 \return 1 Interrupt status is pending.
1649 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)1650 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1651 {
1652 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1653 }
1654
1655
1656 /**
1657 \brief Set Pending Interrupt
1658 \details Sets the pending bit of an external interrupt.
1659 \param [in] IRQn Interrupt number. Value cannot be negative.
1660 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)1661 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1662 {
1663 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1664 }
1665
1666
1667 /**
1668 \brief Clear Pending Interrupt
1669 \details Clears the pending bit of an external interrupt.
1670 \param [in] IRQn External interrupt number. Value cannot be negative.
1671 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)1672 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1673 {
1674 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
1675 }
1676
1677
1678 /**
1679 \brief Get Active Interrupt
1680 \details Reads the active register in NVIC and returns the active bit.
1681 \param [in] IRQn Interrupt number.
1682 \return 0 Interrupt status is not active.
1683 \return 1 Interrupt status is active.
1684 */
NVIC_GetActive(IRQn_Type IRQn)1685 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1686 {
1687 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1688 }
1689
1690
1691 /**
1692 \brief Set Interrupt Priority
1693 \details Sets the priority of an interrupt.
1694 \note The priority cannot be set for every core interrupt.
1695 \param [in] IRQn Interrupt number.
1696 \param [in] priority Priority to set.
1697 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1698 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1699 {
1700 if ((int32_t)(IRQn) < 0)
1701 {
1702 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1703 }
1704 else
1705 {
1706 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
1707 }
1708 }
1709
1710
1711 /**
1712 \brief Get Interrupt Priority
1713 \details Reads the priority of an interrupt.
1714 The interrupt number can be positive to specify an external (device specific) interrupt,
1715 or negative to specify an internal (core) interrupt.
1716 \param [in] IRQn Interrupt number.
1717 \return Interrupt Priority.
1718 Value is aligned automatically to the implemented priority bits of the microcontroller.
1719 */
NVIC_GetPriority(IRQn_Type IRQn)1720 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1721 {
1722
1723 if ((int32_t)(IRQn) < 0)
1724 {
1725 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
1726 }
1727 else
1728 {
1729 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
1730 }
1731 }
1732
1733
1734 /**
1735 \brief Encode Priority
1736 \details Encodes the priority for an interrupt with the given priority group,
1737 preemptive priority value, and subpriority value.
1738 In case of a conflict between priority grouping and available
1739 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1740 \param [in] PriorityGroup Used priority group.
1741 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1742 \param [in] SubPriority Subpriority value (starting from 0).
1743 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1744 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)1745 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1746 {
1747 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1748 uint32_t PreemptPriorityBits;
1749 uint32_t SubPriorityBits;
1750
1751 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1752 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1753
1754 return (
1755 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1756 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1757 );
1758 }
1759
1760
1761 /**
1762 \brief Decode Priority
1763 \details Decodes an interrupt priority value with a given priority group to
1764 preemptive priority value and subpriority value.
1765 In case of a conflict between priority grouping and available
1766 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1767 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1768 \param [in] PriorityGroup Used priority group.
1769 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1770 \param [out] pSubPriority Subpriority value (starting from 0).
1771 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)1772 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1773 {
1774 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1775 uint32_t PreemptPriorityBits;
1776 uint32_t SubPriorityBits;
1777
1778 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1779 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1780
1781 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1782 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1783 }
1784
1785
1786 /**
1787 \brief System Reset
1788 \details Initiates a system reset request to reset the MCU.
1789 */
NVIC_SystemReset(void)1790 __STATIC_INLINE void NVIC_SystemReset(void)
1791 {
1792 __DSB(); /* Ensure all outstanding memory accesses included
1793 buffered write are completed before reset */
1794 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1795 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1796 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
1797 __DSB(); /* Ensure completion of memory access */
1798
1799 for(;;) /* wait until reset */
1800 {
1801 __NOP();
1802 }
1803 }
1804
1805 /*@} end of CMSIS_Core_NVICFunctions */
1806
1807
1808
1809 /* ################################## SysTick function ############################################ */
1810 /**
1811 \ingroup CMSIS_Core_FunctionInterface
1812 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1813 \brief Functions that configure the System.
1814 @{
1815 */
1816
1817 #if (__Vendor_SysTickConfig == 0U)
1818
1819 /**
1820 \brief System Tick Configuration
1821 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
1822 Counter is in free running mode to generate periodic interrupts.
1823 \param [in] ticks Number of ticks between two interrupts.
1824 \return 0 Function succeeded.
1825 \return 1 Function failed.
1826 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1827 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1828 must contain a vendor-specific implementation of this function.
1829 */
SysTick_Config(uint32_t ticks)1830 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1831 {
1832 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
1833 {
1834 return (1UL); /* Reload value impossible */
1835 }
1836
1837 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
1838 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
1839 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
1840 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1841 SysTick_CTRL_TICKINT_Msk |
1842 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1843 return (0UL); /* Function successful */
1844 }
1845
1846 #endif
1847
1848 /*@} end of CMSIS_Core_SysTickFunctions */
1849
1850
1851
1852 /* ##################################### Debug In/Output function ########################################### */
1853 /**
1854 \ingroup CMSIS_Core_FunctionInterface
1855 \defgroup CMSIS_core_DebugFunctions ITM Functions
1856 \brief Functions that access the ITM debug interface.
1857 @{
1858 */
1859
1860 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1861 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1862
1863
1864 /**
1865 \brief ITM Send Character
1866 \details Transmits a character via the ITM channel 0, and
1867 \li Just returns when no debugger is connected that has booked the output.
1868 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1869 \param [in] ch Character to transmit.
1870 \returns Character to transmit.
1871 */
ITM_SendChar(uint32_t ch)1872 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1873 {
1874 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
1875 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
1876 {
1877 while (ITM->PORT[0U].u32 == 0UL)
1878 {
1879 __NOP();
1880 }
1881 ITM->PORT[0U].u8 = (uint8_t)ch;
1882 }
1883 return (ch);
1884 }
1885
1886
1887 /**
1888 \brief ITM Receive Character
1889 \details Inputs a character via the external variable \ref ITM_RxBuffer.
1890 \return Received character.
1891 \return -1 No character pending.
1892 */
ITM_ReceiveChar(void)1893 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
1894 {
1895 int32_t ch = -1; /* no character available */
1896
1897 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
1898 {
1899 ch = ITM_RxBuffer;
1900 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1901 }
1902
1903 return (ch);
1904 }
1905
1906
1907 /**
1908 \brief ITM Check Character
1909 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1910 \return 0 No character available.
1911 \return 1 Character available.
1912 */
ITM_CheckChar(void)1913 __STATIC_INLINE int32_t ITM_CheckChar (void)
1914 {
1915
1916 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
1917 {
1918 return (0); /* no character available */
1919 }
1920 else
1921 {
1922 return (1); /* character available */
1923 }
1924 }
1925
1926 /*@} end of CMSIS_core_DebugFunctions */
1927
1928
1929
1930
1931 #ifdef __cplusplus
1932 }
1933 #endif
1934
1935 #endif /* __CORE_CM4_H_DEPENDANT */
1936
1937 #endif /* __CMSIS_GENERIC */
1938
