Searched refs:__IOM (Results 1 – 7 of 7) sorted by relevance
223 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro385 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */387 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */389 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */391 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …393 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */395 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…420 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…421 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */422 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…[all …]
276 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro453 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */455 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */457 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */459 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …461 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */463 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…488 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…489 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */490 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…[all …]
291 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro468 __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */470 …__IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */472 __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */474 …__IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …476 __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */478 …__IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit…503 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…504 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */505 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…[all …]
223 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro370 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */372 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */374 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */376 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …379 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */398 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…399 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */400 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…401 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */[all …]
228 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro378 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */380 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */382 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */384 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …387 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */406 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…408 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */412 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…413 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */[all …]
218 #define __IOM volatile /*! Defines 'read / write' structure member permissions */ macro364 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */366 …__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */368 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */370 …__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register …373 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */392 …__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Regis…394 …__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset C…395 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */396 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */[all …]
