Searched refs:__IM (Results 1 – 7 of 7) sorted by relevance
221 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro419 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */433 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */434 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */435 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */436 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */437 …__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…647 …__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…688 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */751 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */[all …]
221 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro419 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */433 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */434 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */435 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */436 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */437 …__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…644 …__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…670 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */733 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */[all …]
274 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro487 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */501 __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */502 __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */503 __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */504 __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */505 …__IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…707 …__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Registe…749 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */812 __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */[all …]
289 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro502 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */516 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */517 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */518 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */519 __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */520 …__IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Regist…522 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */523 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */524 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */[all …]
226 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro405 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */525 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */574 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
221 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro397 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */536 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */585 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
216 #define __IM volatile const /*! Defines 'read only' structure member permissions */ macro391 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */501 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
