Searched refs:TC4 (Results 1 – 12 of 12) sorted by relevance
| /loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/ |
| D | saml21e15b.h | 425 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
553 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21e16b.h | 425 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
553 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21e17b.h | 425 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
553 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21e18b.h | 425 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
553 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21g16b.h | 425 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
553 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21g17b.h | 425 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
553 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21g18b.h | 425 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
553 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */
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| D | saml21j16b.h | 435 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
565 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
567 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
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| D | saml21j17b.h | 435 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
565 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
567 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
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| D | saml21j18b.h | 435 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
565 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
567 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
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| D | saml21j18bu.h | 435 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ macro
565 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ macro
567 #define TC_INSTS { TC0, TC1, TC2, TC3, TC4 } /**< \brief (TC) Instances List */
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| /loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/component/ |
| D | tal.h | 732 uint32_t TC4:1; /*!< bit: 10 TC4 Interrupt CPU Select */ member
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