Searched refs:Nvmctrl (Results 1 – 13 of 13) sorted by relevance
73 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_set_INTEN_READY_bit()78 return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_READY) >> NVMCTRL_INTENSET_READY_Pos; in hri_nvmctrl_get_INTEN_READY_bit()84 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_write_INTEN_READY_bit()86 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_write_INTEN_READY_bit()92 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_READY; in hri_nvmctrl_clear_INTEN_READY_bit()97 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_set_INTEN_ERROR_bit()102 return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ERROR) >> NVMCTRL_INTENSET_ERROR_Pos; in hri_nvmctrl_get_INTEN_ERROR_bit()108 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_write_INTEN_ERROR_bit()110 ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_write_INTEN_ERROR_bit()116 ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ERROR; in hri_nvmctrl_clear_INTEN_ERROR_bit()[all …]
481 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
491 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */
347 } Nvmctrl; typedef