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Searched refs:GCLK (Results 1 – 19 of 19) sorted by relevance

/loramac-node-3.4.0/src/boards/mcu/saml21/hpl/gclk/
Dhpl_gclk.c57 hri_gclk_write_GENCTRL_reg(GCLK, in _gclk_init_generators()
69 hri_gclk_write_GENCTRL_reg(GCLK, in _gclk_init_generators()
81 hri_gclk_write_GENCTRL_reg(GCLK, in _gclk_init_generators()
93 hri_gclk_write_GENCTRL_reg(GCLK, in _gclk_init_generators()
105 hri_gclk_write_GENCTRL_reg(GCLK, in _gclk_init_generators()
117 hri_gclk_write_GENCTRL_reg(GCLK, in _gclk_init_generators()
129 hri_gclk_write_GENCTRL_reg(GCLK, in _gclk_init_generators()
141 hri_gclk_write_GENCTRL_reg(GCLK, in _gclk_init_generators()
153 hri_gclk_write_GENCTRL_reg(GCLK, in _gclk_init_generators()
Dhpl_gclk_base.h81 hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); in _gclk_enable_channel()
/loramac-node-3.4.0/src/boards/mcu/saml21/hpl/oscctrl/
Dhpl_oscctrl.c110 …hri_gclk_write_PCHCTRL_reg(GCLK, 0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK… in _oscctrl_init_referenced_generators()
139 …hri_gclk_write_PCHCTRL_reg(GCLK, 1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DPLL_GCLK… in _oscctrl_init_referenced_generators()
184 while (hri_gclk_read_SYNCBUSY_reg(GCLK)) in _oscctrl_init_referenced_generators()
/loramac-node-3.4.0/src/boards/SAMR34/
Duart-board.c39 …hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | ( 1 << GCLK_P… in UartMcuInit()
40 …hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | ( 1 << GCLK_P… in UartMcuInit()
Di2c-board.c48 hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM1_GCLK_ID_CORE, in I2cMcuInit()
50 hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM1_GCLK_ID_SLOW, in I2cMcuInit()
Dspi-board.c34 …hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM4_GCLK_ID_CORE, CONF_GCLK_SERCOM4_CORE_SRC | ( 1 << GCLK_P… in SpiInit()
35 …hri_gclk_write_PCHCTRL_reg( GCLK, SERCOM4_GCLK_ID_SLOW, CONF_GCLK_SERCOM4_SLOW_SRC | ( 1 << GCLK_P… in SpiInit()
Dboard.c79 …hri_gclk_write_PCHCTRL_reg( GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | ( 1 << GCLK_PCHCTRL_CHEN_Pos ) … in BoardInitMcu()
/loramac-node-3.4.0/src/boards/mcu/saml21/saml21b/include/
Dsaml21e15b.h392 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
471 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
Dsaml21e16b.h392 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
471 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
Dsaml21e17b.h392 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
471 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
Dsaml21e18b.h392 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
471 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
Dsaml21g16b.h392 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
471 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
Dsaml21g17b.h392 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
471 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
Dsaml21g18b.h392 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
471 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
Dsaml21j16b.h400 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
479 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
481 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
Dsaml21j17b.h400 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
479 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
481 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
Dsaml21j18b.h400 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
479 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
481 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
Dsaml21j18bu.h400 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ macro
479 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ macro
481 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */
/loramac-node-3.4.0/src/boards/mcu/saml21/hal/documentation/
Dusart_sync.rst50 And the SCK pin can't be set directly. Application can use a GCLK output PIN