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Searched refs:XCHAL_TIMER3_INTERRUPT (Results 1 – 17 of 17) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h328 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h428 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h428 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h428 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h451 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h449 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h439 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h439 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h527 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h527 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h529 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h465 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h531 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
Dcore.h575 XCHAL_SEP XCHAL_TIMER3_INTERRUPT
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h588 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h574 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h332 XCHAL_SEP XCHAL_TIMER3_INTERRUPT