1 /* 2 * xtensa/config/core.h -- HAL definitions dependent on CORE configuration 3 * 4 * This header file is sometimes referred to as the "compile-time HAL" or CHAL. 5 * It pulls definitions tailored for a specific Xtensa processor configuration. 6 * 7 * Sources for binaries meant to be configuration-independent generally avoid 8 * including this file (they may use the configuration-specific HAL library). 9 * It is normal for the HAL library source itself to include this file. 10 */ 11 12 /* 13 * Copyright (c) 2005-2016 Cadence Design Systems, Inc. 14 * 15 * Permission is hereby granted, free of charge, to any person obtaining 16 * a copy of this software and associated documentation files (the 17 * "Software"), to deal in the Software without restriction, including 18 * without limitation the rights to use, copy, modify, merge, publish, 19 * distribute, sublicense, and/or sell copies of the Software, and to 20 * permit persons to whom the Software is furnished to do so, subject to 21 * the following conditions: 22 * 23 * The above copyright notice and this permission notice shall be included 24 * in all copies or substantial portions of the Software. 25 * 26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 29 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 30 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 31 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 32 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 33 */ 34 35 36 #ifndef XTENSA_CONFIG_CORE_H 37 #define XTENSA_CONFIG_CORE_H 38 39 /* CONFIGURATION INDEPENDENT DEFINITIONS: */ 40 #ifdef __XTENSA__ 41 #include <xtensa/hal.h> 42 #include <xtensa/xtensa-versions.h> 43 #include <xtensa/xtensa-types.h> 44 #else 45 #include "../hal.h" 46 #include "../xtensa-versions.h" 47 #include "../xtensa-types.h" 48 #endif 49 50 /* CONFIGURATION SPECIFIC DEFINITIONS: */ 51 #ifdef __XTENSA__ 52 #include <xtensa/config/core-isa.h> 53 #include <xtensa/config/core-matmap.h> 54 #include <xtensa/config/tie.h> 55 #else 56 #include "core-isa.h" 57 #include "core-matmap.h" 58 #include "tie.h" 59 #endif 60 61 #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) 62 #ifdef __XTENSA__ 63 #include <xtensa/coreasm.h> 64 #include <xtensa/config/tie-asm.h> 65 #else 66 #include "coreasm.h" 67 #include "tie-asm.h" 68 #endif 69 #endif /*_ASMLANGUAGE or __ASSEMBLER__*/ 70 71 72 /*---------------------------------------------------------------------- 73 GENERAL 74 ----------------------------------------------------------------------*/ 75 76 /* 77 * Separators for macros that expand into arrays. 78 * These can be predefined by files that #include this one, 79 * when different separators are required. 80 */ 81 /* Element separator for macros that expand into 1-dimensional arrays: */ 82 #ifndef XCHAL_SEP 83 #define XCHAL_SEP , 84 #endif 85 /* Array separator for macros that expand into 2-dimensional arrays: */ 86 #ifndef XCHAL_SEP2 87 #define XCHAL_SEP2 },{ 88 #endif 89 90 /* Variadic macros for indexing and selecting. */ 91 /* parasoft-begin-suppress MISRA2012-RULE-20_7 "enclosing 'x' in parenthesis not appropriate when argument is __VA_ARGS__" */ 92 93 /* For MSVC: */ 94 #define XCHAL_EXPAND(x) x 95 96 /* XCHAL_SELECT(n, ...) expands argument 'n' (0..19) of '...'. */ 97 #define XCHAL__0(x, ...) x 98 #define XCHAL__1(a, x, ...) x 99 #define XCHAL__2(a,b, x, ...) x 100 #define XCHAL__3(a,b,c, x, ...) x 101 #define XCHAL__4(a,b,c,d, x, ...) x 102 #define XCHAL__5(a,b,c,d,e, x, ...) x 103 #define XCHAL__6(a,b,c,d,e,f, x, ...) x 104 #define XCHAL__7(a,b,c,d,e,f,g, x, ...) x 105 #define XCHAL__8(a,b,c,d,e,f,g,h, x, ...) x 106 #define XCHAL__9(a,b,c,d,e,f,g,h,i, x, ...) x 107 #define XCHAL__10(a,b,c,d,e,f,g,h,i,j, x, ...) x 108 #define XCHAL__11(a,b,c,d,e,f,g,h,i,j,k, x, ...) x 109 #define XCHAL__12(a,b,c,d,e,f,g,h,i,j,k,l, x, ...) x 110 #define XCHAL__13(a,b,c,d,e,f,g,h,i,j,k,l,m, x, ...) x 111 #define XCHAL__14(a,b,c,d,e,f,g,h,i,j,k,l,m,n, x, ...) x 112 #define XCHAL__15(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o, x, ...) x 113 #define XCHAL__16(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p, x, ...) x 114 #define XCHAL__17(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q, x, ...) x 115 #define XCHAL__18(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r, x, ...) x 116 #define XCHAL__19(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s, x, ...) x 117 #define XCHAL__SELECT(n, ...) XCHAL__ ## n(__VA_ARGS__) 118 #define XCHAL_SELECT(n, ...) XCHAL_EXPAND(XCHAL__SELECT(n, __VA_ARGS__)) 119 /* parasoft-end-suppress MISRA2012-RULE-20_7 "enclosing 'x' in parenthesis not appropriate when argument is __VA_ARGS__" */ 120 121 122 /*---------------------------------------------------------------------- 123 ERRATA 124 ----------------------------------------------------------------------*/ 125 126 /* 127 * Erratum T1020.H13, T1030.H7, T1040.H10, T1050.H4 (fixed in T1040.3 and T1050.1; 128 * relevant only in XEA1, kernel-vector mode, level-one interrupts and overflows enabled): 129 */ 130 #define XCHAL_MAYHAVE_ERRATUM_XEA1KWIN (XCHAL_HAVE_XEA1 && \ 131 (XCHAL_HW_RELEASE_AT_OR_BELOW(1040,2) != 0 \ 132 || XCHAL_HW_RELEASE_AT(1050,0))) 133 /* 134 * Erratum 453 present in RE-2013.2 up to RF-2014.0, fixed in RF-2014.1. 135 * Applies to specific set of configuration options. 136 * Part of the workaround is to add ISYNC at certain points in the code. 137 * The workaround gated by this macro can be disabled if not needed, e.g. if 138 * zero-overhead loop buffer will be disabled, by defining _NO_ERRATUM_453. 139 */ 140 #if ( XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \ 141 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \ 142 XCHAL_ICACHE_SIZE != 0 && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \ 143 XCHAL_HAVE_LOOPS && XCHAL_LOOP_BUFFER_SIZE != 0 && \ 144 XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453) ) 145 #define XCHAL_ERRATUM_453 1 146 #else 147 #define XCHAL_ERRATUM_453 0 148 #endif 149 150 /* 151 * Erratum 497 present in RE-2012.2 up to RG/RF-2015.2 152 * Applies to specific set of configuration options. 153 * Workaround is to add MEMWs after at most 8 cache WB instructions 154 */ 155 #if ( ((XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2012_0 && \ 156 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) || \ 157 (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RG_2015_0 && \ 158 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2) \ 159 ) && \ 160 XCHAL_DCACHE_IS_WRITEBACK && \ 161 XCHAL_HAVE_AXI && \ 162 XCHAL_HAVE_PIF_WR_RESP && \ 163 XCHAL_HAVE_PIF_REQ_ATTR && !defined(_NO_ERRATUM_497) \ 164 ) 165 #define XCHAL_ERRATUM_497 1 166 #else 167 #define XCHAL_ERRATUM_497 0 168 #endif 169 170 171 /*---------------------------------------------------------------------- 172 ISA 173 ----------------------------------------------------------------------*/ 174 175 #if XCHAL_HAVE_BE 176 # define XCHAL_HAVE_LE 0 177 # define XCHAL_MEMORY_ORDER XTHAL_BIGENDIAN 178 #else 179 # define XCHAL_HAVE_LE 1 180 # define XCHAL_MEMORY_ORDER XTHAL_LITTLEENDIAN 181 #endif 182 183 184 185 /*---------------------------------------------------------------------- 186 INTERRUPTS 187 ----------------------------------------------------------------------*/ 188 189 /* Indexing macros: */ 190 #define I_XCHAL_INTLEVEL_MASK(n) XCHAL_INTLEVEL ## n ## _MASK 191 #define XCHAL_INTLEVEL_MASK(n) I_XCHAL_INTLEVEL_MASK(n) /* n = 0 .. 15 */ 192 #define I_XCHAL_INTLEVEL_ANDBELOWMASK(n) XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK 193 #define XCHAL_INTLEVEL_ANDBELOW_MASK(n) I_XCHAL_INTLEVEL_ANDBELOWMASK(n) /* n = 0 .. 15 */ 194 #define I_XCHAL_INTLEVEL_NUM(n) XCHAL_INTLEVEL ## n ## _NUM 195 #define XCHAL_INTLEVEL_NUM(n) I_XCHAL_INTLEVEL_NUM(n) /* n = 0 .. 15 */ 196 #define I_XCHAL_INT_LEVEL(n) XCHAL_INT ## n ## _LEVEL 197 #define XCHAL_INT_LEVEL(n) I_XCHAL_INT_LEVEL(n) /* n = 0 .. 31 */ 198 #define I_XCHAL_INT_TYPE(n) XCHAL_INT ## n ## _TYPE 199 #define XCHAL_INT_TYPE(n) I_XCHAL_INT_TYPE(n) /* n = 0 .. 31 */ 200 #define I_XCHAL_TIMER_INTERRUPT(n) XCHAL_TIMER ## n ## _INTERRUPT 201 #define XCHAL_TIMER_INTERRUPT(n) I_XCHAL_TIMER_INTERRUPT(n) /* n = 0 .. 3 */ 202 203 204 #define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS XCHAL_HAVE_HIGHPRI_INTERRUPTS 205 #define XCHAL_NUM_LOWPRI_LEVELS 1 /* number of low-priority interrupt levels (always 1) */ 206 #define XCHAL_FIRST_HIGHPRI_LEVEL (XCHAL_NUM_LOWPRI_LEVELS+1) /* level of first high-priority interrupt (always 2) */ 207 /* Note: 1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15 */ 208 209 /* These values are constant for existing Xtensa processor implementations: */ 210 #if (XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2) 211 212 #define XCHAL_INTLEVEL0_MASK UINT32_C(0x00000000) 213 #define XCHAL_INTLEVEL8_MASK UINT32_C(0x00000000) 214 #define XCHAL_INTLEVEL9_MASK UINT32_C(0x00000000) 215 #define XCHAL_INTLEVEL10_MASK UINT32_C(0x00000000) 216 #define XCHAL_INTLEVEL11_MASK UINT32_C(0x00000000) 217 #define XCHAL_INTLEVEL12_MASK UINT32_C(0x00000000) 218 #define XCHAL_INTLEVEL13_MASK UINT32_C(0x00000000) 219 #define XCHAL_INTLEVEL14_MASK UINT32_C(0x00000000) 220 #define XCHAL_INTLEVEL15_MASK UINT32_C(0x00000000) 221 222 /* Array of masks of interrupts at each interrupt level: */ 223 #define XCHAL_INTLEVEL_MASKS XCHAL_INTLEVEL0_MASK \ 224 XCHAL_SEP XCHAL_INTLEVEL1_MASK \ 225 XCHAL_SEP XCHAL_INTLEVEL2_MASK \ 226 XCHAL_SEP XCHAL_INTLEVEL3_MASK \ 227 XCHAL_SEP XCHAL_INTLEVEL4_MASK \ 228 XCHAL_SEP XCHAL_INTLEVEL5_MASK \ 229 XCHAL_SEP XCHAL_INTLEVEL6_MASK \ 230 XCHAL_SEP XCHAL_INTLEVEL7_MASK \ 231 XCHAL_SEP XCHAL_INTLEVEL8_MASK \ 232 XCHAL_SEP XCHAL_INTLEVEL9_MASK \ 233 XCHAL_SEP XCHAL_INTLEVEL10_MASK \ 234 XCHAL_SEP XCHAL_INTLEVEL11_MASK \ 235 XCHAL_SEP XCHAL_INTLEVEL12_MASK \ 236 XCHAL_SEP XCHAL_INTLEVEL13_MASK \ 237 XCHAL_SEP XCHAL_INTLEVEL14_MASK \ 238 XCHAL_SEP XCHAL_INTLEVEL15_MASK 239 240 /* These values are constant for existing Xtensa processor implementations: */ 241 #define XCHAL_INTLEVEL0_ANDBELOW_MASK UINT32_C(0x00000000) 242 #define XCHAL_INTLEVEL8_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 243 #define XCHAL_INTLEVEL9_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 244 #define XCHAL_INTLEVEL10_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 245 #define XCHAL_INTLEVEL11_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 246 #define XCHAL_INTLEVEL12_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 247 #define XCHAL_INTLEVEL13_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 248 #define XCHAL_INTLEVEL14_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 249 #define XCHAL_INTLEVEL15_ANDBELOW_MASK XCHAL_INTLEVEL7_ANDBELOW_MASK 250 251 /* Mask of all low-priority interrupts: */ 252 #define XCHAL_LOWPRI_MASK XCHAL_INTLEVEL1_ANDBELOW_MASK 253 254 /* Mask of all interrupts masked by PS.EXCM (or CEXCM): */ 255 #define XCHAL_EXCM_MASK XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL) 256 257 /* Array of masks of interrupts at each range 1..n of interrupt levels: */ 258 #define XCHAL_INTLEVEL_ANDBELOW_MASKS XCHAL_INTLEVEL0_ANDBELOW_MASK \ 259 XCHAL_SEP XCHAL_INTLEVEL1_ANDBELOW_MASK \ 260 XCHAL_SEP XCHAL_INTLEVEL2_ANDBELOW_MASK \ 261 XCHAL_SEP XCHAL_INTLEVEL3_ANDBELOW_MASK \ 262 XCHAL_SEP XCHAL_INTLEVEL4_ANDBELOW_MASK \ 263 XCHAL_SEP XCHAL_INTLEVEL5_ANDBELOW_MASK \ 264 XCHAL_SEP XCHAL_INTLEVEL6_ANDBELOW_MASK \ 265 XCHAL_SEP XCHAL_INTLEVEL7_ANDBELOW_MASK \ 266 XCHAL_SEP XCHAL_INTLEVEL8_ANDBELOW_MASK \ 267 XCHAL_SEP XCHAL_INTLEVEL9_ANDBELOW_MASK \ 268 XCHAL_SEP XCHAL_INTLEVEL10_ANDBELOW_MASK \ 269 XCHAL_SEP XCHAL_INTLEVEL11_ANDBELOW_MASK \ 270 XCHAL_SEP XCHAL_INTLEVEL12_ANDBELOW_MASK \ 271 XCHAL_SEP XCHAL_INTLEVEL13_ANDBELOW_MASK \ 272 XCHAL_SEP XCHAL_INTLEVEL14_ANDBELOW_MASK \ 273 XCHAL_SEP XCHAL_INTLEVEL15_ANDBELOW_MASK 274 275 #if 0 /*XCHAL_HAVE_NMI*/ 276 /* NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n): */ 277 # define XCHAL_NMILEVEL (XCHAL_NUM_INTLEVELS+1) 278 #endif 279 280 /* Array of levels of each possible interrupt: */ 281 #define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \ 282 XCHAL_SEP XCHAL_INT1_LEVEL \ 283 XCHAL_SEP XCHAL_INT2_LEVEL \ 284 XCHAL_SEP XCHAL_INT3_LEVEL \ 285 XCHAL_SEP XCHAL_INT4_LEVEL \ 286 XCHAL_SEP XCHAL_INT5_LEVEL \ 287 XCHAL_SEP XCHAL_INT6_LEVEL \ 288 XCHAL_SEP XCHAL_INT7_LEVEL \ 289 XCHAL_SEP XCHAL_INT8_LEVEL \ 290 XCHAL_SEP XCHAL_INT9_LEVEL \ 291 XCHAL_SEP XCHAL_INT10_LEVEL \ 292 XCHAL_SEP XCHAL_INT11_LEVEL \ 293 XCHAL_SEP XCHAL_INT12_LEVEL \ 294 XCHAL_SEP XCHAL_INT13_LEVEL \ 295 XCHAL_SEP XCHAL_INT14_LEVEL \ 296 XCHAL_SEP XCHAL_INT15_LEVEL \ 297 XCHAL_SEP XCHAL_INT16_LEVEL \ 298 XCHAL_SEP XCHAL_INT17_LEVEL \ 299 XCHAL_SEP XCHAL_INT18_LEVEL \ 300 XCHAL_SEP XCHAL_INT19_LEVEL \ 301 XCHAL_SEP XCHAL_INT20_LEVEL \ 302 XCHAL_SEP XCHAL_INT21_LEVEL \ 303 XCHAL_SEP XCHAL_INT22_LEVEL \ 304 XCHAL_SEP XCHAL_INT23_LEVEL \ 305 XCHAL_SEP XCHAL_INT24_LEVEL \ 306 XCHAL_SEP XCHAL_INT25_LEVEL \ 307 XCHAL_SEP XCHAL_INT26_LEVEL \ 308 XCHAL_SEP XCHAL_INT27_LEVEL \ 309 XCHAL_SEP XCHAL_INT28_LEVEL \ 310 XCHAL_SEP XCHAL_INT29_LEVEL \ 311 XCHAL_SEP XCHAL_INT30_LEVEL \ 312 XCHAL_SEP XCHAL_INT31_LEVEL 313 314 /* Array of types of each possible interrupt: */ 315 #define XCHAL_INT_TYPES XCHAL_INT0_TYPE \ 316 XCHAL_SEP XCHAL_INT1_TYPE \ 317 XCHAL_SEP XCHAL_INT2_TYPE \ 318 XCHAL_SEP XCHAL_INT3_TYPE \ 319 XCHAL_SEP XCHAL_INT4_TYPE \ 320 XCHAL_SEP XCHAL_INT5_TYPE \ 321 XCHAL_SEP XCHAL_INT6_TYPE \ 322 XCHAL_SEP XCHAL_INT7_TYPE \ 323 XCHAL_SEP XCHAL_INT8_TYPE \ 324 XCHAL_SEP XCHAL_INT9_TYPE \ 325 XCHAL_SEP XCHAL_INT10_TYPE \ 326 XCHAL_SEP XCHAL_INT11_TYPE \ 327 XCHAL_SEP XCHAL_INT12_TYPE \ 328 XCHAL_SEP XCHAL_INT13_TYPE \ 329 XCHAL_SEP XCHAL_INT14_TYPE \ 330 XCHAL_SEP XCHAL_INT15_TYPE \ 331 XCHAL_SEP XCHAL_INT16_TYPE \ 332 XCHAL_SEP XCHAL_INT17_TYPE \ 333 XCHAL_SEP XCHAL_INT18_TYPE \ 334 XCHAL_SEP XCHAL_INT19_TYPE \ 335 XCHAL_SEP XCHAL_INT20_TYPE \ 336 XCHAL_SEP XCHAL_INT21_TYPE \ 337 XCHAL_SEP XCHAL_INT22_TYPE \ 338 XCHAL_SEP XCHAL_INT23_TYPE \ 339 XCHAL_SEP XCHAL_INT24_TYPE \ 340 XCHAL_SEP XCHAL_INT25_TYPE \ 341 XCHAL_SEP XCHAL_INT26_TYPE \ 342 XCHAL_SEP XCHAL_INT27_TYPE \ 343 XCHAL_SEP XCHAL_INT28_TYPE \ 344 XCHAL_SEP XCHAL_INT29_TYPE \ 345 XCHAL_SEP XCHAL_INT30_TYPE \ 346 XCHAL_SEP XCHAL_INT31_TYPE 347 348 /* Array of masks of interrupts for each type of interrupt: */ 349 #define XCHAL_INTTYPE_MASKS XCHAL_INTTYPE_MASK_UNCONFIGURED \ 350 XCHAL_SEP XCHAL_INTTYPE_MASK_SOFTWARE \ 351 XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_EDGE \ 352 XCHAL_SEP XCHAL_INTTYPE_MASK_EXTERN_LEVEL \ 353 XCHAL_SEP XCHAL_INTTYPE_MASK_TIMER \ 354 XCHAL_SEP XCHAL_INTTYPE_MASK_NMI \ 355 XCHAL_SEP XCHAL_INTTYPE_MASK_WRITE_ERROR \ 356 XCHAL_SEP XCHAL_INTTYPE_MASK_IDMA_DONE \ 357 XCHAL_SEP XCHAL_INTTYPE_MASK_IDMA_ERR \ 358 XCHAL_SEP XCHAL_INTTYPE_MASK_GS_ERR \ 359 XCHAL_SEP XCHAL_INTTYPE_MASK_L2_ERR 360 361 /* Interrupts that can be cleared using the INTCLEAR special register: */ 362 #define XCHAL_INTCLEARABLE_MASK (XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR) 363 /* Interrupts that can be triggered using the INTSET special register: */ 364 #define XCHAL_INTSETTABLE_MASK XCHAL_INTTYPE_MASK_SOFTWARE 365 366 367 /* For backward compatibility and for the array macros, define macros for 368 * each unconfigured interrupt number (unfortunately, the value of 369 * XTHAL_INTTYPE_UNCONFIGURED is not zero): */ 370 #if XCHAL_NUM_INTERRUPTS == 0 371 # define XCHAL_INT0_LEVEL 0 372 # define XCHAL_INT0_TYPE XTHAL_INTTYPE_UNCONFIGURED 373 #endif 374 #if XCHAL_NUM_INTERRUPTS <= 1 375 # define XCHAL_INT1_LEVEL 0 376 # define XCHAL_INT1_TYPE XTHAL_INTTYPE_UNCONFIGURED 377 #endif 378 #if XCHAL_NUM_INTERRUPTS <= 2 379 # define XCHAL_INT2_LEVEL 0 380 # define XCHAL_INT2_TYPE XTHAL_INTTYPE_UNCONFIGURED 381 #endif 382 #if XCHAL_NUM_INTERRUPTS <= 3 383 # define XCHAL_INT3_LEVEL 0 384 # define XCHAL_INT3_TYPE XTHAL_INTTYPE_UNCONFIGURED 385 #endif 386 #if XCHAL_NUM_INTERRUPTS <= 4 387 # define XCHAL_INT4_LEVEL 0 388 # define XCHAL_INT4_TYPE XTHAL_INTTYPE_UNCONFIGURED 389 #endif 390 #if XCHAL_NUM_INTERRUPTS <= 5 391 # define XCHAL_INT5_LEVEL 0 392 # define XCHAL_INT5_TYPE XTHAL_INTTYPE_UNCONFIGURED 393 #endif 394 #if XCHAL_NUM_INTERRUPTS <= 6 395 # define XCHAL_INT6_LEVEL 0 396 # define XCHAL_INT6_TYPE XTHAL_INTTYPE_UNCONFIGURED 397 #endif 398 #if XCHAL_NUM_INTERRUPTS <= 7 399 # define XCHAL_INT7_LEVEL 0 400 # define XCHAL_INT7_TYPE XTHAL_INTTYPE_UNCONFIGURED 401 #endif 402 #if XCHAL_NUM_INTERRUPTS <= 8 403 # define XCHAL_INT8_LEVEL 0 404 # define XCHAL_INT8_TYPE XTHAL_INTTYPE_UNCONFIGURED 405 #endif 406 #if XCHAL_NUM_INTERRUPTS <= 9 407 # define XCHAL_INT9_LEVEL 0 408 # define XCHAL_INT9_TYPE XTHAL_INTTYPE_UNCONFIGURED 409 #endif 410 #if XCHAL_NUM_INTERRUPTS <= 10 411 # define XCHAL_INT10_LEVEL 0 412 # define XCHAL_INT10_TYPE XTHAL_INTTYPE_UNCONFIGURED 413 #endif 414 #if XCHAL_NUM_INTERRUPTS <= 11 415 # define XCHAL_INT11_LEVEL 0 416 # define XCHAL_INT11_TYPE XTHAL_INTTYPE_UNCONFIGURED 417 #endif 418 #if XCHAL_NUM_INTERRUPTS <= 12 419 # define XCHAL_INT12_LEVEL 0 420 # define XCHAL_INT12_TYPE XTHAL_INTTYPE_UNCONFIGURED 421 #endif 422 #if XCHAL_NUM_INTERRUPTS <= 13 423 # define XCHAL_INT13_LEVEL 0 424 # define XCHAL_INT13_TYPE XTHAL_INTTYPE_UNCONFIGURED 425 #endif 426 #if XCHAL_NUM_INTERRUPTS <= 14 427 # define XCHAL_INT14_LEVEL 0 428 # define XCHAL_INT14_TYPE XTHAL_INTTYPE_UNCONFIGURED 429 #endif 430 #if XCHAL_NUM_INTERRUPTS <= 15 431 # define XCHAL_INT15_LEVEL 0 432 # define XCHAL_INT15_TYPE XTHAL_INTTYPE_UNCONFIGURED 433 #endif 434 #if XCHAL_NUM_INTERRUPTS <= 16 435 # define XCHAL_INT16_LEVEL 0 436 # define XCHAL_INT16_TYPE XTHAL_INTTYPE_UNCONFIGURED 437 #endif 438 #if XCHAL_NUM_INTERRUPTS <= 17 439 # define XCHAL_INT17_LEVEL 0 440 # define XCHAL_INT17_TYPE XTHAL_INTTYPE_UNCONFIGURED 441 #endif 442 #if XCHAL_NUM_INTERRUPTS <= 18 443 # define XCHAL_INT18_LEVEL 0 444 # define XCHAL_INT18_TYPE XTHAL_INTTYPE_UNCONFIGURED 445 #endif 446 #if XCHAL_NUM_INTERRUPTS <= 19 447 # define XCHAL_INT19_LEVEL 0 448 # define XCHAL_INT19_TYPE XTHAL_INTTYPE_UNCONFIGURED 449 #endif 450 #if XCHAL_NUM_INTERRUPTS <= 20 451 # define XCHAL_INT20_LEVEL 0 452 # define XCHAL_INT20_TYPE XTHAL_INTTYPE_UNCONFIGURED 453 #endif 454 #if XCHAL_NUM_INTERRUPTS <= 21 455 # define XCHAL_INT21_LEVEL 0 456 # define XCHAL_INT21_TYPE XTHAL_INTTYPE_UNCONFIGURED 457 #endif 458 #if XCHAL_NUM_INTERRUPTS <= 22 459 # define XCHAL_INT22_LEVEL 0 460 # define XCHAL_INT22_TYPE XTHAL_INTTYPE_UNCONFIGURED 461 #endif 462 #if XCHAL_NUM_INTERRUPTS <= 23 463 # define XCHAL_INT23_LEVEL 0 464 # define XCHAL_INT23_TYPE XTHAL_INTTYPE_UNCONFIGURED 465 #endif 466 #if XCHAL_NUM_INTERRUPTS <= 24 467 # define XCHAL_INT24_LEVEL 0 468 # define XCHAL_INT24_TYPE XTHAL_INTTYPE_UNCONFIGURED 469 #endif 470 #if XCHAL_NUM_INTERRUPTS <= 25 471 # define XCHAL_INT25_LEVEL 0 472 # define XCHAL_INT25_TYPE XTHAL_INTTYPE_UNCONFIGURED 473 #endif 474 #if XCHAL_NUM_INTERRUPTS <= 26 475 # define XCHAL_INT26_LEVEL 0 476 # define XCHAL_INT26_TYPE XTHAL_INTTYPE_UNCONFIGURED 477 #endif 478 #if XCHAL_NUM_INTERRUPTS <= 27 479 # define XCHAL_INT27_LEVEL 0 480 # define XCHAL_INT27_TYPE XTHAL_INTTYPE_UNCONFIGURED 481 #endif 482 #if XCHAL_NUM_INTERRUPTS <= 28 483 # define XCHAL_INT28_LEVEL 0 484 # define XCHAL_INT28_TYPE XTHAL_INTTYPE_UNCONFIGURED 485 #endif 486 #if XCHAL_NUM_INTERRUPTS <= 29 487 # define XCHAL_INT29_LEVEL 0 488 # define XCHAL_INT29_TYPE XTHAL_INTTYPE_UNCONFIGURED 489 #endif 490 #if XCHAL_NUM_INTERRUPTS <= 30 491 # define XCHAL_INT30_LEVEL 0 492 # define XCHAL_INT30_TYPE XTHAL_INTTYPE_UNCONFIGURED 493 #endif 494 #if XCHAL_NUM_INTERRUPTS <= 31 495 # define XCHAL_INT31_LEVEL 0 496 # define XCHAL_INT31_TYPE XTHAL_INTTYPE_UNCONFIGURED 497 #endif 498 499 500 /* 501 * Masks and levels corresponding to each *external* interrupt. 502 */ 503 504 #define XCHAL_EXTINT0_MASK (UINT32_C(1) << XCHAL_EXTINT0_NUM) 505 #define XCHAL_EXTINT0_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM) 506 #define XCHAL_EXTINT1_MASK (UINT32_C(1) << XCHAL_EXTINT1_NUM) 507 #define XCHAL_EXTINT1_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM) 508 #define XCHAL_EXTINT2_MASK (UINT32_C(1) << XCHAL_EXTINT2_NUM) 509 #define XCHAL_EXTINT2_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM) 510 #define XCHAL_EXTINT3_MASK (UINT32_C(1) << XCHAL_EXTINT3_NUM) 511 #define XCHAL_EXTINT3_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM) 512 #define XCHAL_EXTINT4_MASK (UINT32_C(1) << XCHAL_EXTINT4_NUM) 513 #define XCHAL_EXTINT4_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM) 514 #define XCHAL_EXTINT5_MASK (UINT32_C(1) << XCHAL_EXTINT5_NUM) 515 #define XCHAL_EXTINT5_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM) 516 #define XCHAL_EXTINT6_MASK (UINT32_C(1) << XCHAL_EXTINT6_NUM) 517 #define XCHAL_EXTINT6_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM) 518 #define XCHAL_EXTINT7_MASK (UINT32_C(1) << XCHAL_EXTINT7_NUM) 519 #define XCHAL_EXTINT7_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM) 520 #define XCHAL_EXTINT8_MASK (UINT32_C(1) << XCHAL_EXTINT8_NUM) 521 #define XCHAL_EXTINT8_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM) 522 #define XCHAL_EXTINT9_MASK (UINT32_C(1) << XCHAL_EXTINT9_NUM) 523 #define XCHAL_EXTINT9_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM) 524 #define XCHAL_EXTINT10_MASK (UINT32_C(1) << XCHAL_EXTINT10_NUM) 525 #define XCHAL_EXTINT10_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM) 526 #define XCHAL_EXTINT11_MASK (UINT32_C(1) << XCHAL_EXTINT11_NUM) 527 #define XCHAL_EXTINT11_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM) 528 #define XCHAL_EXTINT12_MASK (UINT32_C(1) << XCHAL_EXTINT12_NUM) 529 #define XCHAL_EXTINT12_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM) 530 #define XCHAL_EXTINT13_MASK (UINT32_C(1) << XCHAL_EXTINT13_NUM) 531 #define XCHAL_EXTINT13_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM) 532 #define XCHAL_EXTINT14_MASK (UINT32_C(1) << XCHAL_EXTINT14_NUM) 533 #define XCHAL_EXTINT14_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM) 534 #define XCHAL_EXTINT15_MASK (UINT32_C(1) << XCHAL_EXTINT15_NUM) 535 #define XCHAL_EXTINT15_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM) 536 #define XCHAL_EXTINT16_MASK (UINT32_C(1) << XCHAL_EXTINT16_NUM) 537 #define XCHAL_EXTINT16_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM) 538 #define XCHAL_EXTINT17_MASK (UINT32_C(1) << XCHAL_EXTINT17_NUM) 539 #define XCHAL_EXTINT17_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM) 540 #define XCHAL_EXTINT18_MASK (UINT32_C(1) << XCHAL_EXTINT18_NUM) 541 #define XCHAL_EXTINT18_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM) 542 #define XCHAL_EXTINT19_MASK (UINT32_C(1) << XCHAL_EXTINT19_NUM) 543 #define XCHAL_EXTINT19_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM) 544 #define XCHAL_EXTINT20_MASK (UINT32_C(1) << XCHAL_EXTINT20_NUM) 545 #define XCHAL_EXTINT20_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM) 546 #define XCHAL_EXTINT21_MASK (UINT32_C(1) << XCHAL_EXTINT21_NUM) 547 #define XCHAL_EXTINT21_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM) 548 #define XCHAL_EXTINT22_MASK (UINT32_C(1) << XCHAL_EXTINT22_NUM) 549 #define XCHAL_EXTINT22_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM) 550 #define XCHAL_EXTINT23_MASK (UINT32_C(1) << XCHAL_EXTINT23_NUM) 551 #define XCHAL_EXTINT23_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM) 552 #define XCHAL_EXTINT24_MASK (UINT32_C(1) << XCHAL_EXTINT24_NUM) 553 #define XCHAL_EXTINT24_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM) 554 #define XCHAL_EXTINT25_MASK (UINT32_C(1) << XCHAL_EXTINT25_NUM) 555 #define XCHAL_EXTINT25_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM) 556 #define XCHAL_EXTINT26_MASK (UINT32_C(1) << XCHAL_EXTINT26_NUM) 557 #define XCHAL_EXTINT26_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM) 558 #define XCHAL_EXTINT27_MASK (UINT32_C(1) << XCHAL_EXTINT27_NUM) 559 #define XCHAL_EXTINT27_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM) 560 #define XCHAL_EXTINT28_MASK (UINT32_C(1) << XCHAL_EXTINT28_NUM) 561 #define XCHAL_EXTINT28_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM) 562 #define XCHAL_EXTINT29_MASK (UINT32_C(1) << XCHAL_EXTINT29_NUM) 563 #define XCHAL_EXTINT29_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM) 564 #define XCHAL_EXTINT30_MASK (UINT32_C(1) << XCHAL_EXTINT30_NUM) 565 #define XCHAL_EXTINT30_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM) 566 #define XCHAL_EXTINT31_MASK (UINT32_C(1) << XCHAL_EXTINT31_NUM) 567 #define XCHAL_EXTINT31_LEVEL XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM) 568 569 #endif /* (XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2) */ 570 571 /* Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3): */ 572 #define XCHAL_TIMER_INTERRUPTS XCHAL_TIMER0_INTERRUPT \ 573 XCHAL_SEP XCHAL_TIMER1_INTERRUPT \ 574 XCHAL_SEP XCHAL_TIMER2_INTERRUPT \ 575 XCHAL_SEP XCHAL_TIMER3_INTERRUPT 576 577 578 /*---------------------------------------------------------------------- 579 EXCEPTIONS and VECTORS 580 ----------------------------------------------------------------------*/ 581 582 #if (XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2) 583 584 /* For backward compatibility ONLY -- DO NOT USE (will be removed in future release): */ 585 #ifdef XCHAL_USER_VECTOR_VADDR 586 #define XCHAL_PROGRAMEXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR 587 #define XCHAL_USEREXC_VECTOR_VADDR XCHAL_USER_VECTOR_VADDR 588 #endif 589 #ifdef XCHAL_USER_VECTOR_PADDR 590 # define XCHAL_PROGRAMEXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR 591 # define XCHAL_USEREXC_VECTOR_PADDR XCHAL_USER_VECTOR_PADDR 592 #endif 593 #ifdef XCHAL_KERNEL_VECTOR_VADDR 594 # define XCHAL_STACKEDEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR 595 # define XCHAL_KERNELEXC_VECTOR_VADDR XCHAL_KERNEL_VECTOR_VADDR 596 #endif 597 #ifdef XCHAL_KERNEL_VECTOR_PADDR 598 # define XCHAL_STACKEDEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR 599 # define XCHAL_KERNELEXC_VECTOR_PADDR XCHAL_KERNEL_VECTOR_PADDR 600 #endif 601 602 /* Indexing macros: */ 603 #define I_XCHAL_INTLEVEL_VECTOR_VADDR(n) XCHAL_INTLEVEL ## n ## _VECTOR_VADDR 604 #define XCHAL_INTLEVEL_VECTOR_VADDR(n) I_XCHAL_INTLEVEL_VECTOR_VADDR(n) /* n = 0 .. 15 */ 605 606 #endif /* XCHAL_HAVE_XEA1 || XCHAL_HAVE_XEA2 */ 607 608 609 /*---------------------------------------------------------------------- 610 DEPRECATED 611 (but still used by RTOS ports etc.) 612 ----------------------------------------------------------------------*/ 613 /* PS (special register number 230): */ 614 #define XCHAL_PS_VALIDMASK 0x00070F3F 615 #define XCHAL_PS_INTLEVEL_BITS 4 616 #define XCHAL_PS_INTLEVEL_NUM 16 617 #define XCHAL_PS_INTLEVEL_SHIFT 0 618 #define XCHAL_PS_INTLEVEL_MASK 0x0000000F 619 #define XCHAL_PS_EXCM_BITS 1 620 #define XCHAL_PS_EXCM_NUM 2 621 #define XCHAL_PS_EXCM_SHIFT 4 622 #define XCHAL_PS_EXCM_MASK 0x00000010 623 #define XCHAL_PS_UM_BITS 1 624 #define XCHAL_PS_UM_NUM 2 625 #define XCHAL_PS_UM_SHIFT 5 626 #define XCHAL_PS_UM_MASK 0x00000020 627 #define XCHAL_PS_RING_BITS 2 628 #define XCHAL_PS_RING_NUM 4 629 #define XCHAL_PS_RING_SHIFT 6 630 #define XCHAL_PS_RING_MASK 0x000000C0 631 #define XCHAL_PS_OWB_BITS 4 632 #define XCHAL_PS_OWB_NUM 16 633 #define XCHAL_PS_OWB_SHIFT 8 634 #define XCHAL_PS_OWB_MASK 0x00000F00 635 #define XCHAL_PS_CALLINC_BITS 2 636 #define XCHAL_PS_CALLINC_NUM 4 637 #define XCHAL_PS_CALLINC_SHIFT 16 638 #define XCHAL_PS_CALLINC_MASK 0x00030000 639 #define XCHAL_PS_WOE_BITS 1 640 #define XCHAL_PS_WOE_NUM 2 641 #define XCHAL_PS_WOE_SHIFT 18 642 #define XCHAL_PS_WOE_MASK 0x00040000 643 644 645 /*---------------------------------------------------------------------- 646 TIMERS 647 ----------------------------------------------------------------------*/ 648 649 650 /*---------------------------------------------------------------------- 651 INTERNAL I/D RAM/ROMs and XLMI 652 ----------------------------------------------------------------------*/ 653 654 655 /*---------------------------------------------------------------------- 656 CACHE 657 ----------------------------------------------------------------------*/ 658 659 660 /* Default PREFCTL value to enable prefetch. */ 661 #if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0 662 #define XCHAL_CACHE_PREFCTL_DEFAULT UINT32_C(0x00044) /* enabled, not aggressive */ 663 #elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0 664 #define XCHAL_CACHE_PREFCTL_DEFAULT UINT32_C(0x01044) /* + enable prefetch to L1 */ 665 #elif ((XCHAL_PREFETCH_ENTRIES >= 16) && XCHAL_HAVE_CACHE_BLOCKOPS) 666 #define XCHAL_CACHE_PREFCTL_DEFAULT UINT32_C(0x81044) /* 12 entries for block ops */ 667 #elif ((XCHAL_PREFETCH_ENTRIES >= 8) && XCHAL_HAVE_CACHE_BLOCKOPS) 668 #define XCHAL_CACHE_PREFCTL_DEFAULT UINT32_C(0x51044) /* 5 entries for block ops */ 669 #else 670 #define XCHAL_CACHE_PREFCTL_DEFAULT UINT32_C(0x01044) /* 0 entries for block ops */ 671 #endif 672 673 674 /* Max for both I-cache and D-cache (used for general alignment): */ 675 #if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE 676 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_ICACHE_LINEWIDTH 677 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_ICACHE_LINESIZE 678 #else 679 # define XCHAL_CACHE_LINEWIDTH_MAX XCHAL_DCACHE_LINEWIDTH 680 # define XCHAL_CACHE_LINESIZE_MAX XCHAL_DCACHE_LINESIZE 681 #endif 682 683 #define XCHAL_ICACHE_SETSIZE (UINT32_C(1) << XCHAL_ICACHE_SETWIDTH) 684 #define XCHAL_DCACHE_SETSIZE (UINT32_C(1) << XCHAL_DCACHE_SETWIDTH) 685 /* Max for both I and D caches (used for cache-coherency page alignment): */ 686 #if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH 687 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_ICACHE_SETWIDTH 688 # define XCHAL_CACHE_SETSIZE_MAX XCHAL_ICACHE_SETSIZE 689 #else 690 # define XCHAL_CACHE_SETWIDTH_MAX XCHAL_DCACHE_SETWIDTH 691 # define XCHAL_CACHE_SETSIZE_MAX XCHAL_DCACHE_SETSIZE 692 #endif 693 694 /* Instruction cache tag bits: */ 695 #define XCHAL_ICACHE_TAG_V_SHIFT 0 696 #define XCHAL_ICACHE_TAG_V 0x1 /* valid bit */ 697 #if XCHAL_ICACHE_WAYS > 1 698 # define XCHAL_ICACHE_TAG_F_SHIFT 1 699 # define XCHAL_ICACHE_TAG_F 0x2 /* fill (LRU) bit */ 700 #else 701 # define XCHAL_ICACHE_TAG_F_SHIFT 0 702 # define XCHAL_ICACHE_TAG_F 0 /* no fill (LRU) bit */ 703 #endif 704 #if XCHAL_ICACHE_LINE_LOCKABLE 705 # define XCHAL_ICACHE_TAG_L_SHIFT (XCHAL_ICACHE_TAG_F_SHIFT+1) 706 # define XCHAL_ICACHE_TAG_L (UINT32_C(1) << XCHAL_ICACHE_TAG_L_SHIFT) /* lock bit */ 707 #else 708 # define XCHAL_ICACHE_TAG_L_SHIFT XCHAL_ICACHE_TAG_F_SHIFT 709 # define XCHAL_ICACHE_TAG_L 0 /* no lock bit */ 710 #endif 711 /* Data cache tag bits: */ 712 #define XCHAL_DCACHE_TAG_V_SHIFT 0 713 #define XCHAL_DCACHE_TAG_V 0x1 /* valid bit */ 714 #if XCHAL_DCACHE_WAYS > 1 715 # define XCHAL_DCACHE_TAG_F_SHIFT 1 716 # define XCHAL_DCACHE_TAG_F 0x2 /* fill (LRU) bit */ 717 #else 718 # define XCHAL_DCACHE_TAG_F_SHIFT 0 719 # define XCHAL_DCACHE_TAG_F 0 /* no fill (LRU) bit */ 720 #endif 721 #if XCHAL_DCACHE_IS_WRITEBACK 722 # define XCHAL_DCACHE_TAG_D_SHIFT (XCHAL_DCACHE_TAG_F_SHIFT+1) 723 # define XCHAL_DCACHE_TAG_D (UINT32_C(1) << XCHAL_DCACHE_TAG_D_SHIFT) /* dirty bit */ 724 #else 725 # define XCHAL_DCACHE_TAG_D_SHIFT XCHAL_DCACHE_TAG_F_SHIFT 726 # define XCHAL_DCACHE_TAG_D 0 /* no dirty bit */ 727 #endif 728 #if XCHAL_DCACHE_LINE_LOCKABLE 729 # define XCHAL_DCACHE_TAG_L_SHIFT (XCHAL_DCACHE_TAG_D_SHIFT+1) 730 # define XCHAL_DCACHE_TAG_L (UINT32_C(1) << XCHAL_DCACHE_TAG_L_SHIFT) /* lock bit */ 731 #else 732 # define XCHAL_DCACHE_TAG_L_SHIFT XCHAL_DCACHE_TAG_D_SHIFT 733 # define XCHAL_DCACHE_TAG_L 0 /* no lock bit */ 734 #endif 735 736 /* Whether MEMCTL register has anything useful */ 737 #define XCHAL_USE_MEMCTL (((XCHAL_LOOP_BUFFER_SIZE > 0) || \ 738 XCHAL_DCACHE_IS_COHERENT || \ 739 XCHAL_HAVE_BRANCH_PREDICTION || \ 740 XCHAL_HAVE_ICACHE_DYN_ENABLE || \ 741 XCHAL_HAVE_DCACHE_DYN_ENABLE) && \ 742 (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0)) 743 744 /* Default MEMCTL values: */ 745 #if XCHAL_HAVE_ICACHE_DYN_ENABLE || XCHAL_HAVE_DCACHE_DYN_ENABLE || XCHAL_HAVE_CME_DOWNGRADES 746 #define XCHAL_CACHE_MEMCTL_DEFAULT UINT32_C(0xFFFFFF08) /* init all possible ways */ 747 #else 748 #define XCHAL_CACHE_MEMCTL_DEFAULT UINT32_C(0x00000000) /* nothing to do */ 749 #endif 750 751 #if XCHAL_DCACHE_IS_COHERENT 752 #define XCHAL_MEMCTL_SNOOP_EN UINT32_C(0x02) /* enable snoop */ 753 #else 754 #define XCHAL_MEMCTL_SNOOP_EN UINT32_C(0x00) /* don't enable snoop */ 755 #endif 756 757 #if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453 758 #define XCHAL_MEMCTL_L0IBUF_EN UINT32_C(0x00) /* no loop buffer or don't enable */ 759 #else 760 #define XCHAL_MEMCTL_L0IBUF_EN UINT32_C(0x01) /* enable loop buffer */ 761 #endif 762 763 #if XCHAL_HAVE_BRANCH_PREDICTION 764 #define XCHAL_MEMCTL_BP_EN UINT32_C(0x08) /* enable branch prediction */ 765 #else 766 #define XCHAL_MEMCTL_BP_EN UINT32_C(0x00) /* don't enable BP */ 767 #endif 768 769 #define XCHAL_MEMCTL_DEFAULT XCHAL_CACHE_MEMCTL_DEFAULT 770 #define XCHAL_MEMCTL_DEFAULT_POST (XCHAL_MEMCTL_SNOOP_EN | XCHAL_MEMCTL_L0IBUF_EN | XCHAL_MEMCTL_BP_EN) 771 772 773 /*---------------------------------------------------------------------- 774 MMU 775 ----------------------------------------------------------------------*/ 776 777 /* See <xtensa/config/core-matmap.h> for more details. */ 778 779 /* Indexing macros: */ 780 /* parasoft-begin-suppress MISRA2012-RULE-20_7 "Cannot parenthesize macro args here" */ 781 #define I_XCHAL_ITLB_SET(n,_what) XCHAL_ITLB_SET ## n ## _what 782 #define XCHAL_ITLB_SET(n,what) I_XCHAL_ITLB_SET(n, _ ## what ) 783 #define I_XCHAL_ITLB_SET_E(n,i,_what) XCHAL_ITLB_SET ## n ## _E ## i ## _what 784 #define XCHAL_ITLB_SET_E(n,i,what) I_XCHAL_ITLB_SET_E(n,i, _ ## what ) 785 #define I_XCHAL_DTLB_SET(n,_what) XCHAL_DTLB_SET ## n ## _what 786 #define XCHAL_DTLB_SET(n,what) I_XCHAL_DTLB_SET(n, _ ## what ) 787 #define I_XCHAL_DTLB_SET_E(n,i,_what) XCHAL_DTLB_SET ## n ## _E ## i ## _what 788 #define XCHAL_DTLB_SET_E(n,i,what) I_XCHAL_DTLB_SET_E(n,i, _ ## what ) 789 /* parasoft-end-suppress MISRA2012-RULE-20_7 "Cannot parenthesize macro args here" */ 790 /* 791 * Example use: XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES) 792 * to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set. 793 */ 794 795 /* Number of entries per autorefill way: */ 796 #define XCHAL_ITLB_ARF_ENTRIES (UINT32_C(1) << XCHAL_ITLB_ARF_ENTRIES_LOG2) 797 #define XCHAL_DTLB_ARF_ENTRIES (UINT32_C(1) << XCHAL_DTLB_ARF_ENTRIES_LOG2) 798 799 /* 800 * For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings: 801 */ 802 #if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY 803 #define XCHAL_KSEG_CACHED_VADDR UINT32_C(0xD0000000) /* virt.addr of kernel RAM cached static map */ 804 #define XCHAL_KSEG_CACHED_PADDR UINT32_C(0x00000000) /* phys.addr of kseg_cached */ 805 #define XCHAL_KSEG_CACHED_SIZE UINT32_C(0x08000000) /* size in bytes of kseg_cached (assumed power of 2!!!) */ 806 #define XCHAL_KSEG_BYPASS_VADDR UINT32_C(0xD8000000) /* virt.addr of kernel RAM bypass (uncached) static map */ 807 #define XCHAL_KSEG_BYPASS_PADDR UINT32_C(0x00000000) /* phys.addr of kseg_bypass */ 808 #define XCHAL_KSEG_BYPASS_SIZE UINT32_C(0x08000000) /* size in bytes of kseg_bypass (assumed power of 2!!!) */ 809 810 #define XCHAL_KIO_CACHED_VADDR UINT32_C(0xE0000000) /* virt.addr of kernel I/O cached static map */ 811 #define XCHAL_KIO_CACHED_PADDR UINT32_C(0xF0000000) /* phys.addr of kio_cached */ 812 #define XCHAL_KIO_CACHED_SIZE UINT32_C(0x10000000) /* size in bytes of kio_cached (assumed power of 2!!!) */ 813 #define XCHAL_KIO_BYPASS_VADDR UINT32_C(0xF0000000) /* virt.addr of kernel I/O bypass (uncached) static map */ 814 #define XCHAL_KIO_BYPASS_PADDR UINT32_C(0xF0000000) /* phys.addr of kio_bypass */ 815 #define XCHAL_KIO_BYPASS_SIZE UINT32_C(0x10000000) /* size in bytes of kio_bypass (assumed power of 2!!!) */ 816 817 #define XCHAL_SEG_MAPPABLE_VADDR UINT32_C(0x00000000) /* start of largest non-static-mapped virtual addr area */ 818 #define XCHAL_SEG_MAPPABLE_SIZE UINT32_C(0xD0000000) /* size in bytes of " */ 819 /* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size. */ 820 #endif 821 822 823 #if XCHAL_HAVE_MPU && XCHAL_HAVE_LX && XCHAL_HAVE_XEA2 824 #define XCHAL_HAVE_CACHEADRDIS 1 /* CACHEADRDIS register present */ 825 #else 826 #define XCHAL_HAVE_CACHEADRDIS 0 827 #endif 828 829 #if XCHAL_HAVE_APB && defined(XTENSA_HWVERSION_NX1_1_0) && \ 830 (XCHAL_HW_VERSION >= XTENSA_HWVERSION_NX1_1_0) 831 #define XCHAL_HAVE_PROGRAMMABLE_APB 1 832 #else 833 #define XCHAL_HAVE_PROGRAMMABLE_APB 0 834 #endif 835 836 /*---------------------------------------------------------------------- 837 MISC 838 ----------------------------------------------------------------------*/ 839 840 /* Data alignment required if used for instructions: */ 841 #if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH 842 # define XCHAL_ALIGN_MAX XCHAL_INST_FETCH_WIDTH 843 #else 844 # define XCHAL_ALIGN_MAX XCHAL_DATA_WIDTH 845 #endif 846 847 /* 848 * Names kept for backward compatibility. 849 * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases 850 * under which they are released. In the T10##.# era there was no distinction.) 851 */ 852 #define XCHAL_HW_RELEASE_MAJOR XCHAL_HW_VERSION_MAJOR 853 #define XCHAL_HW_RELEASE_MINOR XCHAL_HW_VERSION_MINOR 854 #define XCHAL_HW_RELEASE_NAME XCHAL_HW_VERSION_NAME 855 856 /* The condition for the existence of the ATOMCTL register. */ 857 #define XCHAL_HAVE_ATOMCTL (XCHAL_HAVE_EXCLUSIVE || \ 858 (XCHAL_HAVE_S32C1I && \ 859 (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0))) 860 861 862 /*---------------------------------------------------------------------- 863 COPROCESSORS and EXTRA STATE 864 ----------------------------------------------------------------------*/ 865 866 #define XCHAL_EXTRA_SA_SIZE XCHAL_NCP_SA_SIZE 867 #define XCHAL_EXTRA_SA_ALIGN XCHAL_NCP_SA_ALIGN 868 #define XCHAL_CPEXTRA_SA_SIZE XCHAL_TOTAL_SA_SIZE 869 #define XCHAL_CPEXTRA_SA_ALIGN XCHAL_TOTAL_SA_ALIGN 870 871 #if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__) 872 873 /* Invoked at start of save area load/store sequence macro to setup macro 874 * internal offsets. Not usually invoked directly. 875 * continue 0 for 1st sequence, 1 for subsequent consecutive ones. 876 * totofs offset from original ptr to next load/store location. 877 */ 878 .macro xchal_sa_start continue totofs 879 .ifeq \continue 880 .set .Lxchal_pofs_, 0 /* offset from original ptr to current \ptr */ 881 .set .Lxchal_ofs_, 0 /* offset from current \ptr to next load/store location */ 882 .endif 883 .if \totofs + 1 /* if totofs specified (not -1) */ 884 .set .Lxchal_ofs_, \totofs - .Lxchal_pofs_ /* specific offset from original ptr */ 885 .endif 886 .endm 887 888 /* Align portion of save area and bring ptr in range if necessary. 889 * Used by save area load/store sequences. Not usually invoked directly. 890 * Allows combining multiple (sub-)sequences arbitrarily. 891 * ptr pointer to save area (may be off, see .Lxchal_pofs_) 892 * minofs,maxofs range of offset from cur ptr to next load/store loc; 893 * minofs <= 0 <= maxofs (0 must always be valid offset) 894 * range must be within +/- 30kB or so. 895 * ofsalign alignment granularity of minofs .. maxofs (pow of 2) 896 * (restriction on offset from ptr to next load/store loc) 897 * totalign align from orig ptr to next load/store loc (pow of 2) 898 */ 899 .macro xchal_sa_align ptr minofs maxofs ofsalign totalign 900 /* First align where we start accessing the next register 901 * per \totalign relative to original ptr (i.e. start of the save area): 902 */ 903 .set .Lxchal_ofs_, ((.Lxchal_pofs_ + .Lxchal_ofs_ + \totalign - 1) & -\totalign) - .Lxchal_pofs_ 904 /* If necessary, adjust \ptr to bring .Lxchal_ofs_ in acceptable range: */ 905 .if (((\maxofs) - .Lxchal_ofs_) & 0xC0000000) | ((.Lxchal_ofs_ - (\minofs)) & 0xC0000000) | (.Lxchal_ofs_ & (\ofsalign-1)) 906 .set .Ligmask, 0xFFFFFFFF /* TODO: optimize to addmi, per aligns and .Lxchal_ofs_ */ 907 addi.a \ptr, \ptr, (.Lxchal_ofs_ & .Ligmask) 908 .set .Lxchal_pofs_, .Lxchal_pofs_ + (.Lxchal_ofs_ & .Ligmask) 909 .set .Lxchal_ofs_, (.Lxchal_ofs_ & ~.Ligmask) 910 .endif 911 .endm 912 /* 913 * We could optimize for addi to expand to only addmi instead of 914 * "addmi;addi", where possible. Here's a partial example how: 915 * .set .Lmaxmask, -(\ofsalign) & -(\totalign) 916 * .if (((\maxofs) + ~.Lmaxmask + 1) & 0xFFFFFF00) && ((.Lxchal_ofs_ & ~.Lmaxmask) == 0) 917 * .set .Ligmask, 0xFFFFFF00 918 * .elif ... ditto for negative ofs range ... 919 * .set .Ligmask, 0xFFFFFF00 920 * .set ... adjust per offset ... 921 * .else 922 * .set .Ligmask, 0xFFFFFFFF 923 * .endif 924 */ 925 926 /* Invoke this after xchal_XXX_{load,store} macros to restore \ptr. */ 927 .macro xchal_sa_ptr_restore ptr 928 .if .Lxchal_pofs_ 929 addi.a \ptr, \ptr, - .Lxchal_pofs_ 930 .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ 931 .set .Lxchal_pofs_, 0 932 .endif 933 .endm 934 935 /* 936 * Use as eg: 937 * xchal_atmps_store a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 938 * xchal_ncp_load a2, a0,a3,a4,a5 939 * xchal_atmps_load a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5 940 * 941 * Specify only the ARs you *haven't* saved/restored already, up to 4. 942 * They *must* be the *last* ARs (in same order) specified to save area 943 * load/store sequences. In the example above, a0 and a3 were already 944 * saved/restored and unused (thus available) but a4 and a5 were not. 945 */ 946 #define xchal_atmps_store xchal_atmps_loadstore s32i, 947 #define xchal_atmps_load xchal_atmps_loadstore l32i, 948 .macro xchal_atmps_loadstore inst ptr offset nreq aa=0 ab=0 ac=0 ad=0 949 .set .Lnsaved_, 0 950 .irp reg,\aa,\ab,\ac,\ad 951 .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif 952 .endr 953 .set .Laofs_, 0 954 .irp reg,\aa,\ab,\ac,\ad 955 .ifgt (\nreq)-.Lnsaved_ 956 \inst \reg, \ptr, .Laofs_+\offset 957 .set .Laofs_,.Laofs_+4 958 .set .Lnsaved_,.Lnsaved_+1 959 .endif 960 .endr 961 .endm 962 963 #define xchal_extratie_load xchal_ncptie_load 964 #define xchal_extratie_store xchal_ncptie_store 965 #define xchal_extratie_load_a2 xchal_ncptie_load a2,a3,a4,a5,a6 966 #define xchal_extratie_store_a2 xchal_ncptie_store a2,a3,a4,a5,a6 967 #define xchal_extra_load xchal_ncp_load 968 #define xchal_extra_store xchal_ncp_store 969 #define xchal_extra_load_a2 xchal_ncp_load a2,a3,a4,a5,a6 970 #define xchal_extra_store_a2 xchal_ncp_store a2,a3,a4,a5,a6 971 #define xchal_extra_load_funcbody xchal_ncp_load a2,a3,a4,a5,a6 972 #define xchal_extra_store_funcbody xchal_ncp_store a2,a3,a4,a5,a6 973 #define xchal_cp0_store_a2 xchal_cp0_store a2,a3,a4,a5,a6 974 #define xchal_cp0_load_a2 xchal_cp0_load a2,a3,a4,a5,a6 975 #define xchal_cp1_store_a2 xchal_cp1_store a2,a3,a4,a5,a6 976 #define xchal_cp1_load_a2 xchal_cp1_load a2,a3,a4,a5,a6 977 #define xchal_cp2_store_a2 xchal_cp2_store a2,a3,a4,a5,a6 978 #define xchal_cp2_load_a2 xchal_cp2_load a2,a3,a4,a5,a6 979 #define xchal_cp3_store_a2 xchal_cp3_store a2,a3,a4,a5,a6 980 #define xchal_cp3_load_a2 xchal_cp3_load a2,a3,a4,a5,a6 981 #define xchal_cp4_store_a2 xchal_cp4_store a2,a3,a4,a5,a6 982 #define xchal_cp4_load_a2 xchal_cp4_load a2,a3,a4,a5,a6 983 #define xchal_cp5_store_a2 xchal_cp5_store a2,a3,a4,a5,a6 984 #define xchal_cp5_load_a2 xchal_cp5_load a2,a3,a4,a5,a6 985 #define xchal_cp6_store_a2 xchal_cp6_store a2,a3,a4,a5,a6 986 #define xchal_cp6_load_a2 xchal_cp6_load a2,a3,a4,a5,a6 987 #define xchal_cp7_store_a2 xchal_cp7_store a2,a3,a4,a5,a6 988 #define xchal_cp7_load_a2 xchal_cp7_load a2,a3,a4,a5,a6 989 990 /* Empty placeholder macros for undefined coprocessors: */ 991 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0 992 # if XCHAL_CP0_SA_SIZE == 0 993 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 994 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 995 # endif 996 # if XCHAL_CP1_SA_SIZE == 0 997 .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 998 .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 999 # endif 1000 # if XCHAL_CP2_SA_SIZE == 0 1001 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1002 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1003 # endif 1004 # if XCHAL_CP3_SA_SIZE == 0 1005 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1006 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1007 # endif 1008 # if XCHAL_CP4_SA_SIZE == 0 1009 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1010 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1011 # endif 1012 # if XCHAL_CP5_SA_SIZE == 0 1013 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1014 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1015 # endif 1016 # if XCHAL_CP6_SA_SIZE == 0 1017 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1018 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1019 # endif 1020 # if XCHAL_CP7_SA_SIZE == 0 1021 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 1022 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 1023 # endif 1024 #endif 1025 1026 /******************** 1027 * Macros to create functions that save and restore the state of *any* TIE 1028 * coprocessor (by dynamic index). 1029 */ 1030 1031 /* 1032 * Macro that expands to the body of a function 1033 * that stores the selected coprocessor's state (registers etc). 1034 * Entry: a2 = ptr to save area in which to save cp state 1035 * a3 = coprocessor number 1036 * Exit: any register a2-a15 (?) may have been clobbered. 1037 */ 1038 .macro xchal_cpi_store_funcbody 1039 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) 1040 # if XCHAL_CP0_SA_SIZE 1041 bnez a3, 99f 1042 xchal_cp0_store_a2 1043 # if (XCHAL_CP_NUM > 1) 1044 j 90f 1045 # endif 1046 99: 1047 # endif 1048 # if XCHAL_CP1_SA_SIZE 1049 bnei a3, 1, 99f 1050 xchal_cp1_store_a2 1051 # if (XCHAL_CP_NUM > 1) 1052 j 90f 1053 # endif 1054 99: 1055 # endif 1056 # if XCHAL_CP2_SA_SIZE 1057 bnei a3, 2, 99f 1058 xchal_cp2_store_a2 1059 # if (XCHAL_CP_NUM > 1) 1060 j 90f 1061 # endif 1062 99: 1063 # endif 1064 # if XCHAL_CP3_SA_SIZE 1065 bnei a3, 3, 99f 1066 xchal_cp3_store_a2 1067 # if (XCHAL_CP_NUM > 1) 1068 j 90f 1069 # endif 1070 99: 1071 # endif 1072 # if XCHAL_CP4_SA_SIZE 1073 bnei a3, 4, 99f 1074 xchal_cp4_store_a2 1075 # if (XCHAL_CP_NUM > 1) 1076 j 90f 1077 # endif 1078 99: 1079 # endif 1080 # if XCHAL_CP5_SA_SIZE 1081 bnei a3, 5, 99f 1082 xchal_cp5_store_a2 1083 # if (XCHAL_CP_NUM > 1) 1084 j 90f 1085 # endif 1086 99: 1087 # endif 1088 # if XCHAL_CP6_SA_SIZE 1089 bnei a3, 6, 99f 1090 xchal_cp6_store_a2 1091 # if (XCHAL_CP_NUM > 1) 1092 j 90f 1093 # endif 1094 99: 1095 # endif 1096 # if XCHAL_CP7_SA_SIZE 1097 bnei a3, 7, 99f 1098 xchal_cp7_store_a2 1099 99: 1100 # endif 1101 90: 1102 #endif 1103 .endm 1104 1105 /* 1106 * Macro that expands to the body of a function 1107 * that loads the selected coprocessor's state (registers etc). 1108 * Entry: a2 = ptr to save area from which to restore cp state 1109 * a3 = coprocessor number 1110 * Exit: any register a2-a15 (?) may have been clobbered. 1111 */ 1112 .macro xchal_cpi_load_funcbody 1113 #if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) 1114 # if XCHAL_CP0_SA_SIZE 1115 bnez a3, 99f 1116 xchal_cp0_load_a2 1117 # if (XCHAL_CP_NUM > 1) 1118 j 90f 1119 # endif 1120 99: 1121 # endif 1122 # if XCHAL_CP1_SA_SIZE 1123 bnei a3, 1, 99f 1124 xchal_cp1_load_a2 1125 # if (XCHAL_CP_NUM > 1) 1126 j 90f 1127 # endif 1128 99: 1129 # endif 1130 # if XCHAL_CP2_SA_SIZE 1131 bnei a3, 2, 99f 1132 xchal_cp2_load_a2 1133 # if (XCHAL_CP_NUM > 1) 1134 j 90f 1135 # endif 1136 99: 1137 # endif 1138 # if XCHAL_CP3_SA_SIZE 1139 bnei a3, 3, 99f 1140 xchal_cp3_load_a2 1141 # if (XCHAL_CP_NUM > 1) 1142 j 90f 1143 # endif 1144 99: 1145 # endif 1146 # if XCHAL_CP4_SA_SIZE 1147 bnei a3, 4, 99f 1148 xchal_cp4_load_a2 1149 # if (XCHAL_CP_NUM > 1) 1150 j 90f 1151 # endif 1152 99: 1153 # endif 1154 # if XCHAL_CP5_SA_SIZE 1155 bnei a3, 5, 99f 1156 xchal_cp5_load_a2 1157 # if (XCHAL_CP_NUM > 1) 1158 j 90f 1159 # endif 1160 99: 1161 # endif 1162 # if XCHAL_CP6_SA_SIZE 1163 bnei a3, 6, 99f 1164 xchal_cp6_load_a2 1165 # if (XCHAL_CP_NUM > 1) 1166 j 90f 1167 # endif 1168 99: 1169 # endif 1170 # if XCHAL_CP7_SA_SIZE 1171 bnei a3, 7, 99f 1172 xchal_cp7_load_a2 1173 99: 1174 # endif 1175 90: 1176 #endif 1177 .endm 1178 1179 #endif /*_ASMLANGUAGE or __ASSEMBLER__*/ 1180 1181 1182 /* Other default macros for undefined coprocessors: */ 1183 #ifndef XCHAL_CP0_NAME 1184 # define XCHAL_CP0_NAME 0 1185 # define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM 0 1186 # define XCHAL_CP0_SA_CONTENTS_LIBDB /* empty */ 1187 #endif 1188 #ifndef XCHAL_CP1_NAME 1189 # define XCHAL_CP1_NAME 0 1190 # define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM 0 1191 # define XCHAL_CP1_SA_CONTENTS_LIBDB /* empty */ 1192 #endif 1193 #ifndef XCHAL_CP2_NAME 1194 # define XCHAL_CP2_NAME 0 1195 # define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM 0 1196 # define XCHAL_CP2_SA_CONTENTS_LIBDB /* empty */ 1197 #endif 1198 #ifndef XCHAL_CP3_NAME 1199 # define XCHAL_CP3_NAME 0 1200 # define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM 0 1201 # define XCHAL_CP3_SA_CONTENTS_LIBDB /* empty */ 1202 #endif 1203 #ifndef XCHAL_CP4_NAME 1204 # define XCHAL_CP4_NAME 0 1205 # define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM 0 1206 # define XCHAL_CP4_SA_CONTENTS_LIBDB /* empty */ 1207 #endif 1208 #ifndef XCHAL_CP5_NAME 1209 # define XCHAL_CP5_NAME 0 1210 # define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM 0 1211 # define XCHAL_CP5_SA_CONTENTS_LIBDB /* empty */ 1212 #endif 1213 #ifndef XCHAL_CP6_NAME 1214 # define XCHAL_CP6_NAME 0 1215 # define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM 0 1216 # define XCHAL_CP6_SA_CONTENTS_LIBDB /* empty */ 1217 #endif 1218 #ifndef XCHAL_CP7_NAME 1219 # define XCHAL_CP7_NAME 0 1220 # define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM 0 1221 # define XCHAL_CP7_SA_CONTENTS_LIBDB /* empty */ 1222 #endif 1223 1224 #if XCHAL_CP_MASK == 0 1225 /* Filler info for unassigned coprocessors, to simplify arrays etc: */ 1226 #define XCHAL_CP0_SA_SIZE 0 1227 #define XCHAL_CP0_SA_ALIGN 1 1228 #define XCHAL_CP1_SA_SIZE 0 1229 #define XCHAL_CP1_SA_ALIGN 1 1230 #define XCHAL_CP2_SA_SIZE 0 1231 #define XCHAL_CP2_SA_ALIGN 1 1232 #define XCHAL_CP3_SA_SIZE 0 1233 #define XCHAL_CP3_SA_ALIGN 1 1234 #define XCHAL_CP4_SA_SIZE 0 1235 #define XCHAL_CP4_SA_ALIGN 1 1236 #define XCHAL_CP5_SA_SIZE 0 1237 #define XCHAL_CP5_SA_ALIGN 1 1238 #define XCHAL_CP6_SA_SIZE 0 1239 #define XCHAL_CP6_SA_ALIGN 1 1240 #define XCHAL_CP7_SA_SIZE 0 1241 #define XCHAL_CP7_SA_ALIGN 1 1242 #endif 1243 1244 1245 /* Indexing macros: */ 1246 #define I_XCHAL_CP_SA_SIZE(n) XCHAL_CP ## n ## _SA_SIZE 1247 #define XCHAL_CP_SA_SIZE(n) I_XCHAL_CP_SA_SIZE(n) /* n = 0 .. 7 */ 1248 #define I_XCHAL_CP_SA_ALIGN(n) XCHAL_CP ## n ## _SA_ALIGN 1249 #define XCHAL_CP_SA_ALIGN(n) I_XCHAL_CP_SA_ALIGN(n) /* n = 0 .. 7 */ 1250 1251 /* Link-time HAL global variables that report coprocessor numbers by name 1252 (names are case-preserved from the original TIE): */ 1253 #if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__) 1254 # define I_XCJOIN(a,b) a ## b /* parasoft-suppress MISRA2012-RULE-20_7 "Cannot parenthesize macro args here" */ 1255 # define XCJOIN(a,b) I_XCJOIN(a,b) /* parasoft-suppress MISRA2012-RULE-20_7 "Cannot parenthesize macro args here" */ 1256 1257 # ifdef XCHAL_CP0_NAME 1258 extern const uint8_t XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT); 1259 extern const uint32_t XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT); 1260 # endif 1261 # ifdef XCHAL_CP1_NAME 1262 extern const uint8_t XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT); 1263 extern const uint32_t XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT); 1264 # endif 1265 # ifdef XCHAL_CP2_NAME 1266 extern const uint8_t XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT); 1267 extern const uint32_t XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT); 1268 # endif 1269 # ifdef XCHAL_CP3_NAME 1270 extern const uint8_t XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT); 1271 extern const uint32_t XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT); 1272 # endif 1273 # ifdef XCHAL_CP4_NAME 1274 extern const uint8_t XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT); 1275 extern const uint32_t XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT); 1276 # endif 1277 # ifdef XCHAL_CP5_NAME 1278 extern const uint8_t XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT); 1279 extern const uint32_t XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT); 1280 # endif 1281 # ifdef XCHAL_CP6_NAME 1282 extern const uint8_t XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT); 1283 extern const uint32_t XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT); 1284 # endif 1285 # ifdef XCHAL_CP7_NAME 1286 extern const uint8_t XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT); 1287 extern const uint32_t XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT); 1288 # endif 1289 #endif 1290 1291 1292 1293 1294 /*---------------------------------------------------------------------- 1295 DERIVED 1296 ----------------------------------------------------------------------*/ 1297 1298 #if XCHAL_HAVE_BE 1299 #define XCHAL_INST_ILLN 0xD60F /* 2-byte illegal instruction, msb-first */ 1300 #define XCHAL_INST_ILLN_BYTE0 0xD6 /* 2-byte illegal instruction, 1st byte */ 1301 #define XCHAL_INST_ILLN_BYTE1 0x0F /* 2-byte illegal instruction, 2nd byte */ 1302 #else 1303 #define XCHAL_INST_ILLN 0xF06D /* 2-byte illegal instruction, lsb-first */ 1304 #define XCHAL_INST_ILLN_BYTE0 0x6D /* 2-byte illegal instruction, 1st byte */ 1305 #define XCHAL_INST_ILLN_BYTE1 0xF0 /* 2-byte illegal instruction, 2nd byte */ 1306 #endif 1307 /* Belongs in xtensa/hal.h: */ 1308 #define XTHAL_INST_ILL 0x000000 /* 3-byte illegal instruction */ 1309 1310 1311 /* 1312 * Because information as to exactly which hardware version is targeted 1313 * by a given software build is not always available, compile-time HAL 1314 * Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE): 1315 * (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases 1316 * under which they are released. In the T10##.# era there was no distinction.) 1317 */ 1318 /* parasoft-begin-suppress MISRA2012-RULE-20_7 "Cannot parenthesize macro args here" */ 1319 #if XCHAL_HW_CONFIGID_RELIABLE 1320 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) (XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) 1321 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) (XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) 1322 # define XCHAL_HW_RELEASE_AT(major,minor) (XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0) 1323 # define XCHAL_HW_RELEASE_MAJOR_AT(major) ((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0) 1324 #else 1325 # define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor) ( ((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 \ 1326 : ((major) > 1050 && XCHAL_HAVE_XEA1) ? 1 \ 1327 : XTHAL_MAYBE ) 1328 # define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor) ( ((major) >= 2000 && XCHAL_HAVE_XEA1) ? 0 \ 1329 : (XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 \ 1330 : XTHAL_MAYBE ) 1331 # define XCHAL_HW_RELEASE_AT(major,minor) ( (((major) < 1040 && XCHAL_HAVE_XEA2) || \ 1332 ((major) >= 2000 && XCHAL_HAVE_XEA1)) ? 0 : XTHAL_MAYBE) 1333 # define XCHAL_HW_RELEASE_MAJOR_AT(major) XCHAL_HW_RELEASE_AT(major,0) 1334 #endif 1335 /* parasoft-end-suppress MISRA2012-RULE-20_7 "Cannot parenthesize macro args here" */ 1336 1337 /* 1338 * Erratum present in RH.0 hardware and RH.1 hardware. 1339 */ 1340 #if (XCHAL_HW_VERSION == XTENSA_HWVERSION_RH_2016_0) || (XCHAL_HW_VERSION == XTENSA_HWVERSION_RH_2016_1) 1341 #define XCHAL_RH01_ERRATUM 1 1342 #else 1343 #define XCHAL_RH01_ERRATUM 0 1344 #endif 1345 1346 /* 1347 * Erratum present in RH.0 through RH.2 hardware. 1348 */ 1349 #if (XCHAL_HW_VERSION == XTENSA_HWVERSION_RH_2016_0) || \ 1350 (XCHAL_HW_VERSION == XTENSA_HWVERSION_RH_2016_1) || \ 1351 (XCHAL_HW_VERSION == XTENSA_HWVERSION_RH_2017_2) 1352 #define XCHAL_RH012_ERRATUM 1 1353 #else 1354 #define XCHAL_RH012_ERRATUM 0 1355 #endif 1356 1357 1358 #endif /*XTENSA_CONFIG_CORE_H*/ 1359 1360
