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Searched refs:XCHAL_PREFETCH_ENTRIES (Results 1 – 16 of 16) sorted by relevance

/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h253 #define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h253 #define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h253 #define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h253 #define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h246 #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h226 #define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h226 #define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h307 #define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h307 #define XCHAL_PREFETCH_ENTRIES 8 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h300 #define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h251 #define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h295 #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ macro
Dcore.h665 #elif ((XCHAL_PREFETCH_ENTRIES >= 16) && XCHAL_HAVE_CACHE_BLOCKOPS)
667 #elif ((XCHAL_PREFETCH_ENTRIES >= 8) && XCHAL_HAVE_CACHE_BLOCKOPS)
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h307 #define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h305 #define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */ macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h768 #elif ((XCHAL_PREFETCH_ENTRIES >= 16) && XCHAL_HAVE_CACHE_BLOCKOPS)
770 #elif ((XCHAL_PREFETCH_ENTRIES >= 8) && XCHAL_HAVE_CACHE_BLOCKOPS)