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Searched refs:XCHAL_NUM_INTERRUPTS (Results 1 – 18 of 18) sorted by relevance

/hal_xtensa-latest/include/xtensa/config/
Dcore.h339 #if XCHAL_NUM_INTERRUPTS == 0
343 #if XCHAL_NUM_INTERRUPTS <= 1
347 #if XCHAL_NUM_INTERRUPTS <= 2
351 #if XCHAL_NUM_INTERRUPTS <= 3
355 #if XCHAL_NUM_INTERRUPTS <= 4
359 #if XCHAL_NUM_INTERRUPTS <= 5
363 #if XCHAL_NUM_INTERRUPTS <= 6
367 #if XCHAL_NUM_INTERRUPTS <= 7
371 #if XCHAL_NUM_INTERRUPTS <= 8
375 #if XCHAL_NUM_INTERRUPTS <= 9
[all …]
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore.h370 #if XCHAL_NUM_INTERRUPTS == 0
374 #if XCHAL_NUM_INTERRUPTS <= 1
378 #if XCHAL_NUM_INTERRUPTS <= 2
382 #if XCHAL_NUM_INTERRUPTS <= 3
386 #if XCHAL_NUM_INTERRUPTS <= 4
390 #if XCHAL_NUM_INTERRUPTS <= 5
394 #if XCHAL_NUM_INTERRUPTS <= 6
398 #if XCHAL_NUM_INTERRUPTS <= 7
402 #if XCHAL_NUM_INTERRUPTS <= 8
406 #if XCHAL_NUM_INTERRUPTS <= 9
[all …]
Dcore-isa.h425 #define XCHAL_NUM_INTERRUPTS 23 /* number of interrupts */ macro
/hal_xtensa-latest/src/hal/
Dinterrupts.c165 const unsigned char Xthal_num_interrupts = XCHAL_NUM_INTERRUPTS;
531 if( (unsigned)intnum >= XCHAL_NUM_INTERRUPTS || (unsigned)vpri > 0xFF ) in xthal_set_int_vpri()
600 if( (unsigned)intnum >= XCHAL_NUM_INTERRUPTS ) in xthal_get_int_vpri()
705 if( (unsigned)intnum >= XCHAL_NUM_INTERRUPTS ) in xthal_tram_set_sync()
797 const unsigned Xthal_num_ints = XCHAL_NUM_INTERRUPTS;
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h233 #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h335 #define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h335 #define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h335 #define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h358 #define XCHAL_NUM_INTERRUPTS 21 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h354 #define XCHAL_NUM_INTERRUPTS 22 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h323 #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h323 #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h446 #define XCHAL_NUM_INTERRUPTS 9 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h446 #define XCHAL_NUM_INTERRUPTS 9 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h418 #define XCHAL_NUM_INTERRUPTS 25 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h350 #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h446 #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h461 #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ macro