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Searched refs:XCHAL_INT5_LEVEL (Results 1 – 18 of 18) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h265 #define XCHAL_INT5_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h367 #define XCHAL_INT5_LEVEL 2 macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h367 #define XCHAL_INT5_LEVEL 2 macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h367 #define XCHAL_INT5_LEVEL 2 macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h390 #define XCHAL_INT5_LEVEL 2 macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h386 #define XCHAL_INT5_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h355 #define XCHAL_INT5_LEVEL 2 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h355 #define XCHAL_INT5_LEVEL 2 macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h481 #define XCHAL_INT5_LEVEL 3 macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h481 #define XCHAL_INT5_LEVEL 3 macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h453 #define XCHAL_INT5_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h382 #define XCHAL_INT5_LEVEL 3 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h460 #define XCHAL_INT5_LEVEL 1 macro
Dcore.h286 XCHAL_SEP XCHAL_INT5_LEVEL \
391 # define XCHAL_INT5_LEVEL 0 macro
/hal_xtensa-latest/src/hal/
Dinterrupts.c314 DEFAULT_INTVPRI( XCHAL_INT5_LEVEL ),
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h482 #define XCHAL_INT5_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h496 #define XCHAL_INT5_LEVEL 1 macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h249 XCHAL_SEP XCHAL_INT5_LEVEL \
360 # define XCHAL_INT5_LEVEL 0 macro