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Searched refs:XCHAL_INT21_LEVEL (Results 1 – 12 of 12) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h281 #define XCHAL_INT21_LEVEL 3 macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h402 #define XCHAL_INT21_LEVEL 3 macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h371 #define XCHAL_INT21_LEVEL 2 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h371 #define XCHAL_INT21_LEVEL 2 macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h469 #define XCHAL_INT21_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h398 #define XCHAL_INT21_LEVEL 2 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h476 #define XCHAL_INT21_LEVEL 3 macro
Dcore.h302 XCHAL_SEP XCHAL_INT21_LEVEL \
455 # define XCHAL_INT21_LEVEL 0 macro
/hal_xtensa-latest/src/hal/
Dinterrupts.c330 DEFAULT_INTVPRI( XCHAL_INT21_LEVEL ),
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h498 #define XCHAL_INT21_LEVEL 2 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h512 #define XCHAL_INT21_LEVEL 2 macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h265 XCHAL_SEP XCHAL_INT21_LEVEL \
424 # define XCHAL_INT21_LEVEL 0 macro