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Searched refs:XCHAL_INT0_LEVEL (Results 1 – 18 of 18) sorted by relevance

/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h260 #define XCHAL_INT0_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h362 #define XCHAL_INT0_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h362 #define XCHAL_INT0_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h362 #define XCHAL_INT0_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h385 #define XCHAL_INT0_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h381 #define XCHAL_INT0_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h350 #define XCHAL_INT0_LEVEL 5 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h350 #define XCHAL_INT0_LEVEL 5 macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h476 #define XCHAL_INT0_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h476 #define XCHAL_INT0_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h448 #define XCHAL_INT0_LEVEL 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h377 #define XCHAL_INT0_LEVEL 5 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h455 #define XCHAL_INT0_LEVEL 1 macro
Dcore.h281 #define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \
371 # define XCHAL_INT0_LEVEL 0 macro
/hal_xtensa-latest/src/hal/
Dinterrupts.c309 DEFAULT_INTVPRI( XCHAL_INT0_LEVEL ),
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h477 #define XCHAL_INT0_LEVEL 5 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h491 #define XCHAL_INT0_LEVEL 5 macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h244 #define XCHAL_INT_LEVELS XCHAL_INT0_LEVEL \
340 # define XCHAL_INT0_LEVEL 0 macro