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Searched refs:XCHAL_ICACHE_LINE_LOCKABLE (Results 1 – 21 of 21) sorted by relevance

/hal_xtensa-latest/src/hal/
Dcache.c51 const unsigned char Xthal_icache_line_lockable = XCHAL_ICACHE_LINE_LOCKABLE;
Dcache_asm.S453 # if XCHAL_ICACHE_LINE_LOCKABLE
/hal_xtensa-latest/include/xtensa/
Dcacheasm.h372 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
388 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
408 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
424 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
441 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
Dcore-macros.h115 #if XCHAL_ICACHE_SIZE > 0 && XCHAL_ICACHE_LINE_LOCKABLE
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h197 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h295 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h295 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h295 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h295 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h288 #define XCHAL_ICACHE_LINE_LOCKABLE 0 macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h265 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h265 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h375 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h375 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h368 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h293 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h354 #define XCHAL_ICACHE_LINE_LOCKABLE 0 macro
Dcore.h704 #if XCHAL_ICACHE_LINE_LOCKABLE
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h375 #define XCHAL_ICACHE_LINE_LOCKABLE 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h373 #define XCHAL_ICACHE_LINE_LOCKABLE 0 macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h807 #if XCHAL_ICACHE_LINE_LOCKABLE