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Searched refs:XCHAL_HW_MIN_VERSION (Results 1 – 20 of 20) sorted by relevance

/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore.h141 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \
156 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) || \
158 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2) \
661 #if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0
663 #elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0
742 (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
859 (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)))
Dcore-isa.h264 #define XCHAL_HW_MIN_VERSION 281020 /* earliest targeted hw */ macro
/hal_xtensa-latest/include/xtensa/config/
Dcore.h106 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \
121 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) || \
123 XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2) \
764 #if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0
766 #elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0
844 (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
/hal_xtensa-latest/include/xtensa/
Dxtruntime-core-state.h88 #if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) /* have ATOMCTL ? */
Dcacheasm.h509 # if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
543 # if XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0
/hal_xtensa-latest/zephyr/soc/dc233c/xtensa/config/
Dcore-isa.h147 #define XCHAL_HW_MIN_VERSION 230000 /* earliest targeted hw */ macro
/hal_xtensa-latest/src/hal/
Dcache_asm.S844 # if XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RC_2010_1 /* for erratum #325 */
879 # if XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RC_2010_1 /* for erratum #325 */
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h229 #define XCHAL_HW_MIN_VERSION 260001 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h229 #define XCHAL_HW_MIN_VERSION 260001 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h229 #define XCHAL_HW_MIN_VERSION 240005 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h229 #define XCHAL_HW_MIN_VERSION 260003 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h222 #define XCHAL_HW_MIN_VERSION 270004 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/mimx8ml8/xtensa/config/
Dcore-isa.h202 #define XCHAL_HW_MIN_VERSION 260004 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx_adsp/xtensa/config/
Dcore-isa.h202 #define XCHAL_HW_MIN_VERSION 260004 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h273 #define XCHAL_HW_MIN_VERSION 281070 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h273 #define XCHAL_HW_MIN_VERSION 281100 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h266 #define XCHAL_HW_MIN_VERSION 281010 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h227 #define XCHAL_HW_MIN_VERSION 270008 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h273 #define XCHAL_HW_MIN_VERSION 260004 /* earliest targeted hw */ macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h271 #define XCHAL_HW_MIN_VERSION 260004 /* earliest targeted hw */ macro