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Searched refs:XCHAL_HAVE_MPU (Results 1 – 20 of 20) sorted by relevance

/hal_xtensa-latest/src/hal/
Dmpu.c25 #if XCHAL_HAVE_MPU
1314 #if XCHAL_HAVE_MPU in xthal_is_kernel_readable()
1323 #if XCHAL_HAVE_MPU in xthal_is_kernel_writeable()
1332 #if XCHAL_HAVE_MPU in xthal_is_kernel_executable()
1341 #if XCHAL_HAVE_MPU in xthal_is_user_readable()
1350 #if XCHAL_HAVE_MPU in xthal_is_user_writeable()
1359 #if XCHAL_HAVE_MPU in xthal_is_user_executable()
1373 #if XCHAL_HAVE_MPU in xthal_is_cacheable()
1382 #if XCHAL_HAVE_MPU in xthal_is_writeback()
1391 #if XCHAL_HAVE_MPU in xthal_is_device()
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Dset_region_translate.c25 #if XCHAL_HAVE_XEA2 && (!XCHAL_HAVE_MPU)
122 #if XCHAL_HAVE_MPU in xthal_set_region_translation_raw()
169 #if XCHAL_HAVE_MPU in xthal_v2p()
399 #if XCHAL_HAVE_XEA2 & !XCHAL_HAVE_MPU in xthal_set_region_translation()
518 #if XCHAL_HAVE_XEA2 & !XCHAL_HAVE_MPU in xthal_invalidate_region()
Dattribute.c170 #if XCHAL_HAVE_MPU in xthal_set_region_attribute()
Dmisc.c97 #if XCHAL_HAVE_MPU
/hal_xtensa-latest/include/xtensa/
Dmpuasm.h41 #if XCHAL_HAVE_MPU
98 #if XCHAL_HAVE_MPU
Dcore-macros.h487 #if XCHAL_HAVE_MPU in xthal_mpu_set_entry()
496 #if XCHAL_HAVE_MPU in xthal_mpu_set_entry_()
Dxtruntime-core-state.h162 #if XCHAL_HAVE_MPU
/hal_xtensa-latest/zephyr/soc/intel_cnl_adsp/xtensa/config/
Dcore-isa.h594 #define XCHAL_HAVE_MPU 0 macro
/hal_xtensa-latest/zephyr/soc/intel_icl_adsp/xtensa/config/
Dcore-isa.h594 #define XCHAL_HAVE_MPU 0 macro
/hal_xtensa-latest/zephyr/soc/intel_apl_adsp/xtensa/config/
Dcore-isa.h594 #define XCHAL_HAVE_MPU 0 macro
/hal_xtensa-latest/zephyr/soc/intel_tgl_adsp/xtensa/config/
Dcore-isa.h617 #define XCHAL_HAVE_MPU 0 macro
/hal_xtensa-latest/zephyr/soc/sample_controller/xtensa/config/
Dcore-isa.h630 #define XCHAL_HAVE_MPU 0 macro
/hal_xtensa-latest/zephyr/soc/intel_ace15_mtpm/xtensa/config/
Dcore-isa.h687 #define XCHAL_HAVE_MPU 0 macro
/hal_xtensa-latest/zephyr/soc/intel_ace30_ptl/xtensa/config/
Dcore-isa.h687 #define XCHAL_HAVE_MPU 0 macro
/hal_xtensa-latest/zephyr/soc/mt8195_adsp/xtensa/config/
Dcore-isa.h710 #define XCHAL_HAVE_MPU 1 macro
/hal_xtensa-latest/zephyr/soc/nxp_imx8ulp_adsp/xtensa/config/
Dcore-isa.h659 #define XCHAL_HAVE_MPU 0 macro
/hal_xtensa-latest/zephyr/soc/sample_controller32/xtensa/config/
Dcore-isa.h725 #define XCHAL_HAVE_MPU 1 macro
Dcore.h823 #if XCHAL_HAVE_MPU && XCHAL_HAVE_LX && XCHAL_HAVE_XEA2
/hal_xtensa-latest/zephyr/soc/nxp_rt600_adsp/xtensa/config/
Dcore-isa.h782 #define XCHAL_HAVE_MPU 0 macro
/hal_xtensa-latest/zephyr/soc/nxp_rt500_adsp/xtensa/config/
Dcore-isa.h797 #define XCHAL_HAVE_MPU 0 macro